JPH0311737A - Solid phase epitaxy - Google Patents

Solid phase epitaxy

Info

Publication number
JPH0311737A
JPH0311737A JP14771089A JP14771089A JPH0311737A JP H0311737 A JPH0311737 A JP H0311737A JP 14771089 A JP14771089 A JP 14771089A JP 14771089 A JP14771089 A JP 14771089A JP H0311737 A JPH0311737 A JP H0311737A
Authority
JP
Japan
Prior art keywords
film
electrode
single crystal
electrode film
solid phase
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14771089A
Other languages
Japanese (ja)
Inventor
Seiichi Iwamatsu
誠一 岩松
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP14771089A priority Critical patent/JPH0311737A/en
Publication of JPH0311737A publication Critical patent/JPH0311737A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To make it possible to offer an electrode film having a good electro- migration resistance with good productivity by a method wherein the electrode film in an integrated circuit device is formed into a single crystal film by a solid phase epitaxial growth. CONSTITUTION:An electrode film consisting of Al, an Al-Si alloy, an Al-Si-Cu alloy or the like is formed on an Si single crystal substrate by deposition or the like through a contact hole opened in an insulating film, such as an SiO2 film or the like, on the substrate. After that, when a treatment, such as a photoetching or the like is applied to this electrode film, and a heating treatment is performed in an inactive atmosphere, the electrode film can be turned to a single crystal by a solid phase epitaxial growth. In addition to this electrode film, the electrode film may be film consisting of a metal, such as Ti, TiSi, TiN, W, Mo or the like, or each alloy of these metals or a multilayer film consisting of some one of these metals or alloys, a partial multilayer film or the like and the single crystal substrate may be a lower electrode or after an insulating film consisting of SiO2 or the like is formed on the electrode, the insulating film may be turned to a single crystal by a solid phase epitaxial growth.

Description

【発明の詳細な説明】 [産業上の利用分野コ 本発明は集積回路装置における電極膜に関する[従来の
技術] 従来、81基板上のS i ot膜を介してAt電極を
形成し、該At電極をレーザービーム等の量子ビーム 
アニールにより羊結晶化してエレクトロ マイグレーシ
田ン耐性を得る方法が用いられ[発明が解決しようとす
る課ffl] しかし、上記従来技術によると、エレクトロマイグレー
シフン耐性が充分でないという課題や、生産性が悪い等
の課題もあった。
Detailed Description of the Invention [Industrial Field of Application] The present invention relates to an electrode film in an integrated circuit device [Prior Art] Conventionally, an At electrode is formed via a Si ot film on an 81 substrate, and the At Quantum beams such as laser beams with electrodes
A method of obtaining resistance to electromigration by crystallization by annealing is used [issues to be solved by the inventionffl] However, according to the above-mentioned conventional technology, there are problems such as insufficient resistance to electromigration and poor productivity. There were also other issues.

本発明はかかる従来技術の課題を解決し、エレクトロ 
マイグレーシlン耐性の良好な集積回路装置における電
極膜を生産性良く提供する事を目的とする。
The present invention solves the problems of the prior art and
The object of the present invention is to provide an electrode film for an integrated circuit device that has good resistance to migration and is highly productive.

[課題を解決するための手段] 本発明はかかる従来技術、の課題を解決し、本発明の目
的を達成するために、電極膜を固相エピタキシャルによ
る単結晶電極膜と成す事を基本とする。
[Means for Solving the Problems] In order to solve the problems of the prior art and achieve the object of the present invention, the present invention is based on forming an electrode film as a single crystal electrode film by solid phase epitaxial method. .

[実施例] 以下、★施例により本発明を詳述する。[Example] Hereinafter, the present invention will be explained in detail using ★ Examples.

いま、S1拳結晶基板上に810!膜等の絶縁膜を介し
て、該絶縁膜に開けられたコンタクト穴を通してAA、
At−3i 、At−5i−Ou等の電極膜を蒸着等に
て形成後、該電極膜をホト・エツチング等の加工処理を
施して不活性雰囲気中にて加熱処理を施すと、固相エピ
タキシャルにより単結晶化する事ができる。但し、ホト
・エツチング加工前に蒸着中あるいは、不活性雰囲気中
等で加熱処理を施しても良い。
Now, 810 on the S1 fist crystal board! AA, through a contact hole made in the insulating film,
After forming an electrode film of At-3i, At-5i-Ou, etc. by vapor deposition, etc., the electrode film is subjected to processing such as photo-etching and then heat-treated in an inert atmosphere to form a solid phase epitaxial layer. It can be made into a single crystal. However, heat treatment may be performed during vapor deposition or in an inert atmosphere before photo-etching.

なお、電極膜はAAやhL合金の他、T1゜TiSi、
TiN、W、WSi、Mo、MoSi、Ou等の他の金
属や合金あるいは、これら金属や合金の多層膜や部分的
多層膜等であっても良いる単結晶化が少なくとも2ミク
ロン以上進み、コンタクト穴間隔が4ミクロン以下の場
合にはコンタクト穴間隔の中央にて単結晶が互いに衝突
し、結晶粒界を形成する場合もあるが、その場合でもヱ
ルクトロマイグレーション耐性を向上する事カできる。
In addition to AA and hL alloy, the electrode film is made of T1゜TiSi,
Other metals or alloys such as TiN, W, WSi, Mo, MoSi, Ou, etc., or multilayer films or partial multilayer films of these metals or alloys may be formed. Single crystallization progresses to at least 2 microns or more, and contact is formed. When the hole spacing is 4 microns or less, single crystals may collide with each other at the center of the contact hole spacing, forming grain boundaries, but even in that case, the electromigration resistance can be improved.

[発明の効果] 本発明により、エレクトロ マイグレーシコン耐性の良
好な集積回路装置における電極配線を生産住良(形成で
き、提供することができる効果がある。
[Effects of the Invention] The present invention has the advantage that it is possible to form and provide electrode wiring in an integrated circuit device with good electromigration resistance.

さらに、前記S1単結晶基板は下層電極であっても良く
、電極上に8108等の絶縁膜を形゛成後、固相エピタ
キシャルに′より嚇結晶化しても良い以上
Furthermore, the S1 single crystal substrate may be a lower layer electrode, and after forming an insulating film such as 8108 on the electrode, it may be crystallized by solid phase epitaxial method.

Claims (1)

【特許請求の範囲】[Claims] 半導体または電極と絶縁膜を介して連らなった電極膜を
単結晶膜と成す事を特徴とする固相エピタキシャル。
A solid-phase epitaxial method characterized by forming a single-crystalline electrode film that is connected to a semiconductor or an electrode via an insulating film.
JP14771089A 1989-06-09 1989-06-09 Solid phase epitaxy Pending JPH0311737A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14771089A JPH0311737A (en) 1989-06-09 1989-06-09 Solid phase epitaxy

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14771089A JPH0311737A (en) 1989-06-09 1989-06-09 Solid phase epitaxy

Publications (1)

Publication Number Publication Date
JPH0311737A true JPH0311737A (en) 1991-01-21

Family

ID=15436465

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14771089A Pending JPH0311737A (en) 1989-06-09 1989-06-09 Solid phase epitaxy

Country Status (1)

Country Link
JP (1) JPH0311737A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6429519B1 (en) 1997-04-03 2002-08-06 International Business Machines Corporation Wiring structures containing interconnected metal and wiring levels including a continuous, single crystalline or polycrystalline conductive material having one or more twin boundaries
CN100435284C (en) * 2004-06-09 2008-11-19 海力士半导体有限公司 Semiconductor device with low contact resistance and method for fabricating the same
JP2011009595A (en) * 2009-06-29 2011-01-13 Renesas Electronics Corp Semiconductor device and method of manufacturing the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6429519B1 (en) 1997-04-03 2002-08-06 International Business Machines Corporation Wiring structures containing interconnected metal and wiring levels including a continuous, single crystalline or polycrystalline conductive material having one or more twin boundaries
CN100435284C (en) * 2004-06-09 2008-11-19 海力士半导体有限公司 Semiconductor device with low contact resistance and method for fabricating the same
JP2011009595A (en) * 2009-06-29 2011-01-13 Renesas Electronics Corp Semiconductor device and method of manufacturing the same

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