JPH06302602A - Fabrication of semiconductor device - Google Patents
Fabrication of semiconductor deviceInfo
- Publication number
- JPH06302602A JPH06302602A JP8999093A JP8999093A JPH06302602A JP H06302602 A JPH06302602 A JP H06302602A JP 8999093 A JP8999093 A JP 8999093A JP 8999093 A JP8999093 A JP 8999093A JP H06302602 A JPH06302602 A JP H06302602A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- film
- alloy
- refractory metal
- temperature
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置の製造方法
に係り、特に、配線のエレクトロマイグレーション耐性
（以下、『ＥＭ耐性』という）を向上する半導体装置の
製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device which improves electromigration resistance of wiring (hereinafter referred to as "EM resistance").
【０００２】[0002]
【従来の技術】従来から、半導体装置の微細化及び高集
積化に伴って、素子の微細化が行われてきている。この
ため、配線の電流密度が大きくなり、局所的な断線や抵
抗の増加が生じ易くなってきており、ＥＭ耐性を向上す
ることが益々要求されてきている。このエレクトロマイ
グレーションは、金属イオンに電子が衝突してボイドを
発生させ、断線に至らしめる現象である。2. Description of the Related Art Heretofore, elements have been miniaturized with the miniaturization and high integration of semiconductor devices. For this reason, the current density of the wiring is increased, and local disconnection and increase in resistance are likely to occur, and it is increasingly required to improve the EM resistance. This electromigration is a phenomenon in which electrons collide with metal ions to generate voids, which leads to disconnection.
【０００３】そこで、配線のＥＭ耐性を向上する方法の
一つとして、アルミニウム（以下、『Ａｌ』という）に
所望量の銅（以下、『Ｃｕ』という）を添加したＡｌ合
金（以下、『Ａｌ−Ｃｕ合金』という）を配線材料とし
て使用する方法が紹介されている。このＡｌ−Ｃｕ合金
からなる配線は、所望の熱処理を行うことで、当該配線
膜の粒界等に、Ａｌ−Ｃｕ系合金を析出させ、これをボ
イドのシンクとして働かせることで、ＥＭ耐性を向上し
ている。また、同様に、前記Ｃｕの代わりに、所望量の
スカンジウム（以下、『Ｓｃ』という）、パラジウム
（以下、『Ｐｄ』という）、ハフニウム（以下、『Ｈ
ｆ』という）を添加したＡｌ合金を配線材料として使用
することでも、同様の効果を得ることができる。Therefore, as one of the methods for improving the EM resistance of wiring, an aluminum alloy (hereinafter, "Al") in which a desired amount of copper (hereinafter, "Cu") is added to aluminum (hereinafter, "Al") is used. -Cu alloy ") is used as a wiring material. The wiring made of this Al-Cu alloy is subjected to a desired heat treatment to precipitate an Al-Cu-based alloy at the grain boundaries of the wiring film, etc., and this is used as a void sink to improve the EM resistance. is doing. Similarly, instead of Cu, a desired amount of scandium (hereinafter, referred to as “Sc”), palladium (hereinafter, referred to as “Pd”), hafnium (hereinafter, referred to as “H”).
The same effect can be obtained by using an Al alloy added with “f”) as a wiring material.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、この恒
温熱処理工程を行っても、前記Ａｌ合金からなる配線に
シリコン（以下、『Ｓｉ』という）が含まれていると、
当該Ｓｉが配線に析出して実質の配線幅が狭くなり、通
電中に局所的な温度上昇が生じてＥＭ耐性を著しく低下
させるという問題があった（例えば、特願平５−００２
８３７号）。However, even if this constant temperature heat treatment step is performed, if the wiring made of the Al alloy contains silicon (hereinafter referred to as "Si"),
There is a problem that the Si is deposited on the wiring and the actual wiring width is narrowed, a local temperature rise occurs during energization, and the EM resistance is significantly lowered (for example, Japanese Patent Application No. 5-002).
837).
【０００５】そこで、TECHNICAL REPORT OF IEICE.SMD9
2-101(1992-11)、信学技報にて、前田圭一、田口充、菅
野幸保（敬省略）らにより紹介されているように、Ａｌ
−Ｓｉ合金からなる配線の下地として、Ｔｉ膜を形成し
た後、５００℃前後の高温スパッタ法を行い、当該Ｔｉ
膜上に、Ａｌ−Ｓｉ合金からなる配線を蒸着すること
で、当該配線中に存在しているＳｉとＴｉとを反応さ
せ、該配線中に存在するＳｉの量を減少させて、当該配
線中にＳｉが析出することを防止する方法が存在する。Therefore, TECHNICAL REPORT OF IEICE.SMD9
As described in Keiichi Maeda, Mitsuru Taguchi, and Yukiho Kanno (respect omitted) in 2-101 (1992-11), IEICE Tech.
After forming a Ti film as a base of a wiring made of a -Si alloy, a high temperature sputtering method at about 500 ° C is performed to remove the Ti film.
By depositing a wiring made of an Al-Si alloy on the film, Si and Ti existing in the wiring are reacted with each other to reduce the amount of Si existing in the wiring, and There is a method of preventing Si from precipitating.
【０００６】しかしながら、この方法は、Ａｌ−Ｓｉ合
金からなる配線を形成する際についての報告であり、当
該配線のＥＭ耐性を向上する目的で、Ａｌ−Ｓｉ合金に
Ｃｕ等の金属を添加していないため、Ｓｉの析出に起因
したＥＭ耐性の低下は抑制するものの、ＥＭ耐性を十分
に向上することができないという問題があった。また、
仮に、前記Ａｌ−Ｓｉ合金からなる配線に、さらにＣｕ
を添加したとしても、配線自身を５００℃程度の高温で
形成するため、配線中にＡｌ−Ｃｕ系合金を十分に析出
させることができず、ＥＭ耐性を十分に向上させること
ができないという問題があった。[0006] However, this method is a report on forming a wiring made of an Al-Si alloy, and a metal such as Cu is added to the Al-Si alloy for the purpose of improving the EM resistance of the wiring. Since it does not exist, the decrease in EM resistance due to the precipitation of Si is suppressed, but there is a problem that the EM resistance cannot be sufficiently improved. Also,
If the wiring made of the Al-Si alloy is further provided with Cu,
However, since the wiring itself is formed at a high temperature of about 500 ° C. even if Al is added, there is a problem that the Al—Cu alloy cannot be sufficiently precipitated in the wiring and the EM resistance cannot be sufficiently improved. there were.
【０００７】本発明は、このような従来の問題点を解決
することを課題とするものであり、Ａｌ合金からなる配
線中に、Ｓｉが析出することを抑制することで、当該配
線のＥＭ耐性を向上する半導体装置の製造方法を提供す
ることを目的とする。An object of the present invention is to solve such a conventional problem, and by suppressing the precipitation of Si in the wiring made of an Al alloy, the EM resistance of the wiring is suppressed. It is an object of the present invention to provide a method of manufacturing a semiconductor device that improves the manufacturing cost.
【０００８】[0008]
【課題を解決するための手段】この目的を達成するため
に、本発明は、ＣｕとＳｉとを所定量含有したＡｌ合金
からなる配線の下地、上層及び側面の少なくとも一つ
に、高融点金属膜を形成する第１工程と、前記高融点金
属膜形成後、該高融点金属とＳｉとの化合物が形成され
る温度以上で熱処理を行う第２工程と、前記熱処理を行
った後、Ａｌに対するＣｕの固溶限以下の温度で恒温放
置する第３工程と、を含むことを特徴とする半導体装置
の製造方法を提供するものである。In order to achieve this object, the present invention provides a refractory metal at least one of an underlayer, an upper layer and a side surface of a wiring made of an Al alloy containing a predetermined amount of Cu and Si. A first step of forming a film, a second step of forming the refractory metal film, and a heat treatment at a temperature at which the compound of the refractory metal and Si is formed, and a second step of performing the heat treatment on Al. And a third step of keeping it at a temperature equal to or lower than the solid solution limit of Cu, and a method for manufacturing a semiconductor device.
【０００９】そして、Ｓｃ、Ｐｄ、Ｈｆのうちの少なく
とも一種と、Ｓｉとを所定量含有したＡｌ合金からなる
配線の下地、上層及び側面の少なくとも一つに、高融点
金属膜を形成する第１工程と、前記高融点金属膜形成
後、当該高融点金属とＳｉとの化合物が形成される温度
以上で熱処理を行う第２工程と、前記熱処理を行った
後、前記Ａｌ配線に含まれる金属のＡｌに対する固溶限
以下の温度で恒温放置する第３工程と、を含むことを特
徴とする半導体装置の製造方法を提供するものである。Then, a refractory metal film is formed on at least one of a base, an upper layer and a side surface of a wiring made of an Al alloy containing a predetermined amount of at least one of Sc, Pd and Hf and Si. A step of performing a heat treatment after forming the refractory metal film at a temperature at which a compound of the refractory metal and Si is formed, and a step of performing a heat treatment on the metal contained in the Al wiring after the heat treatment. And a third step of isothermally leaving at a temperature not higher than the solid solution limit for Al, the method for manufacturing a semiconductor device is provided.
【００１０】また、前記高融点金属膜として、チタン膜
（以下、『Ｔｉ膜』という）、モリブデン膜（以下、
『Ｍｏ膜』という）、タングステン膜（以下、『Ｗ膜』
という）のうちのいずれかを形成することを特徴とする
半導体装置の製造方法を提供するものである。さらにま
た、前記熱処理を３５０℃以上の温度で行うことを特徴
とする半導体装置の製造方法を提供するものである。As the refractory metal film, a titanium film (hereinafter referred to as "Ti film"), a molybdenum film (hereinafter referred to as "Ti film")
"Mo film"), tungsten film (hereinafter "W film")
That is, any one of the above) is formed. Furthermore, the present invention provides a method for manufacturing a semiconductor device, wherein the heat treatment is performed at a temperature of 350 ° C. or higher.
【００１１】[0011]
【作用】本発明に係る半導体装置の製造方法は、Ａｌ−
Ｓｉ−Ｃｕ合金からなる配線、または、Ｓｉと、Ｓｃ、
Ｐｄ、Ｈｆのうちの少なくとも一種と、を含有するＡｌ
合金からなる配線の下地、上層、側面の少なくとも一つ
に、高融点金属膜を形成した後、該高融点金属とＳｉと
の化合物が形成される温度以上で熱処理を行うことで、
前記配線中のＳｉと高融点金属とを反応させることがで
きる。従って、配線中に存在していたＳｉの量を大幅に
減少させることができる。According to the method of manufacturing a semiconductor device of the present invention, Al-
Wiring made of Si-Cu alloy, or Si and Sc,
Al containing at least one of Pd and Hf
By forming a refractory metal film on at least one of the base, upper layer, and side surface of the wiring made of an alloy, by performing heat treatment at a temperature at which the compound of the refractory metal and Si is formed,
It is possible to react Si in the wiring with a refractory metal. Therefore, the amount of Si existing in the wiring can be significantly reduced.
【００１２】また、この熱処理工程を行った後に、前記
Ａｌ配線に含まれる金属のＡｌに対する固溶限以下の温
度で恒温放置することで、当該配線膜の粒界に、Ａｌ−
Ｃｕ系合金、またはＡｌに含まれる金属に応じて、Ａｌ
−Ｓｃ系合金、Ａｌ−Ｐｄ系合金、Ａｌ−Ｈｆ系合金を
析出することができる。前記高融点金属膜として、Ｔｉ
膜、Ｍｏ膜、Ｗ膜のうちのいずれかを形成することで、
前記熱処理工程において、高融点金属とＳｉとの化合物
をより形成し易くなり、配線中に存在していたＳｉの量
をさらに効果的に減少させることができる。After this heat treatment process, the metal contained in the Al wiring is allowed to stand at a temperature not higher than the solid solubility limit for Al, so that the Al--
Al based on Cu-based alloy or metal contained in Al
It is possible to deposit —Sc alloy, Al—Pd alloy, and Al—Hf alloy. As the refractory metal film, Ti
By forming any one of a film, a Mo film, and a W film,
In the heat treatment step, the compound of the refractory metal and Si can be more easily formed, and the amount of Si existing in the wiring can be reduced more effectively.
【００１３】また、前記熱処理を３５０℃以上の温度で
行うことで、前記高融点金属とＳｉとの反応をさらに行
い易くすることができる。By performing the heat treatment at a temperature of 350 ° C. or higher, the reaction between the refractory metal and Si can be further facilitated.
【００１４】[0014]
【実施例】次に、本発明に係る実施例について、図面を
参照して説明する。図１（１）〜（３）は、本発明の実
施例に係る半導体装置の製造工程の一部を示す部分断面
図である。図１（１）に示す工程では、所望の処理が施
された半導体基板１上に、熱酸化を行い、膜厚が０．６
μｍ程度の酸化膜２を形成する。次いで、前記酸化膜２
上に、スパッタ法により高融点金属膜として、膜厚が
０．２μｍ程度のＴｉ膜３を蒸着する。Embodiments of the present invention will now be described with reference to the drawings. 1A to 1C are partial cross-sectional views showing a part of the manufacturing process of a semiconductor device according to an embodiment of the invention. In the step shown in FIG. 1A, thermal oxidation is performed on the semiconductor substrate 1 that has been subjected to a desired treatment, and the film thickness is 0.6.
An oxide film 2 having a thickness of about μm is formed. Then, the oxide film 2
A Ti film 3 having a film thickness of about 0.2 μm is vapor-deposited thereon as a refractory metal film by a sputtering method.
【００１５】次に、図１（２）に示す工程では、図１
（１）に示す工程で得たＴｉ膜３上に、スパッタ法によ
り、Ａｌ＝９８．５％、Ｃｕ＝０．５％、Ｓｉ＝１．０
％の組成を備えたＡｌ−Ｃｕ−Ｓｉ合金からなる配線膜
を１．０μｍ程度の膜厚で蒸着した後、これをパターニ
ングして、Ａｌ−Ｃｕ−Ｓｉ合金からなる配線４を形成
する。Next, in the step shown in FIG.
Al = 98.5%, Cu = 0.5%, Si = 1.0 on the Ti film 3 obtained in the step (1) by the sputtering method.
%, A wiring film made of an Al—Cu—Si alloy having a composition of 1.0% is vapor-deposited to a film thickness of about 1.0 μm, and then patterned to form a wiring 4 made of an Al—Cu—Si alloy.
【００１６】次いで、図１（３）に示す工程では、図１
（２）に示す工程で得たＡｌ−Ｃｕ−Ｓｉ合金からなる
配線４上に、ＣＶＤ（Chemical Vapor Deposition ）法
により、パッシベーション膜７を蒸着した後、４００
℃、３０分間のアロイ処理を行う。このアロイ処理は、
トランジスタの安定化を得るため、半導体装置の製造工
程中に、一般的に行われる工程である。本実施例では、
このアロイ工程により、Ａｌ−Ｃｕ−Ｓｉ合金からなる
配線４中に含有されていたＳｉが、Ｔｉ膜３と反応しＴ
ｉＳｉ2 膜５（ＴｉとＳｉとの化合物）が形成され、前
記Ａｌ−Ｃｕ−Ｓｉ合金からなる配線４が、Ｓｉの含有
量が減少した配線６となる。このため、Ａｌ−Ｃｕ−Ｓ
ｉ合金からなる配線４中に存在していたＳｉの量を大幅
に減少させることができる。Then, in the step shown in FIG.
After depositing a passivation film 7 by a CVD (Chemical Vapor Deposition) method on the wiring 4 made of an Al—Cu—Si alloy obtained in the step shown in (2), 400
Alloy treatment is performed at 30 ° C. for 30 minutes. This alloy process is
This is a process generally performed during the manufacturing process of a semiconductor device in order to obtain the stabilization of the transistor. In this embodiment,
By this alloying process, Si contained in the wiring 4 made of an Al—Cu—Si alloy reacts with the Ti film 3 to cause T
The iSi 2 film 5 (compound of Ti and Si) is formed, and the wiring 4 made of the Al—Cu—Si alloy becomes the wiring 6 having a reduced Si content. Therefore, Al-Cu-S
The amount of Si existing in the wiring 4 made of i alloy can be greatly reduced.
【００１７】次に、図１（３）で得たウエハに、組み立
て工程等、所望の工程を行った後、２５０℃の恒温放置
処理（エージング処理）を行う。以上の工程を経て、本
実施例に係る半導体装置（発明品）を得た。次に、比較
として、図１（１）に示す工程で、Ｔｉ膜３を形成する
ことなく、図１（２）に示す工程で、酸化膜２上に直接
前記実施例と同様のＡｌ−Ｃｕ−Ｓｉ合金からなる配線
４を形成した後、以下前記実施例と同様の工程（同様の
恒温放置処理も含む）を行い、半導体装置（比較品）を
得た。Next, the wafer obtained in FIG. 1 (3) is subjected to a desired process such as an assembling process, and then subjected to an incubating process (aging process) at 250 ° C. Through the above steps, a semiconductor device (invention) according to this example was obtained. Next, as a comparison, in the step shown in FIG. 1A, without forming the Ti film 3, in the step shown in FIG. After the wiring 4 made of —Si alloy was formed, the same steps (including the same constant temperature standing treatment) as those in the above-described example were performed to obtain a semiconductor device (comparative product).
【００１８】次いで、前記発明品及び比較品について、
ＥＭ耐性の比較を行った。なお、本実施例では、発明品
及び比較品共に、前記恒温放置処理として、２５０℃
で、５時間、１０時間及び５０時間の処理を行ったサン
プルについて、ＥＭ耐性の比較を以下の条件で行った。 配線温度 ２５０℃ 電流密度 ５×１０5 Ａ／ｃｍ2 評価方法 比較品が断線した時間を１として発明品
の断線した時間を相対的に評価した。Next, regarding the above-mentioned invention product and comparative product,
A comparison of EM resistance was made. In this example, both the invention product and the comparative product were subjected to the constant temperature standing treatment at 250 ° C.
Then, the EM resistances of the samples treated for 5 hours, 10 hours and 50 hours were compared under the following conditions. Wiring temperature 250 ° C. Current density 5 × 10 5 A / cm 2 Evaluation method The breakage time of the invention product was relatively evaluated with the breakage time of the comparative product as 1.
【００１９】この結果を表１に示す。The results are shown in Table 1.
【００２０】[0020]
【表１】 [Table 1]
【００２１】表１から、発明品は、比較品と比べＥＭ耐
性が、５時間の恒温放置処理では、８倍、１０時間の恒
温放置処理では、３０倍、５０時間の恒温放置処理で
は、２４倍向上したことが確認された。これは、Ａｌ−
Ｃｕ−Ｓｉ合金からなる配線４中に含有されていたＳｉ
が、Ｔｉ膜３と反応しＴｉＳｉ2 膜５が形成され、Ａｌ
−Ｃｕ−Ｓｉ合金からなる配線４中に存在していたＳｉ
の量を大幅に減少させることができた結果、従来のよう
に、Ｓｉが配線に析出して実質の配線幅が狭くなり、通
電中に局所的な温度上昇が生じてＥＭ耐性を著しく低下
することを抑制できたためである。It can be seen from Table 1 that the invention product has EM resistance higher than that of the comparative product by 8 times in 5 hours of constant temperature treatment, 30 times in 10 hours of constant temperature treatment and 24 times in 50 hours of constant temperature treatment. It was confirmed that it doubled. This is Al-
Si contained in the wiring 4 made of a Cu-Si alloy
But reacts with the Ti film 3 to form a TiSi 2 film 5,
Si existing in the wiring 4 made of -Cu-Si alloy
As a result, Si is deposited on the wiring and the actual wiring width is narrowed, resulting in a local temperature rise during energization, resulting in a significant decrease in EM resistance, as in the conventional case. This is because it was possible to suppress this.
【００２２】一方、比較品は、Ａｌ−Ｃｕ−Ｓｉ合金か
らなる配線４中に含有されていたＳｉが、前記恒温放置
処理の間に粗大化し、実質の配線幅が狭くなったため、
通電中に局所的な温度上昇が生じてＥＭ耐性を著しく低
下させたことが判る。なお、本実施例では、Ｔｉ膜３を
Ａｌ−Ｃｕ−Ｓｉ合金からなる配線４の下地として形成
したが、これに限らず、Ｔｉ３膜は、Ａｌ−Ｃｕ−Ｓｉ
合金からなる配線４の下地、上層及び側面の少なくとも
一つに形成されていればよい。On the other hand, in the comparative product, Si contained in the wiring 4 made of an Al--Cu--Si alloy was coarsened during the above-mentioned constant temperature treatment, and the actual wiring width was narrowed.
It can be seen that a local temperature rise occurred during energization and the EM resistance was significantly reduced. Although the Ti film 3 is formed as the base of the wiring 4 made of an Al—Cu—Si alloy in this embodiment, the Ti 3 film is not limited to this, and the Ti 3 film is formed of an Al—Cu—Si alloy.
It may be formed on at least one of the base, the upper layer and the side surface of the wiring 4 made of an alloy.
【００２３】また、本実施例では、高融点金属膜とし
て、Ｔｉ膜を形成したが、これに限らず、Ｓｉとの化合
物を形成するこが可能であれば、例えば、Ｍｏ膜やＷ膜
等、他の高融点金属膜を形成してもよい。そして、本実
施例では、Ａｌ＝９８．５％、Ｃｕ＝０．５％、Ｓｉ＝
１．０％の組成を備えたＡｌ−Ｃｕ−Ｓｉ合金からなる
配線４を形成したが、これに限らず、Ａｌ−Ｃｕ−Ｓｉ
合金からなる配線４の各成分の組成比は、所望により決
定してよい。Further, in this embodiment, the Ti film is formed as the refractory metal film, but the present invention is not limited to this, and if a compound with Si can be formed, for example, a Mo film, a W film, or the like. Alternatively, another refractory metal film may be formed. Then, in this embodiment, Al = 98.5%, Cu = 0.5%, Si =
Although the wiring 4 made of an Al-Cu-Si alloy having a composition of 1.0% is formed, the present invention is not limited to this, and Al-Cu-Si is also used.
The composition ratio of each component of the wiring 4 made of an alloy may be determined as desired.
【００２４】また、Ａｌ−Ｃｕ−Ｓｉ合金からなる配線
４の他、Ｓｃ、Ｐｄ、Ｈｆのうちの少なくとも一種と、
Ｓｉとを所定量含有したＡｌ合金からなる配線を形成し
た場合でも、同様の効果を得ることができる。そして、
本実施例では、４００℃で３０分間のアロイ処理を行う
ことにより、ＴｉとＳｉとの化合物（ＴｉＳｉ2 ）を形
成したが、これに限らず、ＴｉとＳｉとの化合物を形成
することが可能な温度で行う熱処理であれば、他の熱処
理を行ってもよい。In addition to the wiring 4 made of Al--Cu--Si alloy, at least one of Sc, Pd and Hf,
The same effect can be obtained even when a wiring made of an Al alloy containing a predetermined amount of Si is formed. And
In this embodiment, the compound of Ti and Si (TiSi 2 ) is formed by performing the alloying treatment at 400 ° C. for 30 minutes, but not limited to this, it is possible to form the compound of Ti and Si. Other heat treatments may be performed as long as they are heat treatments performed at various temperatures.
【００２５】また、本実施例では、２５０℃で恒温放置
処理を行ったが、これに限らず、恒温放置処理は、Ａｌ
−Ｃｕ−Ｓｉ合金からなる配線４を形成した場合は、Ａ
ｌに対するＣｕの固溶限以下の温度で行えばよく、Ｓ
ｃ、Ｐｄ、Ｈｆのうちの少なくとも一種と、Ｓｉとを所
定量含有したＡｌ合金からなる配線を形成した場合に
は、当該Ａｌ合金からなる配線に含まれる金属（Ｓｃ、
Ｐｄ、Ｈｆのうちの少なくとも一種）のＡｌに対する固
溶限以下の温度で行えばよい。Further, in the present embodiment, the constant temperature standing treatment was carried out at 250 ° C. However, the present invention is not limited to this, and the constant temperature standing treatment is performed by Al
When the wiring 4 made of a —Cu—Si alloy is formed, A
It may be carried out at a temperature below the solid solubility limit of Cu to 1
When a wiring made of an Al alloy containing a predetermined amount of at least one of c, Pd, and Hf and Si is formed, the metal (Sc,
It may be carried out at a temperature not higher than the solid solubility limit of Al of at least one of Pd and Hf).
【００２６】そして、この恒温放置処理は、例えば、組
み立て工程終了後等、該恒温放置処理が終了した後に、
再び前記固溶限以上の温度がかかる熱処理が施されない
時に行うことが望ましい。これは、前記恒温処理によ
り、析出させたＡｌ−Ｃｕ系合金等が、後の熱処理によ
り再びＡｌ合金中に固溶してしまうことを防止するため
である。This incubating process is carried out after the incubating process is completed, for example, after the assembly process is completed.
It is desirable to perform it again when the heat treatment at a temperature above the solid solution limit is not performed. This is to prevent the Al—Cu based alloy or the like precipitated by the constant temperature treatment from becoming solid solution again in the Al alloy due to the subsequent heat treatment.
【００２７】[0027]
【発明の効果】以上説明したように、本発明に係る半導
体装置の製造方法は、Ａｌ−Ｓｉ−Ｃｕ合金からなる配
線、または、Ｓｉと、Ｓｃ、Ｐｄ、Ｈｆのうちの少なく
とも一種と、を含有するＡｌ合金からなる配線の下地、
上層、側面の少なくとも一つに、高融点金属膜を形成し
た後、該高融点金属とＳｉとの化合物が形成される温度
以上で熱処理を行うことで、前記配線中のＳｉと高融点
金属とを反応させることができる。従って、配線中に存
在していたＳｉの量を大幅に減少させることができる。
この結果、従来のように、Ｓｉが配線中に析出して実質
の配線幅が狭くなることを防止することができ、ＥＭ耐
性を著しく向上することができる。As described above, in the method of manufacturing a semiconductor device according to the present invention, the wiring made of Al--Si--Cu alloy or Si and at least one of Sc, Pd, and Hf is used. Wiring base made of contained Al alloy,
After forming a refractory metal film on at least one of the upper layer and the side surface, heat treatment is performed at a temperature at which the compound of the refractory metal and Si is formed or higher, whereby Si and refractory metal in the wiring Can be reacted. Therefore, the amount of Si existing in the wiring can be significantly reduced.
As a result, it is possible to prevent Si from being deposited in the wiring and narrow the actual wiring width as in the conventional case, and it is possible to remarkably improve the EM resistance.
【００２８】また、この熱処理工程を行った後に、前記
Ａｌ配線に含まれる金属のＡｌに対する固溶限以下の温
度で恒温放置することで、当該配線膜の粒界に、Ａｌ−
Ｃｕ系合金、またはＡｌに含まれる金属に応じて、Ａｌ
−Ｓｃ系合金、Ａｌ−Ｐｄ系合金、Ａｌ−Ｈｆ系合金を
析出することができる結果、さらにＥＭ耐性を向上する
ことができる。After performing this heat treatment step, the metal contained in the Al wiring is allowed to stand at a temperature not higher than the solid solubility limit for Al so that the Al--
Al based on Cu-based alloy or metal contained in Al
As a result of being able to deposit a —Sc alloy, an Al—Pd alloy, and an Al—Hf alloy, the EM resistance can be further improved.
【００２９】前記高融点金属膜として、Ｔｉ膜、Ｍｏ
膜、Ｗ膜のうちのいずれかを形成することで、前記熱処
理工程において、高融点金属とＳｉとの化合物をより形
成し易くなり、配線中に存在していたＳｉの量をさらに
効果的に減少させることができる。また、前記熱処理を
３５０℃以上の温度で行うことで、前記高融点金属とＳ
ｉとの反応をさらに行い易くすることができる。As the refractory metal film, a Ti film, Mo
By forming either the film or the W film, it becomes easier to form a compound of a refractory metal and Si in the heat treatment step, and the amount of Si existing in the wiring can be more effectively reduced. Can be reduced. Further, by performing the heat treatment at a temperature of 350 ° C. or higher, the refractory metal and S
The reaction with i can be further facilitated.
【図１】本発明の一実施例にかかる半導体装置の製造工
程の一部を示す部分断面図である。FIG. 1 is a partial cross-sectional view showing a part of a manufacturing process of a semiconductor device according to an embodiment of the present invention.
１ 半導体装置 ２ 酸化膜 ３ Ｔｉ膜 ４ Ａｌ−Ｃｕ−Ｓｉ合金からなる配線 ５ ＴｉＳｉ2 膜 ６ Ｓｉの含有量が減少した配線 ７ パッシベーション膜DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Oxide film 3 Ti film 4 Wiring consisting of Al-Cu-Si alloy 5 TiSi 2 film 6 Wiring with reduced Si content 7 Passivation film
Claims (4)
ニウム合金からなる配線の下地、上層及び側面の少なく
とも一つに、高融点金属膜を形成する第１工程と、前記
高融点金属膜形成後、該高融点金属とシリコンとの化合
物が形成される温度以上で熱処理を行う第２工程と、前
記熱処理を行った後、アルミニウムに対する銅の固溶限
以下の温度で恒温放置する第３工程と、を含むことを特
徴とする半導体装置の製造方法。1. A first step of forming a refractory metal film on at least one of an underlayer, an upper layer and a side surface of a wiring made of an aluminum alloy containing a predetermined amount of copper and silicon, and after the refractory metal film is formed. A second step of performing a heat treatment at a temperature at which the compound of the refractory metal and silicon is formed or higher, and a third step of performing the heat treatment and then incubating at a temperature not higher than the solid solubility limit of copper in aluminum. A method of manufacturing a semiconductor device, comprising:
のうちの少なくとも一種とシリコンとを所定量含有した
アルミニウム合金からなる配線の下地、上層及び側面の
少なくとも一つに、高融点金属膜を形成する第１工程
と、前記高融点金属膜形成後、該高融点金属とシリコン
との化合物が形成される温度以上で熱処理を行う第２工
程と、前記熱処理を行った後、前記アルミニウム合金か
らなる配線に含まれる金属のアルミニウムに対する固溶
限以下の温度で恒温放置する第３工程と、を含むことを
特徴とする半導体装置の製造方法。2. A first step of forming a refractory metal film on at least one of a base layer, an upper layer and a side surface of a wiring made of an aluminum alloy containing a predetermined amount of at least one of scandium, palladium and hafnium and silicon. And a second step of performing a heat treatment after forming the refractory metal film at a temperature at which the compound of the refractory metal and silicon is formed, and, after performing the heat treatment, included in the wiring made of the aluminum alloy. A third step of isothermally leaving the metal at a temperature not higher than the solid solubility limit for aluminum, the method for manufacturing a semiconductor device.
リブデン膜、タングステン膜のうちのいずれかを形成す
ることを特徴とする請求項１または請求項２に記載の半
導体装置の製造方法。3. The method of manufacturing a semiconductor device according to claim 1, wherein a titanium film, a molybdenum film, or a tungsten film is formed as the refractory metal film.
ことを特徴とする請求項１ないし請求項３のいずれか一
項に記載の半導体装置の製造方法。4. The method of manufacturing a semiconductor device according to claim 1, wherein the heat treatment is performed at a temperature of 350 ° C. or higher.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5089990A JP3033803B2 (en) | 1993-04-16 | 1993-04-16 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5089990A JP3033803B2 (en) | 1993-04-16 | 1993-04-16 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06302602A true JPH06302602A (en) | 1994-10-28 |
| JP3033803B2 JP3033803B2 (en) | 2000-04-17 |
Family
ID=13986078
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5089990A Expired - Fee Related JP3033803B2 (en) | 1993-04-16 | 1993-04-16 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3033803B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100223759B1 (en) * | 1995-12-16 | 1999-10-15 | 김영환 | Method for forming metal interconnection layer of semiconductor device |
| KR20190073723A (en) * | 2017-12-19 | 2019-06-27 | 삼성전자주식회사 | Method for fabricating semiconductor device |
-
1993
- 1993-04-16 JP JP5089990A patent/JP3033803B2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100223759B1 (en) * | 1995-12-16 | 1999-10-15 | 김영환 | Method for forming metal interconnection layer of semiconductor device |
| KR20190073723A (en) * | 2017-12-19 | 2019-06-27 | 삼성전자주식회사 | Method for fabricating semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3033803B2 (en) | 2000-04-17 |
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