JPS63106815A - Digital pattern generator - Google Patents

Abstract

PURPOSE:To decrease an access time and a cycle time of a memory and to reduce the memory capacity by providing a sampling frequency converting means which uses data interpolation method between the memory and an output latch. CONSTITUTION:A sampling frequency conversion means 4 being the application of the data interpolation method is provided after a memory 3 storing a digital pattern to interpolate inbetween low speed sampling frequency data strings area from the memory 3 at a sampling interval of n-time (n=1, 2...). Thus, even if it is required to generate a digital pattern of an over sampling frequency higher than the nyquist frequency, the digital data at each sampling period fso required at minimum by the sampling theorem is stored in the memory 3, the data is read by the sampling frequency fso, its interpolation data is generated by using the sampling frequency conversion means 4 at the post-stage, the interpolation data is generated thereby forming the oversampling digital pattern having a required sampling frequency.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital pattern generator, and more particularly to a digital pattern generator suitable for applications requiring variable signal frequency and its sampling frequency. It is something.

[Conventional technology]

In conventional digital pattern generators, as described in Japanese Unexamined Patent Publication No. 60-233741, each digital value constituting an output digital pattern is generated by a μ program method or a sequential method. ,
Furthermore, even with these combined digital pattern generators, all digital values used were stored in memory, or conversely, it was necessary to store them in memory. [Problems to be Solved by the Invention] The above-mentioned prior art is particularly premised on the use of generating a digital pattern at a relatively low sampling frequency compared to the signal station wave number (i.e., a frequency close to the Nyquist frequency). It will be done.

Therefore, the memory capacity and memory read speed are relatively small and pose no problem. but,
A digital pattern with a sampling frequency that is relatively high compared to the signal frequency (oversampling pattern)
In applications where it is necessary to generate data, the amount of data stored in the memory increases, and it is also necessary to read data at high speed. Therefore, problems arise in that the memory capacity increases and the memory access time and cycle time become faster.An object of the present invention is to linearly increase the sampling frequency compared to the signal frequency and to make it variable. Even in this case, it is an object of the present invention to provide an economical digital pattern generator that has a small memory capacity and can reduce memory access time and cycle time.

[Means for solving problems]

The above purpose is to provide a sampling frequency conversion means (digital interpolation filter, etc.) that applies a data interpolation method after the memory that stores the digital pattern, and to convert between the low-speed sampling frequency data strings read from the memory by n times ( n is achieved by interpolating at sampling intervals of 1, 2°6, . . . ).

[Effect]

According to the above problem solving means, even if it is necessary to generate a digital pattern with an oversampling frequency higher than the Nyquist frequency, the memory has the minimum required digital pattern according to the sampling theorem. The data is stored at its sampling frequency fg.

The interpolated data can be created using the subsequent sampling frequency conversion means to create an oversampled digital pattern at the required sampling frequency. Furthermore, when changing the signal frequency of the digital pattern by f, the same method can be applied by changing the reading frequency fIilo from the memory.

By adopting the digital pattern generation process as described above, it is possible to reduce the memory capacity, slow down the memory access time and cycle time, and realize an economical digital value turn generator. Example] A preferred embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing the basic configuration of this embodiment, in which 1 is an address counter, 2 is an adder for increasing or decreasing the address counter value, 6 is a memory in which a digital pattern is stored, 4 is a sampling frequency conversion means (digital filter for interpolation, etc.), 5 is an output latch for retiming, 6 is an output buffer, and 7 is a clock supply to the above-mentioned address counter, sampling frequency conversion means, output latch, and other necessary parts. Note that the means for increasing and decreasing the address counter 2 may be controlled by software such as a μ program. Further, 8 is a signal that gives an increase/decrease step of the address counter (n is 1, 2, etc.).

or -+, -2. ..., other variable steps may be used. ).

Address counter 1 outputs address signal A of memory 3 in accordance with memory output digital data sampling clock 'fso sent from variable clock generation circuit 7. The memory 5 reads out the digital data B according to this address signal and converts it into the sampling frequency conversion means 4.
Output to. The sampling frequency conversion means 4 interpolates the digital data B according to the sampling clock flI for sampling frequency conversion sent from the variable clock generation circuit 7, and outputs the digital data C subjected to the sampling frequency conversion to the output latch 5. do. A sampling clock fB2 is sent from the variable clock generation circuit 7 to the output latch 5 for selectively retiming and sampling the digital data string C whose sampling frequency has been converted. The digital data D retimed by fB□ is output to the output buffer 6. Here, retiming may be selectively retiming the digital data string C, that is, every m samples (m is 1
,2. ) is also fine. Buffer 6 outputs digital data D as digital data E.

Referring to FIGS. 1 to 6, the operation of the digital pattern generator in the case of generating a sine wave digital pattern, which is particularly widely used, will be explained.

Figure 2 shows a sample with a constant sine wave frequency and a sampling frequency of 4.
FIG. 6 is an explanatory diagram of generating a digital pattern that has been doubled. As shown in FIG. 2, digital sine wave data B read from the memory 6 is interpolated and subjected to sampling frequency conversion to become a digital pattern sequence C. In other words,
The digital sine wave data string B read out from the memory 6 according to the instruction of the address counter 1, which changes every f80Hz (here, 'fso:=fA Hz), is converted by the sampling frequency conversion means 4 to
fs+Hz (here f91=4 fA).

) is converted into a digital sine wave data sequence C interpolated up to . That is, a four-fold sampling frequency conversion is performed here, and if the sampling frequency conversion means 4 is appropriately selected, a sine wave digital pattern without S/H deterioration can be created. The output latch 5 retimes the pattern sequence at fg2Hz (here, fs2=fs1=4 fl), and further passes it through the buffer 6 to output a sine wave digital pattern E.

FIG. 5 shows the operation in the case of generating a sine wave digital pattern with twice the sine wave frequency and the same sampling frequency as in FIG. 2 above.

Figure 3 (a) is the same as the digital sine wave data B in Figure 2, and Figure 3 (b) shows it at twice the frequency f80.
This is the signal B read out from the memory at the sampling frequency f81 (in this case, f80" 2 fA). FIG.
= f82 = 2 fio = 4 fA. ) is the sampling frequency converted. In this case, the operation of each part is the same as that described in FIG. 2, except that the control clocks fBO to fs2 are changed. Further, by setting f,2\f,i and selectively resampling the output C obtained by converting the sampling frequency (for example, every 6 samples), it is possible to correspond to various sampling frequencies.

As mentioned above, in this embodiment, the control clock f, 0 to fa
By changing 2, the sampling frequency and
This has the effect of allowing WJ to generate sinusoidal digital patterns of various signal frequencies.

〔Effect of the invention〕

As explained above, according to the present invention, Sanbri, 8
.

By storing the minimum amount of digital data required by the processing theorem in memory, reading it out at low speed, and interpolating between the data strings, it is possible to generate an oversampled digital pattern, reducing the memory capacity. , which has the effect of reducing memory access time and cycle time, and realizing an economical digital pattern generator.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a digital pattern generator according to an embodiment of the present invention, and FIGS. 2 and 3 (aL (
bL (c) is an explanatory diagram of the operation of the digital pattern generator shown in FIG.

Claims (1)

[Claims] 1. A memory that stores a digital pattern, an address counter that increases or decreases a read address of the memory continuously or discontinuously, and a digital pattern that is read from the memory.
an output latch and an output buffer for retiming, holding, and distributing patterns, and the address counter,
A digital pattern generator comprising a clock generator for supplying an operating clock to an output latch and other necessary parts, characterized in that a sampling frequency conversion means using a data interpolation method is provided between the memory and the output latch. Digital pattern generator. 2. The digital pattern generator according to claim 1, wherein the latch timing of the output latch is controlled to make the sampling frequency of the output digital pattern variable. 3. Controls the increase/decrease number of the address counter, the increase/decrease timing clock of the address counter, the sampling clock of the sampling frequency conversion means, and the latch timing of the output latch, and controls the signal frequency of the output digital pattern and its sampling. A digital pattern generator according to claim 1 or 2, characterized in that the frequency is variable.