JPH0518116U - Sine wave data generation circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] In the method of compensating between the sine wave data written in the external ROM by linear interpolation, the sine wave data is reduced by shortening the time for reading the difference data used in the linear interpolation calculation from the external ROM. Speed up the generation rate of. [Structure] Sine wave data is written in an external ROM, difference data for linear interpolation calculation is stored in a storage element, and a linear interpolation circuit including the storage element, a multiplier, and an adder is configured as an LSI.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to a signal generator incorporated in various signal analyzers, and relates to high-speed operation of sine wave data generation.

[0002]

[Prior Art]

 Of the signal generators that generate digital data from the data generation circuit, D / A convert (digital-analog convert) this data, and output the waveform, the sine wave generator is the most common. Some can generate sine waves and multi-sine waves. The above-mentioned data generation circuit generally uses a method of reading the sine wave data written in the ROM as shown in FIG. In FIG. 3, reference numeral 1 is a phase data generation circuit, 2 is a ROM which receives the phase data output from the phase data generation circuit 1 as an address input, 3 is a latch circuit which holds the output data of the ROM 2, and 4 is a phase data generation circuit. It is a sign circuit for signing the output of the latch circuit 3 in response to the control signal from 1. In this case, in order to reduce the capacity of the ROM2 used as much as possible, only the sine wave data for 1/4 wavelength is written in the ROM2 as shown in FIG. A method of outputting sine wave data for one wavelength by controlling the order etc. is often used. However, even if the above method is used, the number of sine wave data must be increased in order to increase the resolution with respect to time, and the capacity of the ROM 2 must be increased. As an example of countermeasures against this problem, there is a method of compensating for the sine wave data written in the ROM 2 by linear interpolation, as shown in FIG. In FIG. 5, 1 to 4 are the same as in FIG. Reference numeral 5 is a multiplier, 6 is an adder, 101 is a linear interpolation circuit including a multiplier 5 and an adder 6, and 100 is a phase data generation circuit 1, a latch circuit 3, a sign circuit 4 and a linear interpolation circuit 101 which are integrated. LSI (Large Scale Integrated Circuit).

[0003]

In the method of compensating between the sine wave data written in the ROM2 by the linear interpolation, the process of reading the difference data used in the linear interpolation calculation from the ROM2 and the multiplication and addition calculations are required. The linear interpolation processing time becomes a factor that limits the generation rate of sine wave data. Therefore, an object of the present invention is to increase the generation rate of sine wave data.

[0004]

[Means for Solving the Problems]

 In order to achieve such an object, the present invention writes sine wave data in an external ROM, stores difference data for linear interpolation calculation in a storage element, and forms a linear interpolation circuit including the storage element, a multiplier and an adder. Etc. as an LSI.

[0005]

[Action]

 By writing the difference data for the linear interpolation calculation to the storage element provided in the LSI, the difference data read time is shortened as compared with the method using the external ROM. As a result, the linear interpolation processing time is shortened and the sine wave data generation speed is increased.

[0006]

【Example】

Hereinafter, the present invention will be described in detail with reference to the drawings. In FIG. 1, reference numeral 1 is a phase data generation circuit, 7 and 8 are external ROMs which receive the phase data X _i output from the phase data generation circuit 1 as address inputs, storage elements, and 5 are difference data output from the storage element 8. A multiplier that receives ΔY _i and the phase difference data ΔX _N (= X _N −X _i ) output from the phase data generation circuit 1, and 6 is a calculation result output from the multiplier 5 and an external ROM 7. Which receives the waveform data Y _i to be input, 3 is a latch circuit which holds the output data of the adder 6, and 4 is a code for the output of the latch circuit 3 in response to the control signal from the phase data generation circuit 1. It is a coding circuit for attaching. Further, 101 is a linear interpolation circuit composed of a multiplier 5 and an adder 6, and 100 is an L SI that integrates the phase data generation circuit 1, the latch circuit 3, the sign circuit 4, the storage element 8 and the linear interpolation circuit 101. is there.

FIG. 2 shows the relationship between the sine wave data and the ROM data in FIG. In FIG. 2, the waveform data Y _i corresponding to the phase data X _i and X _{i + 1} is written in the external ROM 7, and the difference data Δ Y _i (= Y _{i + 1} −Y _i ) is written in the storage element 8. The sinusoidal data of a certain phase X _N is linearly interpolated by the following equation. Y _N = Y _i + ΔY _i · ΔX _N / ΔX where ΔX _N = X _N −X _i ΔX = X _{i + 1} −X _i ∴0 ≦ (ΔX _N / ΔX) <1 Therefore, the actual calculation is ΔX = 1 is calculated by the following formula. Y _N = Y _i + ΔY _i · ΔX _N

Now, consider the case where a ROM is used as the storage element 8. In this case, the read time of the internal ROM of the LSI is faster than that of the external ROM as in the example shown below. (Example of operation speed) External ROM read time: 120 ns Internal ROM read time: 20 ns Further, as described above, the linear interpolation processing time is a factor that limits the generation speed of sine wave data, and the linear interpolation processing time reads difference data. It consists of time and multiplication and addition operation time. Therefore, the time for reading out the difference data is shortened, so that the linear interpolation processing time is shortened and the generation speed of the sine wave data is increased as a whole.

Note that the storage element 8 in FIG. 1 can be used not only as a ROM as in the previous example but also as a RAM by adding a function of writing difference data to the RAM at an initial stage such as when power is turned on. is there. In this case, the read time of the RAM is faster than that of the internal ROM and the external ROM, so that the generation speed of the sine wave data is further increased.

[0010]

[Effect of the device]

 As is clear from the above description, the present invention has the following effects. By writing the difference data for the linear interpolation calculation to the storage element provided in the LSI, the difference data read time is shortened as compared with the method using the external ROM. As a result, the linear interpolation processing time is shortened and the sine wave data generation speed is increased.

[Brief description of drawings]

FIG. 1 is a sine wave data generation circuit according to the present invention.

FIG. 2 shows the relationship between sine wave data and ROM data.

FIG. 3 shows an example of a conventional sine wave data generation circuit without linear interpolation.

FIG. 4 shows an example of ROM data.

FIG. 5 shows an example of a conventional sine wave data generation circuit with linear interpolation.

[Explanation of symbols]

 1 Phase Data Generation Circuit 2, 7 External ROM 3 Latch Circuit 4 Encoding Circuit 5 Multiplier 6 Adder 8 Storage Element 100 LSI 101 Linear Interpolation Circuit

Claims (1)

[Scope of utility model registration request] 1. A memory in which sine wave data of the phase value and difference data for linear interpolation calculation of the phase value are written in advance at an address corresponding to the phase value of each constant phase interval, and each of the phase intervals in synchronization with a clock signal. A phase data generation circuit for sequentially generating an address signal corresponding to the phase value of and inputting it to the memory; a circuit for obtaining sine wave data in a phase other than the fixed phase interval by linear interpolation by the output of the memory; In a sine wave data generation circuit having a latch circuit that holds output data of an interpolation circuit and a sign circuit that signs the output of the latch circuit in response to a control signal from the phase data generation circuit, a fixed phase interval External RO in which the sine wave data of the phase value is written in advance at the address corresponding to each phase value
M, and a storage element that stores difference data for linear interpolation calculation of the phase value, and the storage element together with the phase data generation circuit, the linear interpolation circuit, the latch circuit, and the code circuit as a large-scale integrated circuit. A sine wave data generation circuit characterized by being configured.