JPS6035685B2 - Data import method - Google Patents

Description

[Detailed description of the invention] The present invention relates to data acquisition schemes.

In order to import analog signals into a digital computer,
The analog signal was sampled and held, then AD converted, and the result was once stored in a buffer via a multiplexer, and then taken into the computer.

At this time, the import from the buffer into the computer is determined by the processing status within the computer. The computer performs data processing using predetermined processing tasks based on the captured data. Some of these processing tasks may be completed in a short time, while others may take a long time, depending on the type of data to be input and the overall processing situation. Therefore, in a computer, when new data is transferred during processing by a processing task based on imported data, the data cannot be imported, resulting in data loss. Conventionally, in order to reduce these drawbacks, the data acquisition interval on the computer may be set larger, or processing tasks that require a long time may be divided into two, etc. measures were taken. However, the former method resulted in an increase in the data acquisition interval as a whole, and the latter method resulted in an increase in overhead time within the computer. The present invention overcomes these conventional drawbacks and aims to provide a data acquisition method. The gist of the present invention is to convert sampling data into digital signals, store the same data converted into digital signals alternately in two storage devices at a predetermined period, and based on an import command generated after a computer finishes processing a task, The sample establishment information is checked, and data is alternately fetched from each of the storage devices to the computer according to the result.

Hereinafter, the present invention will be explained in detail with reference to the drawings. FIG. 1 shows an embodiment of the present invention, and FIG. 2 shows a time chart.

In the figure, the frequency divider circuit DV divides the frequency of the output of the oscillation circuit OSC to generate various control signals. The control signals are a sample/hold command signal 1 for the sample/hold circuit S/day, and an A/○ conversion command signal 2 for the A/○ converter.
, control signals 3 and 4 for the logic circuit LI. Signals 1, 2, 3, and 4 are set to exhibit a fixed time phase delay in the order of signals 1→2→3→4 in consideration of the processing time in each device. Logic circuit LI receives control signal 3
, 4 as inputs, and the control signal 9 of the multiplexer MPX,
It outputs writing and output command signals 10a and 10b for the two buffer memories M1 and M2, and data establishment information 11 which becomes an input signal to the gate circuit GI.

The control signal 9 to the multiplexer MPX is an inverted version of the input signal 3. For example, a high level (hereinafter referred to as "1") controls the distribution of data to the memory MI, and a low level (hereinafter referred to as "1") controls the distribution of data to the memory MI. The multiplexer MPX is controlled so that the data is distributed to the memory M2 with the input signal "0").
Signal 10a is obtained by selecting signal 3 only when signal 9 rises, and signal 10b is obtained by selecting signal 9 only when signal 9 falls. The signal 10a has the role of a content rewriting control signal of the memory MI, and the signal 10b
has the role of a content rewriting control signal of the memory M2.

The signal level of the data establishment information 11 is inverted every time the control signal 4 is applied (from 0 to 1, from 1 to 0)
It is something to do. This signal is given to the central processing unit CPU via gate GI and serves as data establishment information. The central processing unit CPU sends a data capture command signal 5 that is generated every time task processing is completed and terminates every time data is captured, and an address that specifies the type of captured data (i.e., sampling data or data establishment information). It is designed to output signal 6.

These world powers 5 and 6 are provided to the logic circuit L2. Logic circuit L2 takes in multiplexer control signal 9 and signals 5 and 6, and outputs control signal 8a for gate G2, control signal 8b for gate G3, and control signal 7 for gate GI. The control signal 8a controls the contents of the memory MI to be sent to the central processing unit CPU via the gate G2 when the output of the multiplexer MPX selects the memory M2. The control signal 8b controls the contents of the memory M2 to be sent to the central processing unit CPU via the gate G3 when the output of the multiplexer MPX selects the memory MI. In addition, in Fig. 2, n, n+1, n+2
, . . . indicate time, To is the sampling period, Ta is the period of data establishment information, and Ta=To.

Tb indicates the acquisition period of data establishment information, Tn, Tn
+, , Tn+2 indicate the task processing time for task processing based on the data captured at each time n, n+1, and n+2. D indicates time in the relationship D=To−Tb. In the above configuration, sampled and held input data is converted into a digital signal via the A/D converter and sent to the multiplexer MPX.

This multiplexer is controlled by a control signal 9 and distributes the same input data converted into a digital signal to the memories M1 and M2 according to the level of the control signal 9. The same data stored in the memories M1 and M2 is sent from either one of the memories M1 and M2 to the central processing unit CPU via gates G2 and G3 under the control of signals 8a and 8b. The central processing unit CPU determines when to take in data from the memories M1 and M2 based on data establishment information. Data establishment information is synchronized with Ta.
1" and "0" are repeated. Therefore, the previous data establishment information is imported, and when new data establishment information is imported, exclusive OR ( EOR), and when the result is "1", it is assumed that data has been established, and the central processing unit CPU takes in the data.

As a result, the sampling data at any time n is secured in either memory MI or M2 until immediately before the sampling data at time n12 is obtained.

Therefore, for example, the interval from capturing sampling data at an arbitrary time n to capturing the next sampling data is 2 (To-Tb). That is, 7=To−Th
Even if the task processing time is larger than the maximum task processing time within one sample period defined by
), there will be no data loss. Note that under normal conditions, sampling is performed continuously at constant periodic intervals To, and the contents of the tasks that are processed at these sampling intervals are different. Processing is done in one step, and the processing time between each task is irregular. Therefore, considering these things, the following relationship becomes more general as the condition under which the above-mentioned data loss does not occur. That is, if the following condition for the total processing time of n consecutive tasks is satisfied, data loss will not occur.

As shown in equation [1], according to the embodiment of the present invention, the subordinate function has a maximum processing time for each task, Ti≦T
The constraint o-Tb changes to a constraint on the total processing time of any consecutive m tasks as shown in equation '1-, so if the processing time of each task has lengths and shorts, , [If it is within the range shown in Equation 11, there is no risk of data loss.

Furthermore, since the maximum allowable processing time for each task is limited, flexibility in controlling the processing time based on the software configuration on the computer side is increased. In contrast to this, the present embodiment eliminates the need for an increase in overhead and has the advantage of increasing computer usage efficiency. In the above embodiments, two buffer memories are provided, but the main memory may also be used.

At this time, each logic circuit and gate can also be realized by means within the central processing unit. Furthermore, the frequency dividing circuit itself may also be within the central processing unit. The data acquisition timing was performed using EOR, but it can be realized using flip-flops. Furthermore, there may be two or more buffer memories, in which case data loss can be further reduced. Further, although there is generally a plurality of analog inputs, there may be one analog input. According to the invention,
We were able to effectively eliminate data loss.

[Brief explanation of drawings]

FIG. 1 is an embodiment diagram of the present invention, and FIG. 2 is an external waveform diagram. CPU.・・・．・Central processing unit, M1, M2...
・・Buffer memory, DV・・・Frequency dividing circuit. *;Figure 2

Claims (1)

[Claims] 1. In a data acquisition method that converts sampling data into a digital signal and imports the digital signal obtained by the conversion into a computer, the same sampled data is alternately stored in two storage devices at a predetermined period. Detection of the state of information indicating that the sampling data at the time of generation of the command has been established, based on a data import command generated in the computer itself after completion of task processing within the computer based on the sampling data. and, based on the detection results, alternately import corresponding data from among the data stored separately in each of the storage devices into the computer from each of the storage devices each time the data import command is generated. Characteristic data import method.