JPS63106595A - Electronic timepiece - Google Patents

Abstract

PURPOSE:To improve the precision in measurement of a daily deviation by a method wherein adjustment data outputted from a means to store and hold an amount of lag or gain are distributed in a time-sharing manner and outputted to a logic regulation means so as to shorten the period of a logic regulation operation. CONSTITUTION:Binary adjustment data P0-P4 outputted from a laggain amount holding means 3 pass through a binary-decimal conversion circuit 5, and they are converted into a binarized decimal number (position of 10 and position of 1) and inputted to a data distributor 6. The distributor 6 receives as an input the binarized decimal number of a position of 10 and a position of 1 and outputs a logic regulation amount in every one second to an n-bit preset circuit 7. Meanwhile, a control circuit 4 outputs a periodic signal to the circuit 7 and the distributor 6. A logic regulation operation is conducted every one second by the number of times given to the position of 10, and a regulation operation is conducted every 10sec by the number of times given to the position of 1. By this method, the precision of measurement of the daily deviation can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a logic adjustment circuit for adjusting the delay or lead of a crystal oscillator in an electronic timepiece, particularly a high-precision electronic timepiece.

[Summary of the invention]

The present invention provides adjustment data for time-divisionally distributing adjustment data output from means for storing and storing the amount of delay or advance of a crystal oscillator in the entire logical adjustment circuit of an electronic timepiece, and outputting adjustment data to the logical adjustment means. By adding a distributor (hereinafter simply referred to as a data distributor) and shortening the period of logical slowing/sudden operation, daily difference measurement can be performed without increasing the measurement time of daily difference measurement, which is a type of rate measurement method for electronic watches. This makes it possible to improve the measurement accuracy of measurements.

[Conventional technology]

Conventionally, as shown in FIG. 2(a), there is only a latch or the like between the lag/advance star jQ holding means and the preset circuit, and the data (Pφ~P) output from the lag/advance storage holding means is
3) was given directly to the preset circuit.

The conventional logical adjustment operation will be explained below with reference to the drawings. Second
Figures (a) and (b) are a block diagram and a time chart thereof showing a conventional example. In the conventional example shown in FIG. 2(a), the data of the lagging star memory holding means is 4.
It is shown in bits, but it does not have to be 4bH, and the logical adjustment means is shown as a preset method in which a part of the frequency dividing circuit is preset to the content set in the delay/advance amount memory storage means. However, an interrupt method may also be used in which a gate is provided between the oscillation circuit and the frequency dividing circuit, and the gate generates interrupt signals as many as the number set in the delay/advance storage/holding means. The data (Pφ to P3) output from the lag/advance storage storage means is normally output 0.5 seconds after the reset is released, and thereafter the signal LCL is output at a 10 second cycle.
Retained at lunch by IO. Latch output data (
Vφ~V3) is output to a 4-bit preset circuit, and 4
The bit precent circuit sets or resets a part of the frequency dividing circuit to data (■φ~V3) at the rising edge of PVCWIO.

It performs slow and fast movements by pressing the button. The oscillation frequency of the normal oscillation circuit is 3276 B+1Z, PVCWl
Since the output cycle of o is 10 seconds, if the data of the lag/advance storage storage means is N, then the average logical slow/slow amount for 10 seconds is △
f/f (x) is expressed by the formula 0.

8f/f(x) - Sat N/327680 - 00
The amount of acceleration/reduction expressed by the formula is just an average over 10 seconds, and the amount of acceleration/reduction for each second is as shown in FIG. 6(a). In other words, the amount of slowing/slowing per second is expressed by the formula 0 at T1.

△r/r (TI)-±N/ 32768 -,-,
- ■For 1 second other than T1, it is expressed by the 0 formula.

△f/f(Tφ>=0 −−−−・−・−1−−−
−−・−・−・−−−1−−−−−・− Conventional logical adjustment such as 0 or more has no problem in actual use of the watch, but
Problems arise when measuring daily differences.

[Problem that the invention seeks to solve]

Diurnal measurements are typically performed on high-precision clocks.

The method is to detect the magnetic field generated when the 1-second period standard No. 13 and the clock's motor drive, measure the time difference, operate the clock continuously for about a day, and then compare the standard No. 13 and the clock's motor drive again. By measuring the time difference between 2 and 3, it is possible to measure the lag or advance of the clock over the course of a day. According to this method, rate can be measured with higher accuracy and reliability than when using normal instantaneous rate measurement.

However, since the reference signal has a period of 1 second, the time difference between the reference signal and the motor drive can be measured from Tφ to T in Fig. 6(a).
It is uncertain at which timing of 9 the measurement is performed. Therefore, in the worst case, one of the two time difference measurements is T1 and the other is T1.
This is done at the timing of 2. In other words, if the time difference measurement is performed immediately before and after the logical adjustment that is performed in a 10-second period, an error will occur due to the adjustment data N. The error △fg
Assuming that the delay/advance storage storage means has a maximum of 5 bits, /r is expressed by the formula 0 when NfJ<maximum 31.

△f g/f=31/32768 (sec/day
) -■This error is equivalent to approximately 0.4 seconds per year, and is a star that cannot be ignored in a high-precision clock. Furthermore, if the temperature compensation of the crystal in a high-precision timepiece is also performed by logical adjustment, the error will double or triple because there will be two or three systems of logical adjustment means. In order to reduce these errors, the reference signal was set to have a period of 10 seconds, but this method took a long time to measure the time difference.

[Means for solving problems]

In order to solve the above problem, in the present invention, by adding a data distributor between the lagging star memory holding means and the precent circuit, the adjustment data is distributed in a time-division manner, and the logical adjustment is performed every second. , made it work.

[Effect]

According to the above configuration, since the adjustment data is distributed every second and logical adjustment is performed, the error △rg/f that occurs when measuring the daily difference is calculated based on the standard No. 13 with a period of 1 second. Also, it is 1/32768 [sec/day] at most.

This error corresponds to approximately 0.01 seconds per year, and is almost negligible even in high-precision clocks.

〔Example〕

Embodiments of the present invention will be described below based on the drawings.

FIG. 1 is a block diagram showing the basic configuration of the entire logic regulation circuit according to the present invention. In FIG. 1, binary adjustment data (Pφ~
P4) passes through a binary-decimal conversion circuit, is converted into a binary-coded decimal number (tens digit and ones digit), and is input to the data distributor. The binary-to-decimal conversion circuit is a commonly known circuit, and it may be configured such that the binary-coded decimal number is directly given to the data distributor from the lag/lead amount storage means without passing through the binary/IO conversion circuit. do not have. Data distributor is tens place and 1
A binary coded decimal number is input, and the logical adjustment amount per second is output to the nbit preset circuit. The nbit recent circuit presets a part of the frequency dividing circuit to a state corresponding to the logical adjustment amount input from the data distributor. On the other hand, the control circuit outputs periodic signals to the preset circuit and data distributor.

FIG. 3(a) is a circuit diagram showing more specifically the dotted line indicated by 8 in FIG. 1, and FIG. 3(b) is a time chart diagram showing an example of the control signals necessary for this. be. below,
The operation of FIG. 3<a) will be explained. The general operation is that the pre-sent circuit operates every second for the number of times given to the tens digit, and the preset circuit operates every 10 seconds for the number of times given to the ones digit. The 2-bit counter 610 is reset at one-second intervals by the signal RESETI, and counts up at the rising edge of the signal pvcWl/4. When the content of the 2-bit counter matches the value in the tens place, the output of the gate 612 becomes Low, and the signal PVCWI/4 is inhibited by the gate 614 and is no longer transmitted to the preset circuit and the 2-bit counter 610. Therefore, the preset circuit 71 receives 10
The signal PVCWI/4 is transmitted the number of times given to the digit, and the logical speed and speed operation is performed. The operation of the 1's digit is the same as that of the 10's digit, and since the signal RESETIO is output at a 10 second cycle and the PVCWI is output at a 1 second cycle, the 1's digit is output to the precent circuit 71.
signal PVCWI for the given number of times in the ones place every 0 seconds
is transmitted and operates logically. Due to the above circuit operation,
The theoretical adjustment amount for 10 seconds is N1° for the 100th place and N for the 1st place.
If it is 1, then (IOXN, o+N+) / 32768 (s
ec). In this case, the theoretical adjustment amount per second is N1°=1. If N+=3, the result will be as shown in FIG. 6(b).

FIG. 4(a) is also another circuit diagram showing more specifically the dotted line indicated by 8 in FIG. 1, and FIG. 4(b) is a time chart showing an example of the control signals necessary for this. It is a diagram. The outline of the operation is the numerical value given to the tens place, which is 2 every second.
The bit preset circuit operates, and only the circuit given to the digit (■) operates every 10 seconds.

The 2-bit recent circuit B72 is a conventionally known circuit that performs logical slowing/slowing operation by the numerical value given to the data input terminals Dφ and DI when the input terminal P rises. Data input terminal Dφ of 2-bit preset circuit 72
, DI are directly given a numerical value in the 10's digit at the timing of fli of the signal IQ, and operate logically according to the numerical value at the rising edge of the signal pvCW. 4 bit counter 6
20. The operations of the gate 621 and the gate 626 are shown in FIG.
It is similar to that in a), and the contents of the counter are incremented every second by the signal UPI, and continue counting up until one loss is reached.

Until the contents match, the gate 621 outputs the old signal, so the old signal is applied to the input terminal Dφ of the 2-bit precent circuit at the timing when the No. 13 IQ is Lo-, and the logic speed and speed operation is performed every second with a speed and speed amount of 1. With the above circuit operation, the 10-second logical slowdown ■ is calculated by changing the tens place to N as in Example 1 of Part 3 (a).
+o, if the 1s digit is N, (IOXN, o+N+)/
32768 (sec). In this case, the theoretical adjustment amount per second is also as shown in FIG. 6(b), as in the first embodiment.

FIG. 5(a) is another circuit diagram showing more specifically the dotted line indicated by A in FIG. 1, and FIG. 5(b) is a time chart showing an example of the control signals necessary for this. It is a diagram. The outline of the operation is that the number given to the tens place every second is 3b
It is preset to the 3-bit presettable counter 630 until the contents of the 4-bit counter 631 match the contents of the 1's digit.
The contents of 30 are incremented by 1, the result is output to the 3-bit precent circuit 73, and the logical speed is operated by the numerical value outputted every second. When a single pulse is input to the input terminal P of the 3-bit pre-centered counter 630, the data input terminals Dφ, D1 . This is a conventionally known circuit in which the data applied to D2 is preset into a counter, and when the input terminal U falls, the contents of the counter are incremented by one. The 3-bit presettable counter 630 is set to 1 by the signal PRESETI output every second.
The contents of the 0's digit are precented every second.*4btt counter 631 outputs a signal RESET every 10 seconds.
Its contents are cleared by IO, and the signal pvc is output every second until the value matches the value given to the l digit.
+1 is added by w. 4bit counter 631 and 1
Since the gate 632 outputs fli until the contents of the digit match, the signal UPI is transmitted to the input terminal U of the 3-bit precenter pull counter 630, and the 3-bit
The content of the Briscentaple counter is increased by +7.

The 3-bit preset circuit 73 operates logically according to the numerical value held in the 3-bit pre-center pull counter 630 by the signal pvcw outputted every second.

Due to the above circuit operation, the logical adjustment amount for 10 seconds is (10XN+o+N+) / 32768 (sec
It is J'. In this case, the theoretical adjustment amount per second is also as shown in FIG. 6(b), as in the first embodiment.

Although all of the logic adjustment means in the above embodiments are shown using the precent method, they can also be implemented using an interrupt method in which an interrupt signal is generated between the oscillation circuit and the frequency dividing circuit.

〔Effect of the invention〕

According to the present invention, by simply adding a simple logic circuit, it is possible to dramatically improve the measurement accuracy of daily difference measurement without increasing the measurement time of daily difference measurement. For example, the reference signal used for daily difference measurement has a period of 1 second, and with the conventional logical adjustment system that has a 6-bit lag/advance memory storage means, a maximum annual difference of about 0.7 seconds (I + fixed difference) will occur. On the other hand, if the logical adjustment according to the present invention is used, it is possible to reduce the measurement error to about 0.01 seconds per year at the maximum under the same measurement conditions.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment according to the present invention. Figure 2(a) is a block diagram showing a conventional example, Figure 2(b)
is a time chart diagram showing the control signal, FIG. 3(a)
, FIG. 4(a) and FIG. 5(a) are circuit diagrams showing Embodiment 1, Embodiment 2, and Embodiment 3, respectively, of a data distributor according to the present invention. FIG. 3(b), FIG. 4(b), and FIG. 5(b) are time charts showing control signals of the first embodiment, the second embodiment, and the third embodiment of the data distributor according to the present invention, respectively. FIG. 6(a) is a time chart diagram showing an example of the conventional example 413, ■. FIG. 6(b) is a time chart diagram showing an example of a gradual and rapid layer according to the present invention. 1... Crystal oscillation circuit 2... Frequency divider circuit 3... Lag/lead ■ Memory holding means 4... Control circuit 5... Binary/decimal conversion circuit 6... Data distributor 7...・Applicant for nbit precent circuit and above Seiko Electronics Co., Ltd. June 2015
Figure 212I (a) Figure 212I (a) Figure 3 (a) Figure 4 (a) Schematic diagram of the large bag example 2 of the tuff arrangement.

Claims (1)

[Scope of Claims] An electronic timepiece comprising a crystal oscillator, a logical adjustment means for adjusting the delay or lead of the crystal oscillator, and a means for storing the delay or lead amount of the crystal oscillator, comprising: It is characterized by having an adjustment data distributor that distributes the adjustment data outputted from the means for storing and holding the advance amount in a time division manner and outputting the adjustment data to the logical adjustment means, and shortens the period of the logical adjustment and adjustment operation. Electronic clock.