JP2662779B2 - Electronic clock - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic circuit for adjusting the delay or advance of a crystal oscillator in an electronic timepiece, particularly in a high-accuracy electronic timepiece. [Summary of the Invention] The present invention distributes, in a time-division manner, adjustment data output from a means for storing and holding a delay or advance amount of a crystal oscillator in an entire logic slow / fast circuit of an electronic timepiece, and adjusts the adjusted data to a logic slow / fast means. By adding an adjustment data distributor (hereinafter simply referred to as a data distributor) that outputs the clock, and shortening the cycle of the logical slowing / starting operation, the measurement time of the day-to-day measurement, which is a type of electronic clock rate measurement method, can be extended. Thus, it is possible to improve the measurement accuracy of the day difference measurement without performing the measurement. [Prior Art] Conventionally, as shown in FIG. 2 (a), only a latch or the like is provided between the delay / advance amount storage and holding means and the preset circuit, and data (P0 ~ P
3) was given directly to the preset circuit. Hereinafter, the conventional logic operation will be described with reference to the drawings. 2 (a) and 2 (b) are a block diagram showing a conventional example and a time chart thereof. In the conventional example shown in FIG. 2 (a), the data of the delay / advance amount storage and holding means is 4b.
Although it is indicated by it, it is not particularly required to be 4 bits, and the logic deceleration means is shown by a preset method in which a part of the frequency dividing circuit is preset to the content set in the delay advance amount storage means. However, an interrupt method may be used in which a gate is provided between the oscillation circuit and the frequency dividing circuit, and the number of interrupt signals generated in the gate is equal to the number set in the delay / advance amount storage means. The data (P0 to P3) output from the delay / lead amount storage and holding means is normally output 0.5 seconds after the reset is released, and thereafter held in a latch by a signal LCL10 output at a cycle of 10 seconds. The latch output data (V0 to V3) is output to the 4-bit preset circuit, and the 4-bit preset circuit is PVCW10
By setting or resetting a part of the frequency dividing circuit to the data (V0 to V3) at the rise of, the slow / fast operation is performed. Since the oscillation frequency of the normal oscillation circuit is 32768 Hz and the output cycle of the PVCW10 is 10 seconds, assuming that the data of the delay / advance amount storage means is N, the average logical change amount Δf / f for 10 seconds
Is represented by an equation. Δf / f () = ± N / 327680 The amount of acceleration / deceleration represented by the equation is merely an average for 10 seconds, and the amount of acceleration / acceleration every second is as shown in FIG. 6 (a).
That is, the acceleration / deceleration amount per second is represented by an equation at T1. Δf / f (T1) = ± N / 32768 In one second other than T1, it is expressed by an equation. Δf / f (T0) = 0... The above-described conventional logic regulation does not cause any problem in the actual use of the clock, but causes a problem in the day-to-day measurement. [Problems to be Solved by the Invention] The day difference measurement is usually performed on a high-precision timepiece. The method detects a reference signal having a one-second cycle and a magnetic field generated when the clock of the clock is driven, measures a time difference between the signals, continuously operates the clock for about one day, and again determines a time difference between the reference signal and the motor drive of the clock. Is measured to measure the advance of the clock in one day. According to this method, the rate can be measured with higher accuracy and reliability than in the case of normal instantaneous rate measurement. However, since the reference signal has a one-second cycle, the time difference measurement between the reference signal and the motor drive is performed according to T0 to T9 in FIG.
It is uncertain at what timing of measurement. Therefore, in the worst case, one of the two time difference measurements is performed at the timing of T1, and the other is performed at the timing of T2. That is, if the time difference measurement is performed immediately before and immediately after the logical acceleration / deceleration performed in a cycle of 10 seconds, an error due to the acceleration / deceleration data N occurs. The error Δfg / f is expressed by an equation when N is 31 at the maximum, assuming that the delay / advance amount storage and holding means is 5 bits at the maximum. Δfg / f = 31/32768 [sec / day] …… This error is equivalent to about 0.4 seconds per year, which is too much for a high precision timepiece. Further, in the case where the temperature of the crystal is also compensated for in a high-accuracy timepiece by logic slowing or slowing, the error is doubled and tripled because the number of logic slowing and slowing means is two or three. In order to reduce these errors, the reference signal is set at a period of 10 seconds. However, this method has a problem in that the time difference measurement takes a long time. [Means for Solving the Problems] In order to solve the above problems, in the present invention, by adding a data distributor between the delay lead amount storage and holding means and the preset circuit, the adjustment data is time-divided. Logically, and a logical acceleration / deceleration operation is performed every second. [Operation] According to the configuration as described above, since the adjustment data is distributed every second and the logical acceleration / deceleration operation is performed, the error Δfg / f generated at the time of measuring the day difference is determined by setting the reference signal to a one-second cycle. Even
It is at most 1/32768 [sec / day]. This error is equivalent to about 0.01 second per year, which is almost impossible even for a high-precision watch. Embodiment An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the basic configuration of the entire logic regulation circuit according to the present invention. In FIG. 1, binary adjustment data (P0 to
P4) passes through a binary-decimal conversion circuit, is converted into a binary-coded decimal number (a tens place and a ones place), and is input to a data distributor. 2
The decimal-to-decimal conversion circuit is a general known circuit, and may have a configuration in which a binary-coded decimal number is directly supplied to the data distributor without passing through the binary-decimal conversion circuit from the delay / lead amount storage means. . The data distributor inputs the binary digit of the tens place and the ones place, and outputs the amount of logical acceleration / deceleration every second to the nbit preset circuit. The n-bit preset circuit presets a part of the frequency dividing circuit in a state corresponding to the amount of logical acceleration / deceleration input from the data distributor. On the other hand, the control circuit outputs a periodic signal to the preset circuit and the data distributor. FIG. 3 (a) is a circuit diagram more specifically showing the inside of the dotted line indicated by A in FIG. 1, and FIG. 3 (b) is a time chart showing an example of a control signal required for this. is there. Hereinafter, the operation of FIG. 3A will be described. The outline of the operation is that the preset circuit operates every tenth of the number given to the tens place, and the preset circuit operates every ten seconds of the number given to the ones place. The 2-bit counter 610 is reset every 1 second by the signal RESET1, and counts up at the rising edge of the signal PVCW1 / 4. When the content of the 2-bit counter matches the value of the tens place, gate 612
Becomes low, the signal PVCW1 / 4 is inhibited by the gate 614, and is not transmitted to the preset circuit and the 2-bit counter 610. Therefore, the preset circuit 71 is
The signal PVCW1 / 4 is transmitted the number of times given in the tens place, and the logic operates slowly. The operation of the tens place is the same as that of the tens place,
Since the signal RESET10 is output at a cycle of 10 seconds and the PVCW1 is output at a cycle of 1 second, the signal PVCW1 is transmitted to the preset circuit 71 the number of times given to the first place every 10 seconds, and the logic circuit operates slowly.
With the above circuit operation, the amount of logical acceleration / deceleration for 10 seconds is in the tens place
Assuming that the place of N ₁₀ and 1 is N ₁ , (10 × N ₁₀ + N ₁ ) / 32768 [sec]. In this case, the logical acceleration / deceleration amount per second is N ₁₀ = 1, N ₁
If = 3, the result is as shown in FIG. 6 (b). FIG. 4 (a) is another circuit diagram more specifically showing the inside of the dotted line indicated by A in FIG. 1, and FIG. 4 (b) is a time chart showing an example of control signals required for this. FIG.
The outline of the operation is a numerical value given in the tens place, 2b every second
The it preset circuit operates, and the preset circuit operates every ten seconds for the number of times given to the first place. The 2-bit preset circuit 72 is a conventionally known circuit in which when the input terminal P rises, the logic operation is performed by a numerical value given to the data input terminals D0 and D1.
The data input terminals Dφ and D1 of the 2-bit preset circuit 72 are given a tens digit directly at the timing when the signal 1Q is Hi,
At the rise of the signal PVCW, the logical operation is performed by the numerical value. The operation of the 4-bit counter 620, the gate 621, and the gate 626 is the same as that of FIG.
The content of the counter increases by 1 and counts up until it matches the content of the first place. Until the contents match, since the gate 621 outputs Hi, Hi is applied to the input terminal D0 of the 2-bit preset circuit at the timing when the signal 1Q is Low, and the logical slowing / fastening operation is performed every second at a slack amount of 1. With the above circuit operation, the amount of logical acceleration / deceleration for 10 seconds is the third
In the same manner as in the first embodiment in FIG. 9A, assuming that the tens place is N ₁₀ and the ones place is N ₁ , (10 × N ₁₀ + N ₁ ) / 32768 [sec]. In this case, the amount of logical acceleration / deceleration for each second is also as shown in FIG. 6B as in the first embodiment. FIG. 5 (a) is another circuit diagram more specifically showing the inside of the dotted line indicated by A in FIG. 1, and FIG. 5 (b) is a time chart showing an example of control signals necessary for this. FIG. The outline of the operation is as follows. The value assigned to the tens place every second is preset in the 3-bit presettable counter 630. Until the contents of the 4-bit counter 631 match the contents of the ones place, 3
The content of the bit presettable 630 is incremented by one, and the result is output to the 3-bit preset circuit 73, and the logic operation is performed by the numerical value output every second. 3b
The it presettable counter 630 is configured such that when one pulse is input to the input terminal P, the data supplied to the data input terminals Dφ, D1 and D2 are preset to the counter, and when the input terminal U falls, the content of the counter is incremented by +1. This is a conventionally known circuit. The content of the tenth place is preset to the 3-bit presettable 630 every second by the signal PRESET1 output every second. 10 for 4bit counter 631
The content is cleared by a signal RESET10 output every second and is incremented by 1 by a signal PVCW output every second until the value matches the value given in the ones place. Until the contents of the 4-bit counter 631 and the ones digit match, the gate 632 remains
Since Hi is output, the signal UP1 is transmitted to the input terminal U of the 3-bit presettable counter 630, and the contents of the 3-bit presettable counter are incremented by 1. The signal PVCW output every second causes the 3-bit preset circuit 73 to operate logically faster and slower by the numerical value held in the 3-bit presettable counter 630. By the circuit operation described above, the amount of logical acceleration / deceleration for 10 seconds is obtained by assuming that the tens place is N ₁₀ and the 1 place is N ₁ as in the first embodiment of FIG. 3 (a). (10 × N ₁₀ + N ₁ ) / 32768 [sec]. In this case, the amount of logical acceleration / deceleration for each second is also as shown in FIG. 6B as in the first embodiment. Although the logic moderating means of the above embodiments are all shown in the preset system, it is also possible to carry out the present invention by an interrupt system in which an interrupt signal is generated between the oscillation circuit and the frequency dividing circuit. [Effects of the Invention] According to the present invention, it is possible to dramatically improve the measurement accuracy of daylight measurement without increasing the measurement time of daylight measurement simply by adding a simple logic circuit. For example, while the reference signal used for measuring the day difference has a one-second cycle, the conventional logic having a 5-bit delay lead amount storage and holding means causes a measurement error of about 0.4 second at a maximum in contrast to the present invention. If the logic slowdown is used, the maximum difference is about a year under the same measurement conditions.
A measurement error of 0.01 seconds is possible.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment according to the present invention. 2 (a) is a block diagram showing a conventional example, FIG. 2 (b) is a time chart showing the control signals, and FIGS. 3 (a) and 4 (b).
5 (a) and 5 (a) are circuit diagrams showing Embodiment 1, Embodiment 2 and Embodiment 3 of a data distributor according to the present invention, respectively. FIGS. 3 (b), 4 (b) and 5 (b) are time charts showing control signals of the first, second and third embodiments of the data distributor according to the present invention, respectively. FIG. 6A is a time chart showing an example of the amount of acceleration and deceleration in the conventional example. FIG. 6B is a time chart showing an example of the amount of acceleration and deceleration according to the present invention. 1 ... Crystal oscillation circuit 2 ... Division circuit 3 ... Delay / lead amount storage / holding means 4 ... Control circuit 5 ... Binary / decimal conversion circuit 6 ... Data distributor 7 ... Nbit preset circuit

Claims (1)

(57) [Claims] A crystal oscillator, a logic controller for adjusting the delay or advance of the crystal oscillator, and a delay for storing and holding the amount of delay or advance of the crystal oscillator in a predetermined time period longer than 1 second as adjustment data composed of a plurality of digits. An electronic timepiece having an advance amount storage and holding means, wherein the adjustment data is divided into a lower digit and an upper digit, and a numerical value corresponding to each digit is divided in a time-division manner and output to the logical acceleration / deceleration means. A distributor, wherein the logic moderator responds to the time-division-divided upper digit data over all of a plurality of periods shorter than the predetermined time period constituting the predetermined time period, and In response to the lower-order data divided in a time-division manner in a part of a plurality of periods shorter than the predetermined time period constituting a time period, a time-averaged logical moderation is performed in response to the lower-order data. Electronic timepiece characterized in that it is configured to perform the work. 2. 2. The electronic timepiece according to claim 1, wherein the predetermined time period is 10 seconds. 3. 2. The electronic timepiece according to claim 1, wherein the period shorter than the predetermined time period is one second.