SU1128187A1 - Digital phase meter - Google Patents

Abstract

A DIGITAL PHASOMETER containing the first and second drivers, a control generator, a unit for determining the number of cycles, a pulse counter, a reversible pulse counter, a first memory register and a delay line; the first input of the phase meter through the first driver is connected to the input of the controlled generator, the first input of the cycle number determination unit and the input of the zero setting of the pulse counter, and the second phase phase input through the second driver connected to the second input of the cycle number detection unit and through the delay line to the input records in the high-order bits of the first memory register, whose inputs are connected to the outputs of the pulse counter and the reversing pulse counter, the output of the controlled generator is connected to the input of the pulse counter s, and the third input cycle number determining unit. the outputs of which are connected to the input of the pulse counter, which is different in that, in order to increase its accuracy, it is equipped with an arithmetic logic unit, the second and third memory registers, a digital indicator, a control unit, a sign trigger, an inverter and an installation unit zero, and the outputs of the arithmetic logic node through the second memory register are connected to the inputs of the third register, digital indicator and the second inputs of the arithmetic logic node, the first inputs of which are connected to the same output mi first and third memory registers, in addition,. the first bits of the first and third memory registers are connected in parallel with the higher bits of the first input of the arithmetic logic unit; the last bits of the second memory register are three, the character's gauge is connected to the inputs of the sign bits of the third memory register, the digital indicator, and the first the input of the control unit, the second input of which is connected to the output of the controlled generator, the first outputs of the control unit are connected respectively to the control inputs of the arithmetic logic unit, the second and third outputs N3 00, respectively dispenses with the recording and control inputs of the second shift register memory, fourth, fifth and sixth outputs 00 - respectively to the inputs | recording the trigger of the digit, digital indicator and third memory register, the output of the second driver is connected to the control inputs and writing to the lower bits of the first memory register directly, and to the control inputs of the third memory register via inverter, reverse zero counter settings impulses of the first, second and third memory registers are connected to the output of the zero setting block

Description

1 The invention relates to a phase-measuring technique and can be used to measure shifts in excess of 360 °. A digital phase meter is known for measuring large phase shifts that contains input drivers, switches, clock generator, dividers, reversible counters, a binary phase quantizer, an equivalence block, an OR circuit, and an inverter 1. Measurement in this device is performed in one period of the studied signals by their zero-transitions, therefore, it has a low measurement accuracy in the presence of noise in the input signals causing fluctuations of the zero-transitions. The closest in technical terms to the present invention is a measurement of phase displacements exceeding 360 °, a cumulative phase meter that contains the first and second drivers, a generator, a cycle number determination circuit, a counter pulse counter, a pulse counter, a memory register delay line, two digital-to-analogue converters and an adder, the first input of the phase meter Through the first .wirer connected to the first input - a circuit for determining the number of the cyclo and the input of the devices of the pulse counter. and the second input of the phase meter through the second transformer is connected to the second input of the Scheli circuit. cycles and through the delay line to the input of the register register m, the inputs of which are connected to the outputs of the pulse counter and reversible pulse counter, the generator output is connected to the input of the pulse counter and the third input of the cycle number determination circuit c) Codes of which are connected to the input of the reverse pulse counter The input of digital-to-analog converters is connected to the high and low bits of the memory register, and the outputs are connected to the inputs of the adder, the output of which is connected to the output of the phase meter. In the dstm phase meter, each phase of the input signal is converted, the phase shift of the input signals into a digital code obtained in the phase shift meter. When the phase shift changes by more than 241, the code of the reversible pulse counter, character 7., J changes the integer number of cycles. Phase shift codes and cycle numbers are written to memory registers, then converted to direct current voltage using digital-to-analog converters, corresponding to the measured phase shift and speed 21. A disadvantage of the known phase meter is low measurement accuracy due to fluctuations of zero-transitions input signals caused by the action of noise and interference, in addition, the measurement result is an analogue value - voltage, which makes it difficult to use together with the means E computing. The purpose of the invention is to improve the accuracy of measurement of cumulative phase shifts. . ; . . The goal is achieved by having a digital phase meter containing the first and second drivers, a controlled oscillator, a unit for determining the number of cycles, a pulse count, a reversible pulse counter, a first memory register, and a delay line, the first input of the phase meter the first driver is connected to the input of the controlled oscillator, the first input of the cycle number determining unit and the input of the zero setting of the pulse counter, and the second phaseometer input through the second driver is connected to the second input of the number determination unit shslov And through; the delay line to the input to the high-order bits of the first memory register, whose inputs are connected to the outputs of the pulse counter and the reversible pulse counter, the output of the controlled generator is connected to the input of the pulse counter and the third input of the cycle-determining unit whose outputs are connected to the inputs reversible pulse counter, additionally equipped with an arithmetic-logic, knot, second and third memory registers, a digital indicator, a control unit, a sign trigger, an inverter and a zero setting unit, with the outputs of the arithmetic unit through the second memory register are connected to the inputs of the third memory register, digital indicator and the second inputs of the arithmetic logic node, the first inputs of which are connected to the same outputs 3 of the first and third memory registers; the third memory registers are connected to the higher digits of the first input of the arithmetic logic node; the last bit of the second memory register is connected to the inputs of the sign bits of the third memory register, the first indicator of the control unit, the second input of which is connected to the output of the controlled generator, the first outputs of the control unit are connected respectively to the control inputs of the arithmetic logic node, the second and third outputs, respectively, the recording and shift control inputs of the Second Register memory, the fourth, fifth and sixth outputs - respectively with the inputs of the recording of the character Trigger, the digital indicator and the third memory register; the output of the second driver is connected to the inputs of the control and recording bits of the first register memory directly, and to the inputs of the third register uyravleii memory - via inverter, a zero setting inputs of the reversible pulse counter and the first, second and third memory registers connected to the output setting unit zero. On . 1 shows the functionality of the phase meter circuit; Fig. 2 shows the voltage displays explaining the operation of the phase meter. The digital phase meter contains the formers 1 and 2, the inputs of which are connected respectively to the inputs 3 and 4 of the phase meter, the block 5 for determining the number of cycles (revolutions), the first and second inputs of which are connected respectively to the outputs of the formers 1 and 2, and the outputs to the reverse inputs The counter of 6 pulses, the controlled generator of 7 clock pulses, the input of which is connected to the output of the first driver 1, and the output to the synchronization input of the block of determining the number of cycles and the counting input of the counter 8 pulses, set input to the output of the first shaper 1, the first register 9, memory, inputs, low bits of which are connected to the outputs of the counter .8, MSB inputs - outputs to the down counter 6, the record entry in the lower bits - to the output of the second formirova74. bodies 2, and the records in the higher bits are connected to the output of the second driver 2 via the delay line 1.0, the arithmetic logic node 11 ,. the first inputs of which are connected to the corresponding outputs of the second register 12 of memory, the second inputs to the corresponding outputs of registers 9 and 13 of the memory, and the highest bit of registers 9 and 13 is connected in parallel with the second I inputs of the higher bits of node P, the output which is connected to the corresponding inputs of the register 12, the control inputs of the node 11 are connected to the first outputs of the block 14. 15 controls, the outputs of the register 12 are connected to the corresponding inputs of the digital register 13. 16. The output of the last, most significant bit of register 12 is connected to the trigger input of 17 characters, the synchronization input is connected to the fourth output 18 of block 15, and the output to the corresponding inputs of register 13, indicator 16. and the first inputs 19 of block 15. Recording outputs and the shift control register 12 is connected respectively to the second and third outputs 20 and 21 of block 15, the synchronization input of indicator 16 and the synchronization input of register 13 are connected respectively to the fifth and sixth outputs 22 and 23 of block 15, the second input 24 of which is connected to the output of controlled g 7. The output generator of the generator 2 is connected to vhodu.upravleni register 9 directly and to the input 13 of the control - through an inverter 25, the zero setting inputs of the counter registers 6 and 9, 12 and 13 connected to the output setting unit 26 zero. ., The device measures several values of phase shifts, taking into account their signs, averages these values, and corrects the result, taking into account the phase shift N, obtained during the installation of the vessel. Phase shift measurement result can be represented by the formula 2 r2: (+ W I 1 about 360 ° - measurement discreteness, where 2m phase shift, determined by counter width 8;,. Ffi - number of counter bits 8} j Nj - the number code of cycles, determined by the output code of the reversible counter 6 2 - the number of averaged measurement results, V - 1 9 l d ,, The device works as follows. Harmonic signals, the phase shift between which is to be measured (Fig.2o1. B), are fed to inputs 3 and 4 phase meters. Formers 1 and 2 are formed from the input signals of the forward signal. square pulses (figure 2 v. g), whose fronts soft their zero transitions. Block 5 determines the number of cycles on one of the outputs by a pulse when the phase shift between signals changes by more than 360 This pulse increases or decreases the code N of the counter 6 per unit .. When measuring; phase shifts within 360 N) T, o (it where the maximum measured number of cycles, the volume of the reversing counter should be chosen equal to 2, while the high bit of counter 6 is significant, and the positive the sign of the phase shift corresponds to ogichesky zero output sign bit, and a negative sign .skay logical unit. In FIG. 1, the phase meter circuit is received M. From the output of the reversible counter 6, the N code and the sign code of the leading edges of the pulses from the output of the driver 2, delayed: line 10 delay for the response time of the cycle number determining unit 5 and the reversing counter 6, are rewritten into the high register bits . The controlled oscillator 7 forms a sequence of pulses of frequency (2) where ix is the frequency of the Input signals, the phase meter. These pulses are continuously fed to the input of the phase shift counter 8, the capacitance of which is chosen equal to 2. Counter 8 is set to zero state by the leading edge of the pulses of the former 1 at time points 1, b, tj, i.2K, 3, 4-247 4- 2 +1. (Fig. 2 c). At times ij, i. ,, i., J, ..., 4-g + 4 4-2 + 8 2 t). corresponding to the leading edges of the pulses at the output of the imager 2, in the meter 8, the LM codes are formed, corresponding to the value of the measured phase shift. The LM codes are rewritten into the lower bits of the register 9 by the leading edges of the pulses from the output of the former 2. Thus, in each measurement cycle in register 9, codes are obtained that correspond to values of the measured phase shift, number of cycles, and sign. These codes are fed to the inputs of the arithmetic-logic node 11 for subsequent transformations. The arithmetic logic unit 11 accumulates the measurement results of 2 + & H taking into account the sign, transforms the received code and subtracts the value of the initial one. phase shift y, expressed by the code 4N (j. To do this, the control inputs of the node 11 are outputted from the output 14–15 to a group of control signals. For example, at time intervals Us.iv A. signals, under the influence of which the phase shift code measured in the last cycle is added to the node 11. The outputs of the register 9 are influenced by a signal (Fig. 2d) at its control input to the first inputs of the node 11 C) Banbi time1 - ,, „, 4-t ti% -i + & The unit 15 at the output 14 of the fort mirrors a group of control signals, under the influence of which the node 11 performs the subtraction of the LF code recorded in the register 13 from the measurement result. In this case, the outputs of register 9 are turned off, and the outputs of register 13 under the influence of a control signal at its input are connected to the first inputs of node 11. Obtained at the output of node 11, the result codes of arithmetic operations indicated above are stored in register 12. when another pulse arrives at the input records of this register from the output 20 of block 15 (Fig. 23). When the measured phase shift is changed to a negative overlap or the phase shift changes from 0 to -2.3fM in counters 8 and 6, the measurement result is represented by an additional code, so the hebraic addition of the measurement results of each clock cycle is performed without additional code conversions.

The volume of the arithmetic logic unit 11 and the register 12 is chosen to learn the required number of cycles required for averaging the measurement results, so that the arithmetic logic unit 11 and the register 12 do not overflow. In the phase meter, the diagram is shown in FIG. , the number of measurement cycles is chosen 2, therefore, the number of bits of node 11 and register 12 must be m + n + k binary bits.

After performing the required number of measurement cycles over the time interval Tjj in register 12, the code of the averaged measurement result is formed. This result is represented by a direct code, if the sign of the result is positive, and an additional code, if the sign is negative. In order to present the final measurement result in the direct code, irrespective of the sign, the additional code is converted into direct, if the sign of the result is negative. For this, the sign of the measurement result is memorized in trigger 17 (Fig. 2 g) upon the transition of the recording pulse from output 18: block 15 of d. 2c. In Fig. 2g, the sign of the measurement result is negative.,

. In the time interval t. L at the output 14 of the block 15, a group of control signals is formed, corresponding to the operation of converting the additional code to the direct one. Under the influence of these signals, node 11 converts the additional code of the measurement result recorded in register 12 to direct. The resulting direct code is written to register 12. Thus, in register 12 is semi-. Direct measurement result code is given regardless of sign. After that, in the time interval, for example, 4-g 8 4-gb + 1o, the measurement result is divided by the number 2, for which the shift control input of the register 12 receives the shift control signal (figure 2) from the output 21 of the block 15. Simultaneously The input to the record of register 12 is a series of t pulses from the output 20 of block 15 (fig.2d which shifts the measurement result by .k bits to the left. Thus, in bits from 1 doP) + n-1 register 12

H minor bits) I get the direct binary code of the final averaged measurement result of the number of cycles and phase shift, and the output of the trigger 17 is the code of the sign of this measurement result. The measurement result code is fixed by a digital indicator 16 when a signal is received at the end input from the output of the 22 block, 15 (). The digital indicator 16 may contain input registers, a binary code converter; binary decimal and display device. . ; To eliminate the additive error of the bone due to channel identiality, and to enable measurement of phase shift increments in the proposed phase meter, the possibility of correcting the measurement result is provided, which is performed as follows: counter 6 and registers 9, J2 and 13 set-; c in the initial zero state. Then, the measurement of the initial phase shift "as described above, is performed, resulting in, on. the output of register 12 is generated code uHf. averaged measurement result Chd. This code, according to the signal from output 23 of block 15, is recorded in registers 13. The code dMd is subtracted in each step of the subsequent measurements, as described. but higher. Thus it is performed. correction of the additive error of the result of measuring the phase shift. .

, In phase fetepe it is possible to adjust the number of average measurement cycles, i.e. t number adjustment. To do this, block 15 may contain a switch for the number of averaged clock cycles, which changes the number of pulses that shift information in register 12,

Thus, the use of the invention will allow substantially. sow the phase measurement accuracy. shifts, both due to averaging the results of several measures of measurement, and due to the correction result of measurement. The proposed phase meter permits measurement of phase movements with high accuracy with the occurrence of asynchronous noise and noise in the input signals.

Claims (1)

DIGITAL PHASOMETER containing the first and second formers, a controlled generator, a unit for determining the number of cycles, a pulse counter, a reversible pulse counter, a first memory register and a delay line: and the first, the input of the phase meter through the first driver is connected to the input of the controlled generator, the first input of the determination unit the number of cycles and the zero-pulse input of the pulse counter, and the second input of the phase meter through the second driver is connected to the second input of the block for determining the number of cycles and through the delay line to the recording input high-order bits of the first memory register, the inputs of which are connected to the outputs of the pulse counter and the reversible pulse counter, the output of the controlled generator is connected to the input of the pulse counter and the third input of the unit for determining the number of cycles, the outputs of which are connected to the inputs of the reversible pulse counter, characterized in that ', that, in order to increase its accuracy, it is equipped with an arithmetic-logical unit, the second and third memory registers,. a digital indicator, a control unit, a sign trigger, an inverter and a zero-setting unit, and the outputs of the arithmetic-logical node through the second memory register are connected to the inputs of the third memory register, the digital indicator and the second inputs of the arithmetic-logical node, the first inputs of which are connected to the outputs of the same name the first and third memory registers, in addition, the senior bit of the first and third memory registers are connected in parallel with the senior bits of the first input of the arithmetic-logical node, the last bit in Each memory register is connected via a sign trigger to the inputs of the sign bits of the third memory register, digital indicator and the first input of the control unit, the second input of which is connected to the output of the controlled generator, the first outputs of the control unit are connected respectively to the control inputs of the arithmetic-logical unit , the second and third outputs, respectively, with the recording and shift inputs of the second memory register, the fourth, fifth and sixth outputs, respectively, with the recording inputs of the sign trigger, digital indicator and of the third memory register, the output of the second driver is connected directly to the control and write inputs to the lower bits of the first memory register, and to the control inputs of the third memory register through the inverter-, zero-setting inputs of the reverse pulse counter and the first, second and third registers memory connected to the output of the zero-block. SU „., 1128187 1 11281