JPS63104374A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To decrease current in a stand-by state, by using P channel transistors, which are always in off states, as load elements in stead of high resistance parts in a high resistance load type static RAM. CONSTITUTION:A high resistance load element PM1 and a driving N-channel transistor NM3 are connected in series to compose an inverter set. Also, a high resistance load element PM2 and a driving N channel transistor NM4 are connected in series to compose an inverter set. These inverters are connected in flip flop composition. The said load elements PM1 and PM2 are composed of P-channel transistors, which are always in off states, in stead of conventional high resistance parts. Besides, these transistors for load element formation are formed into a multilayered structure of P-type polycrystal silicon layers, so that high integration can be realized.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor memory device, and more specifically,
This invention relates to an improved structure of a static RAM in which a memory cell is constituted by a pair of inverters connected in series with a high resistance load element and an N-channel transistor.

[Conventional technology]

An equivalent circuit of a conventional static memory cell (high resistance load type memory cell) of this type is shown in FIG. 3, and a cross-sectional structure of the same memory cell is shown in FIG. 4.

That is, first, in the conventional example circuit shown in FIG.
H3 and NH3 are drive N-channel transistors that are connected in series to each of these high-resistance parts to form an inverter, and NH3 and NH3 are transmission transistors that connect these drive N-channel transistors and bit (data) lines. This is an N-channel transistor.

Further, in the conventional structure shown in FIG. 4, reference numeral 1 denotes a P-type well in a silicon semiconductor substrate, 2 denotes an N-type diffusion layer diffused into the P-type well, 3 denotes an insulating film for isolation between elements, 4 is a gate insulating film, and 5 is a polycrystalline silicon gate electrode.

6.8 is an interlayer insulating film, 15a and 15b are polycrystalline silicon wiring parts, 15b is a power supply line, and 1G is a part of this polycrystalline silicon wiring part made to have a high resistance value by diffusion of impurities, etc. High resistance part, 13 is aluminum wiring part (
(bit line), 14 is a passivation film covering these.

In the case of the conventional configuration, the inverter is connected in series with the high resistance section R1 and the driving N-channel transistor NM3, and the inverter is connected in series with the high resistance section R2 and the driving N-channel transistor NM4. By configuring this, it is possible to stably generate high and low potentials for nodes N1 and N2, which makes it possible to associate data 'o' and '1°° and retain and rewrite the same data. become.

In addition, by applying the high resistance parts R1 and R2 with extremely high resistance values as each load element in this way, any one of the driving N-channel transistors N in the on state can be
High resistance parts R1 and R2 connected in series with M3 and MN4
can reduce the current flowing to the In other words, the power consumption of the chip in the data retention state (standby state 8) can be suppressed to a minimum.

On the other hand, each load element has a depression type,
Although it is possible to apply N-channel transistors of the However, since each high resistance part can be formed together with each wiring part in the second polycrystalline silicon layer, it can be said that it is suitable for high integration. It is.

[Problem that the invention seeks to solve]

However, each high-resistance part in the high-resistance load type memory cell in the conventional configuration is formed by optimizing polycrystalline silicon to have a high resistance value, but there is a limit due to the high resistance value. However, as the frequency of memory devices becomes higher, the high resistance length is shortened, and as the number of memory cells increases, it becomes difficult to suppress the current during standby.

The present invention was made to improve such problems in the conventional device, and its purpose is to be suitable for high integration and to reduce the current during standby. An object of the present invention is to provide a semiconductor memory device of this type.

[Means for solving problems]

In order to achieve the above object, the semiconductor memory device according to the present invention includes, as a load element in a static memory cell,
A P-channel transistor that is always off is used, and this P-channel transistor is formed in a multilayer structure using P-type polycrystalline silicon layers.

[For production]

Therefore, in the case of the present invention, the potential during standby can be reduced by utilizing the leakage current of the P-channel transistor as a load element, and the P-channel transistor is connected to the P-type polycrystalline silicon layer. By forming a multilayer structure, high integration of the device can be achieved.

〔Example〕

Hereinafter, one embodiment of a semiconductor memory device according to the present invention will be described in detail with reference to FIGS. 1 and 2.

FIG. 1 is an equivalent circuit diagram of a static memory cell (high resistance load type memory cell) to which this embodiment is applied, and a second
The figure is a cross-sectional view showing the structure of the same memory cell as above, and in each figure of these embodiments, the same reference numerals as in the conventional example of FIGS. 3 and 4 indicate the same or similar parts.

In the case of this embodiment, instead of the high resistance parts R1 and R2 as load elements in the conventional circuit, P channel transistors PMI and P whose gates and sources are at the same potential are used.
H1 is provided, and the structure is as follows.

That is, as in the conventional example, an N-type diffusion layer 2 is selectively diffused into a P-type well 1 in a silicon semiconductor substrate, and the elements are separated by an insulating film 3, and a gate insulating film 4 is formed in each case. Through each polycrystalline silicon gate electrode J4
5 is formed and covered with interlayer insulation 1y2f3.

Next, a contact hole is formed in the interlayer insulating film 6, and the polycide film is deposited on the hill to be patterned to selectively form silicide wiring parts 7a and 7b. As you can see, one of the wiring parts 7b is , a part of which is used as a power supply line, and later becomes the gate electrode of a P-channel transistor as a high resistance load element.

Subsequently, an interlayer insulating film 1118 is deposited on these, and a hole is formed in the interlayer insulating film 8 at a portion that will become the gate electrode of the P-channel transistor, thereby forming the gate electrode 10.

Next, holes are selectively opened in areas where ohmic contact should be made with each of the silicide wiring parts 7a and 7b, and a second P-type polycrystalline silicon layer 9 is deposited, or after depositing non-doped polysilicon, Then, after selectively forming the channel region of the P-channel transistor into an N-type region 11, an interlayer insulating film 12 is deposited, and a contact hole is formed. Then, an aluminum interconnection layer 13 is selectively formed, and finally a bassy transition film 14 is formed, thus obtaining the desired P-channel transistors PMI and PH1.

In this embodiment, it is necessary to use a polycide film for the wiring portions 7a and 7b in order to prevent the formation of a PH10 junction. There is no problem since the P side is always at a high potential.

Therefore, in the case of the circuit device having the P-channel transistors PMI and PH1 as high resistance loads configured as described above, the connection from Vcc to node N1 or N
2, the P channel transistor PMI, P
Since only the leakage current of H1 is present, the current value in the data retention state in the memory cell can be reduced, and each P-channel transistor PMI, PH
1 and each of the N-channel transistors in the first layer are formed in a multilayer structure, so that the device itself can be highly integrated.

In the configuration of the above embodiment, a P-channel transistor which is always in an off state is used as a high-resistance load element in the memory cell, but a high-resistance section for potential fixing in the peripheral circuit 9, for example, Of course, the structure in which a P-channel transistor is formed of a P-type polysilicon layer can be used in other circuits.

〔Effect of the invention〕

As described in detail above, according to the present invention, a P-channel transistor which is always off is used as a load element in a static memory cell, and this P-channel transistor is formed into a multilayer structure using a P-type polycrystalline silicon layer. Since a part of the power supply line is also used as a gate electrode, the current characteristics in the standby state of the memory cell can be effectively improved, and the device configuration can be highly integrated. Moreover, the structure itself is relatively simple and has excellent features such as being easy to implement.

[Brief explanation of the drawing]

FIG. 1 is an equivalent circuit diagram showing a static memory cell to which an embodiment of the present invention is applied, FIG. 2 is a sectional view showing the structure of the same memory cell, and FIGS. 3 and 4 are conventional FIG. 2 is an equivalent circuit diagram and a sectional view according to an example. PMI, PH1...P channel transistor as a high resistance load element, NH3, NH3...N for driving
Channel transistor, NH3, NH3... N-channel transistor for transmission. 1...P type well, 2...N type diffusion layer, 3...
...Inter-element isolation insulating film, 4,10...Gate insulation■
5...Gate electrode, 8,8.12...Interlayer insulating film, 7a, 7b...Silicide wiring part, S...
...P-type polycrystalline silicon layer, 11...N-type region, 1
3... Aluminum wiring layer, 14... Passivation film. Agent: Masuo Oiwa Figure 1, Figure 2, Figure 3, Figure 4, Figure 1, Incident Indication: Tokugan Sho gl-25″θ//L1
．． 2. Name of the invention ¥ - Mimi 3 B. [Deke 3. Relationship with the person making the amendment Patent applicant address 2-2-3 Marunouchi, Chiyoda-ku, Tokyo Name (601) Mitsubishi Electric Co., Ltd. Representative Shiki
Moriya 4, Agent Address: Mitsubishi Electric Corporation, 2-2-3 Marunouchi, Chiyoda-ku, Tokyo Name (7375) Masuo Oiwa, Patent Attorney (Contact Number: 03 (213) 3421 Patent Department). 5. Subject of correction (1) Detailed description of the invention column in the specification (2) Drawing 6, contents of correction (1) Correct “gate electrode” on page 7, line 17 of the specification to “gate insulating film” . (2) Same [;Correct "polycide film" in lines 11-12 of page 8 to "silicide film". (3) Figures 2 and 4 of the drawings will be amended as shown in the attached sheet.
Upper figure 2

Claims (2)

[Claims] (1) A static semiconductor memory device consisting of a memory cell in which a set of inverters, each consisting of a high resistance load element and a driving N-channel transistor connected in series, is connected in a flip-flop configuration in a P-type well of an N-type semiconductor substrate. A semiconductor memory device characterized in that a P-channel transistor which is always in an off state is used as the load element. (2) P-channel transistor as a load element,
The semiconductor according to claim 1, characterized in that it is formed in a multilayer structure of P-type polycrystalline silicon layers, and a part of the power supply line in the memory cell is shared as the gate electrode of this P-channel transistor. Storage device.