JPH01202858A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To improve the degree of integration of a storage device by forming source-drain regions, a channel region and a gate electrode of an insulated gate type field-effect transistor in a second conductivity type by polysilicon films composed of two layers shaped to an upper section by an insulated gate type field-effect transistor in a first conductivity type. CONSTITUTION:Severally two of a first insulated gate type field-effect transistors and second insulated gate type field-effect transistors in a first conductivity type are formed to a substrate. Two of third insulated gate type field-effect transistors having a first conductive film as sources, drains and channel regions, a second conductive film as gate electrodes and a second insulating film as gate insulating films in second conductivity type are shaped onto at least one of the field-effect transistors through a first insulating film. It is preferable that the first and second conductive films consist of polycrystalline silicon (polysilicon) films. Accordingly, the degree of integration of a storage device is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and particularly to a semiconductor memory device suitable for a highly integrated, ultra-low power consumption static random access memory.

[Conventional technology]

A conventional complementary insulated gate field effect transistor (complete CMO8) type static random access memory cell has two n
Channel drive MoS transistor T1. T, and two p
Channel load MOS transistor T1. A flip-flop circuit formed by cross-connecting inverter circuits each consisting of T4, and an n-channel transfer M connected to two storage nodes N, N2 of this flip-flop circuit.
This flip-flop circuit is composed of OS transistors T, , T, and is supplied with a power supply voltage Vcc and a ground potential, and a data line 21, 21' is connected to the drain of the transfer MOS transistor. The common gate is the word line 20. As is well known, the operation of such a static random access memory cell is as follows: the word line is turned on, and the data line is set to ``High'' or ``Low'' via the transfer MO3) register.
This cell is used to store information in a storage node, or to read out the state of a storage node, and this cell functions as a static storage device. A static random access memory cell having such a CMOS circuit is characterized in that during standby, only the leakage current of the MoS transistor flows through the memory cell, resulting in extremely low power consumption.

Figure 25 shows a static random access memory cell as described above that has been improved in order to obtain a higher density memory. Day-32, number 2. (1985) pp. 258-281 (I E E E, T
RANS, Electron Devices.

vol, ED-32, Ha2, 1985.
As described in pp. 258-281), a p-channel load MOS transistor of a flip-flop circuit is formed on a polysilicon film on an n-channel drive MOS transistor. A plan view and a sectional view of this type of device are shown in FIGS. 25 and 26, respectively. That is, FIG. 26 is a cross-sectional view taken along the line AA' in FIG. Furthermore, a polysilicon film is provided on the top and side surfaces thereof, and a source 5c, a drain 5b, and a channel portion 5e of a p-channel load MoS transistor are formed in the polysilicon film. Furthermore, the above p.
The gate electrode of the channel load MOS transistor is common to the gate electrode 4b of the n-channel drive MoS transistor located directly below the channel portion 5e, and the channel portion 5e is formed on the gate electrode 4b, and is made of thin silicon oxide. Film 13 serves as a gate insulating film of a p-channel MOS transistor. Furthermore, to explain the conventional technology using FIG. 25, first, the drive MO of the flip-flop circuit is
The S transistor has an n-type impurity region 1e forming a common source and an n-type impurity region 1c forming a drain.
, ld and gate electrodes 4b and 4c.

Further, each gate electrode 4b, 4c has a connection hole 2b,
They are cross-connected to each other's drain side impurity regions through 2a. Furthermore, the n-type impurity region forming the drain of each drive MOS transistor is common to the source of the n-channel transfer MoS transistor connected to the flip-flop circuit, and forms the storage node of the flip-flop circuit. , the transfer MOS transistor has an n-type impurity region 1a forming the source impurity region, a common gate electrode 4a, and a drain.

1b. Further, the n-type impurity regions 1a and lb are connected to aluminum electrodes 8a and 8b via connection holes 7a and 7b. Note that the common gate electrode 4a constitutes a word line in the memory, and the aluminum electrodes 8a and 8b constitute data lines, respectively. In addition, regions are formed on the drains 5a, 5b of the p-channel load MOS transistors and the gate electrodes 4b, 4c of the drive MOS transistors, which are formed of a low-resistance polysilicon film doped with a high concentration of p-type impurities. Connection holes 7c and 7d are opened so as to be commonly exposed, and aluminum electrodes 8c and 8d connect the drain 5a and gate electrode 4b made of a polysilicon film, and the drain 5b and gate electrode 4c made of a polysilicon film, respectively. It is connected. Furthermore, the sources 5c of the p-channel load MOS transistors are made of a common low-resistance polysilicon film doped with p-type impurities at a high concentration, and the power supply voltage Vec is supplied to the sources of the two p-channel load MOS transistors. has been done. In addition, the above p-channel MO
Channel portions 5d and 5e of the S transistors are arranged on gate electrodes 4c and 4d of the drive M○S transistor, respectively.

[Problem to be solved by the invention]

In the above conventional technology, since the gate electrode of the n-channel drive MoS transistor formed in the silicon substrate and the gate electrode of the laminated P-channel load MOS transistor are shared, the p-channel load MOS
The channel portion of the transistor must be placed above the gate electrode of the driving MoS transistor. Therefore, there has been a problem in that the degree of freedom in laying out the memory cells is reduced, making it impossible to efficiently reduce the memory cell area.

Furthermore, in order to form a thin insulating film on the gate electrode of the drive MoS transistor, the material for the gate electrode may be limited. It is difficult to form a thin insulating film on the surface of these silicides, and there is also the problem that these low resistance materials cannot be practically used.

An object of the present invention is to provide a semiconductor memory device having a static random access memory cell with a high degree of freedom in design, high integration, and stable operation.

[Means to solve the problem]

The above object is to provide a semiconductor memory device having a static random access memory cell including a flip-flop circuit using complementary insulated gate field effect transistors, in which a first insulated gate field effect transistor of a first conductivity type is provided on a substrate. and a second insulated gate field effect transistor, and a source is placed over at least one of the field effect transistors via a first insulating film.

A third insulated gate field effect of a second conductivity type, which has a first conductive film serving as a drain and channel region, a second conductive film serving as a gate electrode, and a second insulating film serving as a gate insulating film. This is achieved by a semiconductor memory device characterized by forming two transistors.

The first insulated gate field effect transistor operates, for example, as a drive MOS transistor, the second insulated gate field effect transistor operates as a transfer MoS transistor, and the third insulated gate field effect transistor operates as a load MOS transistor. It is preferable to let

The first and second conductive films are preferably polycrystalline silicon (hereinafter referred to as polysilicon) films, and the first conductive film is a polysilicon film to which p-type impurities are added. It is preferable.

The first insulated gate field effect transistor is used for driving, and its gate electrode is electrically connected to at least a portion of the drain region of the first conductive film of the third insulated gate field effect transistor. It is preferable. Furthermore, it is preferable that the first conductive film is a polysilicon film doped with a second conductivity type impurity, and a channel region is formed between the source and drain regions. Preferably, one of the first and second conductive films is formed on the other, and the second insulating film is formed between them.

[Effect]

The third insulated gate field effect transistor made of the above-mentioned two-layer polysilicon film constitutes a load transistor in a flip-flop circuit of a static random access memory cell. 1. To form the source, drain, channel part, and gate of the transistor. Since the third insulated gate field effect transistor can be arranged regardless of the arrangement of the driving transistors formed on the silicon substrate, there is a large degree of freedom in design.

〔Example〕

Hereinafter, the present invention will be explained in more detail using Examples.

Embodiment 1 FIGS. 1A and 1B are plan views of a static random access memory cell according to the present invention.
FIG. 2 shows a cross-sectional structure taken along line AA' in the figure. FIG. 1(A) is a plan view showing the n-channel drive MOS transistor, transfer MOS transistor, word line, and data line, and FIG. 1(B) shows the p-channel load MOS transistor. . 1 and 2, the n-channel drive MoS transistor and the transfer MoS transistor are formed in a p-type well (p-type impurity island region) 10 formed in an n-type silicon substrate 9.
The respective gate electrodes 4a, 4d
, 4e are the first layer conductive films. Further, the gate electrodes 4d and 4e of the drive MoS transistor are connected to the connection hole 2.
They are cross-connected to n-type impurity regions 1c' and 1d, which are respective drains, via e and 2d. here,
The material of the gate electrode is polysilicon doped with a high concentration of n-type or p-type impurities, a high-melting point metal such as tungsten or molybdenum, a compound (silicide) of these high-melting point metals and silicon, or a combination of polysilicon and silicide. Any known gate material such as a composite film (polycide film) may be used. Further, the n-type impurity region 1e, which serves as a common source of the drive MOS transistors, is used as a ground potential wiring.

On the other hand, the p-channel load MOS transistor is formed on the silicon oxide film (SiO2 film) 13 on the drive MOS transistor. That is, the source and drain of the p-channel load MoS transistor are made of the SiO
, film 13 main 13th upper layer polysilicon film 16a , 1
6b and 16c, channel parts 16d and 16e of p-channel MOS transistors are formed in the polysilicon film of the same layer, and a thin insulating film 19
is the gate insulating film of the p-channel MoS transistor, and the gate electrode is the third layer polysilicon film 18a, 18.
It is formed by b. For more details, see Figure 1 (A
), (B), the n-type impurity region 1c' which becomes the drain of the drive MOS transistor which is one storage node of the flip-flop circuit becomes the source of the transfer MOS transistor by the gate electrode 4d via the connection holes 2c and 2e. A connection hole 15a is formed in the insulating film 13 connected to the n-type impurity region 1c and on the gate electrode 4d connected to the n-type impurity region 1c or the n-type impurity region 1c. A polysilicon film 16a, which is a second conductive film, is connected. Similarly, the n-type impurity region 1d that becomes the drain of the drive MOS transistor, which is the other storage node of the flip-flop circuit, is a common impurity region with the source impurity region of the transfer MOS transistor, and is connected to the impurity region on or connected to the impurity region. A connection hole 15b is formed in the silicon oxide film 13 on the gate electrode 4e.
A hole is opened, and the second layer polysilicon 16b is connected. The second layer of polysilicon 16c, which is the common source of the p-channel MOS transistors, is also used as a wiring layer for the power supply voltage Vcc in the memory, and is used as a wiring layer for the two load p-channel MOS transistors in each memory cell.
A power supply voltage is supplied to the source of the S transistor.

Note that the source of the p-channel MoS transistor.

The drain region is formed in a self-aligned manner with respect to third layer polysilicon films 18a and 18b, which are gate electrodes, and the channel length is determined by the width of this gate electrode. Further, the third layer polysilicon films 18a and 18b forming these gate electrodes are connected to the n-type impurity region 1d, which is the drain of the n-channel drive MOS transistor, which is the storage node, through the connection holes 17a, 17b. lc'. Furthermore, the third layer polysilicon film 18
A and 18b are doped with p-type or n-type impurities at a high concentration to reduce the resistance, but the material of this layer does not have to be polysilicon, and can be made of tungsten like the gate material of the drive MOS transistor described above. Known gate materials such as high melting point metals such as and molybdenum, compounds of these high melting point metals and silicon (silicide), composite films of polysilicon and silicide (polycide film), and titanium nitride films (TiN) with low interdiffusion of impurities. Composite membranes using can be used.

Further, two data lines in the static memory cell are formed by connecting aluminum electrodes 8a, 8b to n-type impurity regions 1a, lb, which are the drains of the transfer MOS transistors, via connection holes 7a, 7b. In addition, in the structure of the static random access memory cell having the p-channel load MOS transistor described above, as is well known, a high concentration PN junction D1 with a large leakage current as shown in the equivalent circuit of FIG. ．． 'D is formed.

Next, the manufacturing process of this example will be explained using FIG. 4. Figures (A) to (F) are cross-sectional views at each manufacturing process of the static MOS memory cell according to this embodiment.
, represents a cross section taken along line AA' in FIG. In this embodiment, all MOS transistors formed in the silicon substrate used in the memory cell are located in the p-type well 10.
It is a channel MOS transistor, and a complementary MO8 (0MO8) circuit using a double well is used for the memory peripheral circuit, but a single well structure of a p-type well or an n-type well may be used. Furthermore, the conductivity type of the silicon substrate may be n-type or p-type. In addition, in this embodiment, only the manufacturing process of the memory cell part will be described, but the peripheral C-M
Known techniques can be used to manufacture the O8 circuit.

First, an impurity concentration of 10 Ω was implanted into an n-type silicon substrate 9 with a specific resistance of about 10 Ω by boron ion implantation and thermal diffusion.
After forming a p-type well 10 with a thickness of 1s to 1017an-'' and a depth of 1 to 10IIm, a p-type channel stopper layer 22 and a thickness of 100 to 110mm for element isolation are formed by selective oxidation.
A silicon oxide film (field oxide film) 11 with a thickness of 00 nm is formed, and then a silicon oxide film 12, which is a gate oxide film, with a thickness of 10 nm to 1100 nm is formed in the part that will become the active region of the MOS transistor [Fig. )]. Next, a connection hole 2d is opened in a part of the gate oxide film by wet etching using a hydrofluoric acid solution, and after polysilicon is deposited by low pressure vapor phase chemical growth (LPCVD), an n-type film such as phosphorus is deposited. Impurities are introduced by vapor phase diffusion, and gate electrode 4a is formed by photolithography and dry etching.

These gate electrodes 4a are processed into a pattern of 4e.

1oi4~1 using 4e as a mask for ion implantation
Ion implantation of n-type impurity ions such as arsenic is performed with an implantation amount of 0"aa-", and a predetermined annealing process is performed to a depth of 0.0.
N-type impurity regions 1b, ld, and le of 5 to 0.3- are formed [FIG. 4(B)]. Next, the silicon oxide film 13 is LP
5 (deposited to a thickness of 1 to 11000 nm by CVD method,
A contact hole 15b is opened, and then a second layer polysilicon film 16 is deposited to a thickness of 10 to 500 nm by LPCVD, and patterned by photolithography and dry etching [FIG. 4(C)].

Next, an insulating film 19 such as a 5 in 2 film with a thickness of 5 to 50 nm is deposited by the LPCVD method, and after being densified by predetermined annealing, a contact hole 17a is opened on the n-type impurity region ld, and then, A third layer of polysilicon films 18a and 18b is deposited to a thickness of 10 to SOO nm by the LPCVD method, and a p-layer is deposited by photolithography and dry etching.
The gate electrode pattern of the channel MOS transistor is processed (FIG. 4(D)), and p-type impurities such as boron are implanted using the third layer polysilicon films 18a and 18b as masks for ion implantation. 10~
50Kev, implantation amount I XIO”~I XIO”Ql
The source/drain regions of the stacked p-channel MOS transistors are formed in a self-aligned manner by doping by ion implantation and predetermined annealing.At this time, at the same time, the third layer of polysilicon is added. Membrane 18a, 1
A p-type impurity is also introduced into 8b to lower the resistance. Note that when the implantation energy of the boron ions 23 is high, the photoresist used to process the third layer polysilicon films 18a and 18b may be used as a mask for ion implantation to prevent boron from leaking into the channel portion. In this case, it is necessary to introduce impurities into the third layer polysilicon film in advance to lower the resistance. Furthermore, the third
If n-type impurities are added to the polysilicon film at a high concentration in advance, the conductivity type of the gate electrode can be changed even if the source and drain regions of the P-channel MoS transistor are formed in a self-aligned manner as described above. can be made n-type [4th
Figure (E)]. Next, a silicon oxide film 14 containing, for example, phosphorus with a thickness of 100 to 11,000 nm is deposited by the CVD method to reduce the level difference in the memory cell, a connection hole 7b is opened by photolithography and dry etching, and an aluminum film is deposited by sputtering. Deposited to a thickness of 0.1-2-
The aluminum electrode 8b is patterned by photolithography and dry etching [FIG. 4(F)].

Furthermore, as shown in the plan view of the p-channel MOS transistor section in FIG. 5, by using the third layer polysilicon film 18c also for the divided word lines, the parasitic capacitance of the word lines can be reduced and the memory Operation speed can be increased.

Embodiment 2 This embodiment relates to a static random access memory cell according to Embodiment 1, in which power supply voltage wiring is made independent for supplying power to the sources of two p-channel load MoS transistors in the memory cell. Figure 6 (
A) and (B) are diagrams showing plan views of the static random access memory cell according to the present embodiment;
) shows a portion of a drive MOS transistor and a transfer MOS transistor, and (B) shows a portion of a stacked p-channel load MOS transistor. Also, the seventh
The figure is a diagram showing a cross-sectional structure taken along the line AA' in FIG. 6. 6 and 7, the second layer polysilicon films 16b and 16f are the drain region of the p-channel load MOS transistor, and the second layer polysilicon film is the channel region 1 of the p-channel MOS transistor.
6d, 16e.

The second layer polysilicon films 16c and 16g are the source regions of the P-channel MOS transistors, and these polysilicon films 16c and 16g are independent wiring lines for supplying power supply voltage Vcc. In addition, the second layer polysilicon 16b and 16f have connection holes 15b,
n-type impurity regions 1d and lc of the storage node via 15c.
Alternatively, a third gate electrode is connected to the gate electrodes 4d and 4e connected to the n-type impurity regions 1d and lc, and further forms the gate electrode of the p-channel load MoS transistor.
The polysilicon films 18a and 18b of the second layer have connection holes 24a,
24b, the second layer polysilicon film 16b, 1
Connected to 6f.

According to this embodiment, the power supply wiring for the power supply voltage Vcc to the two p-channel load M○S transistors does not use a common wiring as in the first embodiment, so that the arrangement of the p-channel MoS transistors in the memory cell is The degree of freedom is increased, efficient arrangement is possible, and the memory cell area can be further reduced. Furthermore, the third polysilicon film is never directly connected to an n-type impurity region where a thick interlayer insulating film is deposited, and is always connected to the second polysilicon film through a thin insulating film.
Since it is connected to the polysilicon layer, microfabrication such as photolithography and dry etching becomes easy, and manufacturing yield can be improved.

Embodiment 3 This embodiment is a stacked p-channel M in a static random access memory cell in Embodiment 1.
The present invention relates to a flip-flop circuit of an OS transistor in which a fourth layer of conductive film is used in the cross-connection portion of gate electrodes. FIG. 8 is a plan view showing the layered p-channel MoS transistors of the static memory cell according to this embodiment, and the n-channel drive MOS transistors and transfer MOS transistors formed in the silicon substrate are shown in FIG. This is the same as Figure 1 (A). Furthermore, Figure 9 shows the 8th
It is a figure which shows the cross-sectional structure of the AA' line in the top view of a figure. In FIGS. 8 and 9, second-layer polysilicon films 16a and 16b are drain regions of p-channel MOS transistors, and are connected to underlying storage nodes via connection holes 15a and 15b. On the other hand, the second layer polysilicon 16c is the common source of the p-channel MOS transistor, and the third layer polysilicon film 18a, which becomes the gate electrode, is provided above the channel parts 16d and 16e of the p-channel MOS transistor. 18b is formed. Further, connection holes 25a are formed in the insulating films 19 and 19' on the second and third layer polysilicon films.
, 25b, 25c are opened, and the fourth layer polysilicon film 26a is doped with p-type impurities at a high concentration.
, 26b cross-connect the second and third layer polysilicon films. As shown in the plan view of the p-channel MOS transistor in FIG. 10, a fourth layer of polysilicon film 26c is formed and used for the divided word lines as described in Example 1, thereby achieving high-speed memory operation. can be done.

In this case, the fourth layer polysilicon film may be any other conductive film with low resistivity, such as a high melting point metal such as tungsten, its compound with silicon (silicide), or a composite film of silicide and polysilicon. can be mentioned.

According to this embodiment, the stacked p-channel load MOS
Since the gate electrode of the transistor does not need to be directly connected to the gate electrode or drain region of the drive MOS transistor, the degree of freedom in arranging the gate electrode of the p-channel MOS transistor is increased, and the memory cell area can be further reduced.

Embodiment 4 This embodiment is a static random access memory cell according to Embodiment 1, and the operating characteristics of the memory cell are improved by reducing the wiring resistance of the ground potential of the memory cell. FIG. 11 shows the drive MOS transistor, transfer MOS transistor, and ground wiring of the static memory cell according to this embodiment. Note that the structure of the stacked p-channel load MoS transistor is the same as that of other embodiments, so a description thereof will be omitted here.

In FIG. 11, a part of the interlayer insulating film is removed to form connection holes 2f and 2g on the n-type impurity regions 1f and 1g that form the sources of the two drive MOS transistors. The regions if and Ig are connected to the first layer polysilicon film 4f and fixed to the ground potential.

Further, the first layer polysilicon film 4f serves as a wiring for supplying a ground potential to all cells in the memory.

Note that this first layer polysilicon film 4f is a drive MOS
It is the same layer as the gate electrode of the transistor or transfer MOS transistor, and a low-resistance gate material as described in the first embodiment can also be used. Note that the present invention relates to a ground wiring method and can be similarly applied to the second embodiment and the third embodiment.

According to this embodiment, the resistance value of the ground wiring to the memory cell can be lowered, so even if the memory speed is increased, the operation can be stabilized, and a semiconductor memory device with high speed and less malfunction can be provided. can do.

Embodiment 5 This embodiment relates to the static random access memory cell according to Embodiment 1, in which ground potential wiring is performed using a conductive film formed above the main surface of a silicon substrate. FIG. 12 shows a plan view of the static memory cell according to this embodiment, and FIG. 13 shows a cross-sectional structure taken along line AA' in FIG. 12. In FIGS. 12 and 13, the n-type impurity region lf, which is the source of the two driving MOS transistors, the Sin on 1g, the impurity region if,
Ig is connected to a second layer polysilicon film 28, and furthermore, this second layer polysilicon film 28 serves as a ground wiring and applies a ground potential to each memory cell in the memory. Further, the third layer polysilicon films 30a, 30
b is the drain region of the stacked p-channel load MOS transistor, and the third layer polysilicon film 3
0c is a common source and is a channel portion 30d of the p-channel MoS transistor.

On 30e, a fourth layer of polysilicon 32a and 32b is formed with a thin insulating film 19 interposed therebetween, which will serve as the gate electrode of the p-channel load transistor. It should be noted that this embodiment relates to a ground wiring method, and thus can be applied to the second and third embodiments as well as the fourth embodiment. The second layer of polysilicon described in this example is made of a high melting point metal such as tungsten, a compound of these high melting point metals and silicon (silicide), or a composite film of silicide and polysilicon (polycide). A conductive film with low resistance may be used.

According to this embodiment, the resistance value of the ground wiring to the memory cell can be lowered, stable operation is possible even when the memory speed is increased, and the memory cell area can be reduced. It is possible to provide a semiconductor memory device that is optimal for integration, has high speed, and has few malfunctions.

Embodiment 6 This embodiment is a static random access memory cell in Embodiment 1, and a stacked p-channel load MO.
This relates to an S transistor in which the channel region is formed above the gate electrode. 14th! is a cross-sectional view of the static memory according to this embodiment, and the third layer polysilicon films 34b and 34c are the source and drain regions of the stacked p-channel MOS transistor, and the p
There is a channel region of a channel MOS transistor. Note that the source, drain, and channel regions described above are formed by ion implantation of boron atoms using, for example, photoresist as a mask for ion implantation. Also, the third
The polysilicon film 34b of the third layer is connected to the drive MO through the connection hole.
It is connected to the gate electrode 4e of the S transistor and constitutes a storage node portion of the flip-flop. Also,
A power supply voltage Vcc is applied to the third layer polysilicon film 34c, and furthermore, this polysilicon film 34c serves as a wiring for the power supply voltage Vec within the memory. Further, the second layer polysilicon film 33b is the p-channel MoS
The second layer polysilicon film 33a is the gate electrode of the transistor, and the second layer polysilicon film 33a is the other p of the flip-flop circuit.
is the gate electrode of the channel load MoS transistor,
It is cross-connected to n-type impurity region 1d, which is a storage node, via a connection hole.

Note that this example is Example 2. Example 3. Embodiment 4 This can be similarly applied to Embodiment 5.

Furthermore, it is generally better for the third layer polysilicon film to be thinner than the second layer polysilicon film. This makes it possible to shorten the over-etching time to prevent dry etching residue when patterning the third layer of polysilicon, and it is possible to shorten the over-etching time to prevent dry etching residue when patterning the third layer of polysilicon.
This is to prevent the film 19 from disappearing due to over-etching, but according to this embodiment, the channel region can be formed in the thin third layer polysilicon film, and the p It is possible to reduce the leakage current and threshold voltage of the channel MOS transistor,
A semiconductor memory device with low power consumption can be provided.

Embodiment 7 This embodiment is a static random access memory cell according to Embodiment 1, in which a conductive film with low interdiffusion of impurities is laid on the first conductive film constituting the gate electrode of the drive MOS transistor. related to things. FIG. 15 is a diagram showing cross-sectional manufacturing of the static memory cell in this example.

In the same figure, a drive MOS transistor and a transfer MO
The gate electrodes 4a and 4e of the S transistor are the first layer of polysilicon film, and a titanium nitride film (
A conductive film 35 with little interdiffusion of impurities, such as a TiN film), is formed, and is connected to the second layer polysilicon film 16b, which is the drain region of the n-channel MOS transistor, via a connection hole.

According to this embodiment, the first layer of n-type polysilicon and the second layer of n-type polysilicon
Since a barrier conductive film 35 with little interdiffusion of impurities is interposed between the N-th p-type polysilicon layers, a barrier conductive film 35 with little interdiffusion of impurities exists at the connection portion between the n-channel MOS transistors of the flip-flop circuit, as shown in FIG. Since such a PN junction is not formed, the operation of the memory becomes stable and high-speed operation is possible.

Embodiment 8 The present invention is a static random access memory cell according to Embodiment 7, in which a conductive film for preventing mutual diffusion of impurities is formed only in the connection hole. FIG. 16 is a cross-sectional view of the static memory cell according to this embodiment,
S io on the gate electrode 4e of the drive MoS transistor
, a contact hole is formed in the film 13, and a barrier conductive film 36 such as a titanium nitride film (TiN film) with low mutual diffusion of impurities is embedded in the contact hole, and the second layer p-type polyester film 36 is buried in the contact hole. A silicon film 16b is connected. Regarding the method of embedding the electrically sensitive film 36 in the connection hole, for example, after depositing the conductive film 36 on the entire surface, the conductive film 36 is removed from the portion other than the connection hole by isotropic dry etching.

According to this embodiment, as in the seventh embodiment, the n-channel MOS transistor and the n-channel MOS of the flip 70 tube circuit are
Since P and N junctions are not formed at the connection part of the transistor, the operation of the memory becomes stable and high-speed operation is possible, and since the conductive film 36 exists only in the connection hole part, there are no restrictions on the material of the gate electrode. The surface of the connection hole can be flattened without causing any damage, and the manufacturing yield can be increased.

Note that in this embodiment, as shown in the cross-sectional view of FIG.
It can be applied in exactly the same way even when connected to d.

Embodiment 9 This embodiment is a static random access memory cell according to Embodiment 1, in which a connection hole is formed at the connection portion between the gate electrode of the stacked P-channel MOS transistor and the n-type impurity region which is the drain region of the drive MOS transistor. A barrier conductive film with low interdiffusion of impurities is embedded inside. FIG. 18 is a diagram showing the cross-sectional structure of the static memory cell according to this embodiment, and the third layer polysilicon film 18a, which becomes the gate electrode of the stacked n-channel MOS transistor, is used as the gate electrode of the n-channel drive MOS transistor. The connection is made through a barrier conductive film 36, such as a titanium nitride film (TiN film), which is buried in a contact hole on the n-type impurity region 1d, which is the drain, and has little interdiffusion of impurities.

Note that the manufacturing process is simplified by reducing the resistance of the gate electrode of a stacked n-channel MOS transistor at the same time as forming the source and drain regions, but in this case, the conductivity type of the gate electrode becomes p-type. A PN junction, D4, as shown in FIG. 19, is formed at the connection between the gate electrode and the n-type impurity region of the storage node. Therefore, according to this embodiment, the above-mentioned PN junction D3. D4 is not formed, and the gate potential of the n-channel MOS transistor is not lowered due to the built-in potential of the PN junction, making it possible to stabilize the memory operation.

Embodiment 10 This embodiment is a static random access memory cell in Embodiment 1, and includes a stacked p-channel load MO.
This relates to the material of the gate insulating film of the S transistor. That is, in this embodiment, the gate insulating film 19 of the n-channel MOS transistor in FIG.
Alternatively, an insulating film with a high dielectric constant such as a tantalum oxide film (Ta, os) is used.

According to this embodiment, it is possible to increase the gate capacitance of the p-channel MoS transistor, thereby increasing the driving capability of the p-channel MOS transistor, and stabilizing the static memory operation. Note that this embodiment can be applied to the gate insulating film 19 of all embodiments described in the present invention.

Embodiment 11 This embodiment is a static random access memory cell in Embodiment 1, in which the third layer of polysilicon film, in which the gate electrode of the stacked p-channel MOS transistor is formed, is connected to the self-aligned connection of the data line. This is what was used in the section. FIG. 20 and FIG. 21 show a plan view and a cross-sectional view, respectively, of the static memory cell according to this embodiment.

Figure 20 (A), like Figure 1 (A), shows the drive MOS transistor and transfer MoS transistor, and Figure 20 (B) shows the self-aligned connection between the stacked p-channel MoS transistor and the data line. The 21st
The figure is a diagram showing a cross-sectional structure taken along the line AA' in FIG. 20.

In FIGS. 20 and 21, connection holes 37 are formed on the drain impurity regions 1a and lb of the transfer MOS transistors.
Holes a and 37b are opened, and third layer polysilicon films 18c and 18d doped with n-type impurities are connected.

Note that in the connection holes 37a and 37b, the gate electrode 4a.

Since the silicon oxide film 38 is formed on the surface of 4a', the gate electrode surface is not exposed due to the formation of connection holes 37a and 37b. In addition, the gate electrode 4a
, the side wall of 4a' is also an insulating film side wall spacer 3.
It is electrically insulated by 9.

Therefore, the connection holes 37a and 37b are connected to the gate electrode 4a.

Even if these gate electrodes are located on 4a', there will be no short circuit between these gate electrodes and the third layer polysilicon films 18c and 18d. On the other hand, the polysilicon film 18C218d extends to the top of the gate electrodes 4a, 4a',
The aluminum electrodes 8a, 8b are connected to the third layer polysilicon films 18c, 18d on the gate electrodes 4a, 4a', respectively, via connection holes 7a, 7b.

According to this embodiment, the connection holes 7a and 7b of the aluminum electrodes 8a and 8b forming the data line and the gate electrode 4a
, 4a', it is not necessary to secure a layout margin, and the area of the memory cell can be reduced. Note that this embodiment can be similarly applied to each of the embodiments from embodiment 2 to embodiment 11.

Embodiment 12 This embodiment is an example of the second layer polysilicon film in which the source/drain regions and channel regions of the stacked p-channel MoS transistor in the static random access memory cell in Embodiment 1 are formed. This is used for a self-aligned connection of data lines similar to No. 11. FIG. 22 is a diagram showing a cross-sectional structure of a static memory cell according to this example. In the figure, the second layer polysilicon film 16i doped with n-type impurities is exactly the same as the third layer polysilicon film 16i of the self-aligned connection part of Example 11, and is used as the drain diffusion layer of the transfer MoS transistor. Furthermore, this second R-th polysilicon film 16i extends above the gate electrodes 4a, 4a' of the transfer MOS transistors, and a connection hole 7b is opened to form the above-mentioned n-type impurity region 1b. An aluminum electrode 8b is connected to the second layer polysilicon film 16i.

According to this embodiment, as in the eleventh embodiment, there is no need to ensure a layout margin between the connection hole 7b of the aluminum electrode 8b forming the data line and the gate electrode 4a, and the area of the memory cell can be reduced. Can be done. Note that this embodiment can be similarly applied to each of the embodiments from embodiment 2 to embodiment 10.

Embodiment 13 This embodiment is a static random access memory cell according to Embodiment 1, in which the data line is formed using a second layer of aluminum electrode. FIG. 23 is a diagram showing a cross-sectional structure of a static random access memory cell according to this embodiment. In the figure, a first layer aluminum electrode 40b is connected to the n-type impurity region 1b of the transfer MoS transistor via a connection hole 7b. Furthermore, the second layer aluminum electrode 42b constituting the data line is formed between the flattened layers, on the I@l edge film 41, and is connected to the first layer through the connection hole 43b. It is connected to the aluminum electrode 40b.

According to this embodiment, it is possible to increase the thickness of the insulating film between the second layer aluminum electrode forming the data line and the other conductive film in the lower layer, so that the insulating film in the memory cell can be thickened. The capacitance component parasitically occurring in the data line is reduced, making it possible to speed up memory write and read operations.

Embodiment 14 This embodiment is a static random access memory cell according to Embodiment 1, and relates to a method of cross-connecting gate electrodes of a flip-flop circuit of stacked P-channel MOS transistors. FIGS. 27(A) and 27(B) are plan views of the static memory cell according to this embodiment, and FIGS.
A) shows the drive MOS transistor, transfer MOS transistor, word line and data line;
) indicates a portion of a stacked p-channel MoS transistor. Further, FIG. 28 is a diagram showing a cross-sectional structure taken along line AA' of the plan view shown in FIG. 27. 27th
In the figure and FIG. 28, second layer polysilicon films 16a and 16b are drain regions of a p-channel MOS transistor, and contact holes 15a.

It is connected to n-type impurity regions 1c and ld forming the lower layer storage node via 15b. In addition, the third layer polysilicon films 18a and 18b provide p-channel MO
A gate electrode of an S transistor is formed. Further, the second and third layer polysilicon films 16a
, 16b, 18a, and 18b, connection holes 7e, 7f, 7g, and 7h are formed in the insulating film 19, etc., and
In particular, the connection holes 7gt and 7h are the second layer of polysilicon 16.
The first layer of aluminum electrode 40 is placed on c.
d and 40c, the second layer polysilicon film 16a
and the third layer polysilicon film 18b, the second layer polysilicon film 16b, and the third layer polysilicon film 18a.
are each cross-connected. Further, the data line of the memory cell is formed using a second layer of aluminum electrode as in the thirteenth embodiment.

According to this embodiment, since the gate electrode of the stacked p-channel MOS transistor does not need to be directly connected to the drain region of the driving MoS transistor, the degree of freedom in arranging the gate electrode of the p-channel MOS transistor is increased. The memory cell area can be further reduced.

Furthermore, in the cross-connection section, the gate electrode of one p-channel MOS transistor is connected to the drain region of the other p-channel MOS transistor through an aluminum electrode, so the conductivity type of the gate electrode of the p-channel MOS transistor is It may be n-type or p-type, and it is possible to improve the characteristics of the p-channel MoS transistor. Furthermore, since the second layer of aluminum electrodes are used for the data lines, the writing and reading operations of the memory can be made faster.

Embodiment 15 This embodiment is a static random access memory cell in Embodiment 1, in which the conductivity type of the silicon substrate on which the memory cell is formed is p-type. FIG. 29 is a diagram showing a cross-sectional structure of a static random access memory cell according to this embodiment. In the figure, the structures of the n-channel drive MOS transistor, the transfer MOS transistor, and the laminated p-channel load MOS transistor are exactly the same as in the first embodiment. - way,
The memory cell is formed in a p-type silicon substrate 44, and is formed in an n-type impurity region 1b of an n-channel MoS transistor.
, ld, and le, a p-type impurity region 45 having a higher concentration than the substrate is formed. Furthermore, p of the peripheral circuit
The channel MOS transistor is formed in an N-type well as seen in a known dynamic random access memory.

According to this embodiment, productivity can be improved because a versatile P-type silicon substrate is used, which is the same as silicon substrates used in other semiconductor memory devices, logic circuit devices, and the like.

Furthermore, since the p-type impurity region formed inside the p-type silicon substrate has a barrier effect against carriers generated by irradiation with α rays, soft errors in the memory device can be prevented.

Example 16 This example, like Example 15, concerns the conductivity type and well structure of a silicon substrate. FIG. 30 is a diagram showing the cross-sectional structure of the static random access memory cell according to this embodiment, and the structures of the n-channel drive MoS transistor, transfer MOS transistor, and stacked p-channel load MOS transistor are as follows. It is exactly the same. On the other hand, the memory cell is formed in a p-type well 10 that is formed in an n-type well 46 formed in a p-type silicon substrate 44, as shown in the figure. Furthermore, the n-channel MOS transistor of the peripheral circuit of the memory is formed in a p-type well similar to the memory cell, and the p-channel MOS transistor is formed in an n-type well shallower than the n-type well 46 of the memory cell. ing.

According to this embodiment, productivity can be improved because a p-type silicon substrate, which has the same versatility as silicon substrates used in other semiconductor memory devices, logic circuit devices, etc., is used. Furthermore, since a p-type well is formed within an n-type well, and peripheral circuits and memory cells are formed within each p-type well, each n-type well is fixed at a predetermined potential. , it is possible to prevent malfunction of the device due to external noise mixed into the input terminal.

〔Effect of the invention〕

According to the present invention, in a fully CMO8 type static random access memory cell having stacked insulated gate field effect transistors, the source, drain region, channel region and Since the gate electrode is formed of two layers of polysilicon film formed above the first conductivity type insulated gate field effect transistor formed on the silicon substrate, the second conductivity type transistor is used as a memory cell. ii in the optimal position within! can be placed,
This increases the degree of freedom in design and has a small cell area, making it ideal for highly integrated memory devices.

[Brief explanation of the drawing]

1, 5, 6, 8, 10, 11, 12, 20, and 27 are plan views of one embodiment of the present invention; Figures 4, 7, and 9. Fig. 13, Fig. 14, Fig. 15, Fig. 16, Fig. 17,
Fig. 18, Fig. 21, Fig. 22, Fig. 23, Fig. 28,
Figure 29. FIG. 30 is a sectional view of one embodiment of the present invention, FIG.
24 is an equivalent circuit diagram of an embodiment of the present invention, FIG. 24 is an equivalent circuit diagram of a conventional technique, FIG. 25 is a plan view of a conventional technique, and FIG. 26 is an equivalent circuit diagram of an embodiment of the present invention.
The figure is a sectional view of the prior art. la, lb, lc, lc' ld, le,
if, Ig...N-type impurity region 2a, 2b, 2c, 2d, 2e, 2f, 2
g, 7at7b, 7c, 7d, 7e, 7f,
7g, 7h, 15a. 15b, 15c, 17a, 17b, 24a,
24b, 25a, 25b. 25c, 27a, 27b, 29a, 29b,
31a, 31b, 37a. 37b, 43a, 43b=----Connection hole 4a, 4
a' 4b, 4c, 4d, 4e - gate electrode 4f...
...First layer polysilicon film 5a, 5b...
...Drain 5c...Source 5d, 5e...Channel portion 8a, 8b, 8c, 8d...Aluminum electrode 9...N-type silicon substrate 10. ...P-type well 11, 12.13.13' 14.38...Silicon oxide film (Sin, film) 16, 16a, 16b
, 16c, 16f, 16g, 16i...
...Second layer polysilicon film 16d, 16e
, 30d, 30e, 34e...Channel portions 18a, 18b, 18c, 18d... of p-channel MOS transistors
...Third layer polysilicon film 19, 19'...
- Insulating film 20... Word lines 21, 21'... Data line 22... Channel stopper layer 23... Boron ions 26a, 26b, 26c... ...Fourth layer polysilicon film 28...
・Second layer polysilicon film 30a, 30b,
30c...Third layer polysilicon film 32a, 32b
...Fourth layer polysilicon film 33a, 33b
...Second layer polysilicon films 34b, 34c
...Third layer polysilicon film 35, 36...
... Conductive film 39 ... Side wall spacer 40a,
40b, 40c, 40d...First layer aluminum electrode 41...Interlayer insulating films 42a, 42b...Second layer aluminum electrode 44...・P-type silicon substrate 45...p-type impurity region 46...N-type well T□, T2...n-channel drive MOS transistor T
,,T,... p-channel load MOS transistor T,
, T, . . . n-channel transfer MoS transistor D1.
D2. D,,D4...PN joint agent patent attorney
Junnosuke Nakamura Figure 1 (A) Figure 1 CB) Figure 3 t-e: Genit Densai 31: nllnno] 4th clause - P type tsu: 翿: 2ru - Teshin V''44 Rusttsu/Botaku d , ρ: n pull military force 1: special hole 23: boron inan 8b; aluminum wire At& Fig. 4 (E) Fig. 4 (F) Fig. 5 Fig. 6 (A) Fig. 6 (B) 16f: Calculation 2nd layer E)!/l Con 8 East f: Arithmetic 1 Mayami's r Silicon 1 9: N-type positive deposit A Figure 11 Figure 14] b Evil 36: Conductive wire Figure 17 19 Figure 16112/! [Tri A
;ζriT3. T4: P+N kill rental MO5) Funshi "Staff 576 z n+e"'FA/坤z 桥ふJ
qK) Koto")n"; 75 Fig. 24 4a'; Gate snow removal 40a-d: 'November - eyes 7) Remi: Tsu At&
Figure 27 (A) Figure 27 CB) 1a-e
: n type book 8 product relation 4a~C: Woot electric A4 color 5a, b: drain 5c: source 10: P! Hi 1. Well 11.12, 1'3.14: Silicon layer 1 [film 44:
I￥ Shikukon 11 Shikoku 45:P”!Rice squeeze 4 balls 28th figure 44: P-type silicon kudzu 4 more 46: N-type well 10:P “”! Well 30th figure

Claims (1)

[Claims] 1. In a semiconductor memory device having a static random access memory cell including a flip-flop circuit using complementary insulated gate field effect transistors, a first insulated gate of a first conductivity type is provided on a substrate. type field effect transistor and a second insulated gate type field effect transistor, and form a source, drain, and channel region over at least one of the field effect transistors with a first insulating film interposed therebetween. Two third insulated gate field effect transistors of the second conductivity type are formed, each having a first conductive film, a second conductive film serving as a gate electrode, and a second insulating film serving as a gate insulating film. A semiconductor memory device characterized by: 2. The first conductive film is located below the second conductive film, and the second insulating film is disposed between the first and second conductive films. The semiconductor memory device according to item 1. 3. The first conductive film is located above the second conductive film, and the second insulating film is disposed between the first and second conductive films. The semiconductor memory device according to item 1. 4. The first insulated gate field effect transistor is a driving transistor, and its gate electrode is electrically connected to at least a portion of the drain region of the first conductive film of the third insulated gate field effect transistor. 2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is connected as follows. 5. The gate electrode of the third insulated gate field effect transistor is cross-connected to the drain region of the first insulated gate field effect transistor via a third conductive film. The semiconductor memory device according to item 1. 6. The semiconductor memory device according to claim 1, wherein the static random access memory cell has at least two power supply voltage feed lines. 7. A fourth conductive film having a small impurity diffusion coefficient is formed at least in a portion of the first insulated gate field effect transistor connected to the source of the third insulated gate field effect transistor. Claim 1
The semiconductor storage device described in 1. 8. In a semiconductor memory device having a static random access memory cell consisting of a flip-flop circuit having stacked insulated gate field effect transistors, a driving insulated gate field effect transistor of a first conductivity type formed on a silicon substrate; 1. A semiconductor memory device comprising, with an insulating film interposed therebetween, a second conductivity type load insulated gate field effect transistor made of a two-layer polysilicon film.