JPS63102237A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the area occupied by a monitor element in a chip region, and attain the miniaturization of a chip, by a method wherein several kinds of monitor elements to be incorporated in a wafer are arranged on a plurality of separately divided chip regions. CONSTITUTION:On a reticle, for example, four chip regions 3 are arranged. Patterns of, for example, four monitor element O, X, , square are arranged sepa rately on the four chip regions 3 one by one. Consequently, four chip region 3 on a wafer make up a set, and the four patterns O, X, , square are separately replicated on each chip region 3 of the set. Therefore, the number of monitor elements arranged on the chip region 3 is one. Thereby the number of monitor elements arranged on the chip region 3 is reduced, so that the chip region 3 that is a chip itself can be made small in accordance with the reduction amount. Further this miniaturization requires no modification in a manufacturing process containing the manufacture of a mask.

Description

[Detailed Description of the Invention] [Summary] In manufacturing a semiconductor device in which a plurality of types of monitor elements are incorporated into a chip area of a wafer, chip miniaturization is achieved by distributing the plurality of types of monitor elements in a plurality of chip areas. The aim is to

[Industrial application field]

The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of arranging a plurality of types of monitor elements in a chip area of a wafer.

In the manufacture of semiconductor devices, particularly semiconductor integrated circuits (ICs), monitor elements based on the circuits to be formed are often incorporated into the chip area or scribe line portion of the wafer due to the reliability of the wafer process.

Generally, a plurality of chips with the same circuit are manufactured from one wafer, and it is desired to make the chips smaller.

[Conventional technology]

Chips on which circuits are formed and used in semiconductor devices are generally rectangular, and each chip area is arranged in a matrix on a wafer using a wafer process that typically involves multiple photolithography techniques. It is manufactured by forming a circuit and then cutting it along scribe lines that partition chip areas.

In photolithography technology, a pattern necessary for forming the above-mentioned circuit is provided on a mask or a reticle, and the pattern is transferred to a wafer by exposure. In the case of a reticle, step-and-repeat exposure is used because only a portion of the wafer is covered. Furthermore, a mask that covers the entire surface of the wafer is manufactured by transferring a reticle.

On the other hand, in the above wafer process, to confirm the process,
A plurality of types of monitor elements based on the circuits to be formed are often incorporated into the chip area or scribe line portion of the wafer.

FIG. 2 is a plan view fal (b
) (cl.

In the figure, figure (a) shows the reticle, figure tc+ shows the mask, figure tc+ shows the wafer, 1 is the chip area of the reticle, 2 is the chip area of the mask, 3 is the chip area of the wafer, and 4 is the scribe. The relationship is such that the transfer of the chip area 1 forms the chip area 2 and the transfer of the chip area 2 forms the chip area 3.

Moreover, ◯, ×, △, and mouth each indicate patterns of monitor elements with different contents. Here, it is assumed that these four elements are all of a plurality of types of monitor elements that need to be incorporated into the wafer.

One chip area 1 is provided on the reticle, and the patterns Q, x, Δ, and mouth are arranged in that chip area 1.

Therefore, on the wafer, as shown in FIG. tc, the openings are transferred to the patterns ○,

Note that the above-mentioned arrangement of the monitor elements may also utilize the portion of the scribe line 4 that is in contact with the chip region 3, but such a case is also included in the above description. In that case, the chip area 3 including the portion in contact with two adjacent sides of the chip area 3 in the scribe line 4
You can treat it as such.

However, since the scribe line 4 is usually used as a space (alignment mark space) for arranging alignment marks for a reticle or a mask, the space that can be used for arranging monitor elements is not so large.

[Problem that the invention seeks to solve]

As circuits become more sophisticated, the number of types of monitor elements required and the alignment mark space increase.

Further, since the monitor element includes connection pads for monitoring, the pattern of the monitor element is larger than the pattern of the element incorporated into the circuit.

For this reason, as the circuit becomes more sophisticated, the area occupied by the monitor element in the chip area 3 increases, causing a problem that the chip area 3, that is, the chip becomes larger.

[Means for solving problems]

The above problems are solved by the manufacturing method of the present invention, in which a plurality of types of monitor elements to be incorporated into a wafer are distributed and arranged in a plurality of chip areas.

According to the present invention, it is preferable that the above-mentioned dispersion be performed in a plurality of chip regions of the reticle which are the basis of pattern transfer to the wafer.

[Effect]

The above-mentioned dispersion reduces the number of monitor elements arranged in one chip area, so the area occupied by the monitor elements in the chip area decreases, and the chip area, that is, the chip, becomes smaller.

This dispersion needs to be incorporated into the mask pattern, but by doing it at the reticle stage as described above, there is no need to change the semiconductor device manufacturing process, including mask production, from the conventional one, and it can be easily done. It can be implemented.

〔Example〕

Hereinafter, an embodiment of the method of the present invention will be described below.
This will be explained using t (bl tc). The same reference numerals indicate the same objects throughout the figures.

FIG. 1 is a diagram corresponding to FIG. 2 explaining the conventional method. As in the case of FIG. 2, the transfer of chip area 1 forms chip area 2, and the transfer of chip area 2 forms chip area 3.

The reticle is provided with four chip areas 3, and the four monitor element patterns ○,

Therefore, on the wafer, as shown in Figure (C1), four chip areas 3 form one set, and four patterns O1×, △, and openings are distributed one by one in each chip area 3 in the set. The number of monitor elements arranged in the chip area 3 becomes 1 (flit).

This reduces the number of monitor elements arranged in the chip area 3 to 1/4 of the conventional method shown in FIG. 2, and reduces the size of the chip area 3, that is, the chip, in proportion to the reduction.

However, this miniaturization does not require any changes to the manufacturing process, including mask production.

Note that, as in the case of the description of the conventional method, the above-mentioned arrangement of the monitor elements includes the case where the portion of the scribe line 4 in contact with the chip region 3 is also utilized. In that case, the portions of the scribe line 4 that are in contact with two adjacent sides of the chip region 3 may be treated as the chip region 3 .

In this case, when the arrangement of the monitor element is absorbed into the scribe line 4, chip miniaturization will not be realized, but as the circuit becomes more sophisticated, the reality is that the alignment mark space mentioned earlier Due to the influence of the increase in the amount of noise, it is generally necessary to use the chip area 3 as the area for arranging the monitor element.

In the above embodiment, the pattern is transferred from the reticle to the mask.
Although the explanation has been made in the case of a wafer, it goes without saying that the same applies to the case of a reticle-wafer.

〔Effect of the invention〕

As explained above, according to the configuration of the present invention, in manufacturing a semiconductor device in which multiple types of monitor elements are assembled on a wafer, the monitor elements can be arranged in a chip area without changing the manufacturing process including mask production. This has the effect of reducing the area occupied and making it easier to miniaturize the chip.

[Brief explanation of the drawing]

FIG. 1 is a plan view illustrating an embodiment of the method of the present invention, and FIG. 2 is a plan view illustrating a conventional method. In the figure, 1 is the chip area of the reticle, 2 is the chip area of the mask, 3 is the chip area of the wafer, 4 is the scribe line, and ○, ×, and △ are the patterns of the monitor element.

Claims (1)

[Claims] 1) When forming a plurality of rectangular chip areas partitioned by scribe lines and having the same circuit on a wafer, and incorporating a plurality of types of monitor elements based on the circuit into the chip area, the above-mentioned A method for manufacturing a semiconductor device, comprising distributing and arranging a plurality of types of monitor elements in a plurality of the chip regions. 2) The method for manufacturing a semiconductor device according to claim 1, wherein the dispersion is performed in a plurality of chip regions of a reticle that serve as a basis for pattern transfer to the wafer. .