JPS6034016A - Semiconductor integrated circuit wafer and mask for manufacturing the same - Google Patents

Abstract

PURPOSE:To facilitate assembly and environmental tests by a method wherein, when a plurality of rectangular chips with different chip sizes are formed on one semiconductor substrate, a plurality of the chips of one type and a plurality of the chips of another type are formed separately with a scribing line at their boundary in such a manner that the two types of chips touch with each other at their corners and vacant regions formed by above method are removed. CONSTITUTION:When chips of LSI-A and chips of LSI-B, which have chip sizes different from each other, are formed on the same semiconductor substrate, at first LSI-A chips are formed above a scribing line, which is used as a boundary, using one type of mask. Then LSI-B chips are formed below the scribing line so as to make corners of LSI-B chips touch the corners of LSI-A chip using another type of mask. Thus, the formation of these LSI chips is made easier. With this method, vacant regions 2 are formed above the scribing line and between LSI-A chips and vacant regions 3 are formed below the scribing line and between LSI- B chips, but these regions are unnecessary parts and cut off at the time of scribing.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to a semiconductor integrated circuit wafer and a mask used for manufacturing the same, and particularly relates to a single semiconductor wafer.

[Prior art]

Conventionally, two different chip sizes were placed on one semiconductor wafer.
When a large-scale integrated circuit of type 6 (denoted as LSI) is completely formed, it is not shown in the g1 diagram.
-A and LS I-B of width XB and length B are combined with free area 1 to form a rectangular pattern with two sides of XA + XB (!: yA).

When using a stepper as a device for aligning and exposing an LSi pattern on a semiconductor wafer, the pattern shown in Figure 1 is used as a mask for integrated circuit manufacturing by 5 to 1 inch of the actual pattern.
Using a size 0x, reduction projection exposure is performed at a period of yA in the vertical direction and XA0xB in the horizontal direction. If a mask contact type alignment exposure device is used, a mask is used in which the actual size pattern shown in FIG. 1 is repeatedly formed in the vertical direction at a period of yA l in the horizontal direction at a period of XA and XB.

In either alignment exposure method, the LSI as shown in Figure 2
A pattern will be formed on the semiconductor wafer.

When this wafer is separated using a dicing saw, chips A and LSI-H having patterns of LSI-A and LSI-H shown in FIGS. An added chip Bl is obtained.

Next, it is necessary to separate the chip B1 into the product chip B and the empty area 1, but since this scribe line overlaps the side surface of the chip A, it is impossible to make any scratches with the dicing saw. Coupled with the fact that the chip B1 is small, a huge number of man-hours are required for separation, and in many cases it is unavoidable to assemble the chip B1 as it is.

However, it is difficult to assemble a chip with empty area 1 in anything other than a ceramic case unless there is a bonding pad around the empty area of the LSI-H, and since it is still different from the mass-produced product, it is subjected to environmental tests under the same conditions. There was a drawback that it could not be done.

[Purpose of the invention]

An object of the present invention is to provide a semiconductor integrated circuit wafer in which many types of LSIs are formed on a single wafer, and LSI chips that can be cut with a dicing saw without leaving any inconvenient empty areas, except for the above-mentioned drawbacks. The object of the present invention is to provide a mask for use in manufacturing the same.

[Structure of the Invention] The semiconductor integrated circuit wafer of the first aspect of the present invention is a semiconductor integrated circuit wafer in which a plurality of rectangular integrated circuits each having a chip size of at least 2af are formed on a single semiconductor substrate, and each integrated circuit is divided into rectangular shapes on a single semiconductor substrate. In a semiconductor integrated circuit wafer to be used separately, integrated circuit chips of the same size among the chips are placed in the same row or column divided by scribe lines for separating into individual integrated circuit chips and free space chips. integrated circuit chips of different sizes are arranged in separate rows or columns separated by the scribe line, and adjacent chips of different sizes touch each other at corners of the chips, and the two sides of each chip sandwiching the corner have at least two masks to be used for each other.
In the mask used for manufacturing semiconductor integrated circuits in which integrated circuit patterns designed to have a chip size of FII class are formed in rectangles corresponding to each chip size, and a large number of these rectangular patterns are arranged on the same substrate. , among the integrated circuit chip patterns, one circuit chip pattern of the same size is divided into individual integrated circuit chips as well as free area chips. ) arranged through multiple turns,
km circuit chip patterns of different sizes are arranged in separate rows or columns demarcated by the scribe lines, and Afl+
The chip patterns of different sizes in the J alignment are arranged so that they touch each other at the corner of the chip pattern, and the two sides of each chip pattern that sandwich the corner are perpendicular to each other.

[Explanation of Examples]

Next, embodiments of the present invention will be briefly explained with reference to the drawings.

FIG. 4 is a schematic diagram of the basic pattern used for forming the mask of the present invention.

In FIG. 4, LSI-A is a first LSr chip pattern and LSI-B is a second LSI chip pattern. The vertical and horizontal dimensions of these two LSI chips are x
A, ya and xRlyn are different.

The corners of the first LSI chip pattern and the second LSI chip pattern touch each other at the 0 point, and the two sides that sandwich the 0 point, that is, the two sides of the first chip pattern □x, □y and Qx' of the two sides of the second chip pattern
, oy' are arranged so that their sides are at right angles. That is, the angles of XOY' and YoX' are right angles, and as a result, XQX' and YOY' form straight lines and intersect at right angles. Furthermore, free area 2 and free area 3 are areas that become empty chips. In other words, basic nokter yiixA+XB
It forms a rectangle surrounded by sides yA+yB, and is divided into four chip patterns by dividing lines XX' and YY' corresponding to the scribe line.If an integrated circuit is formed on the wafer using this pattern, four chip patterns will be formed. One chip can be formed and two empty chips of 2.3 are left. As a result, the integrated circuit chip forming an integrated circuit and the empty chip requiring separation are completely separated.

FIG. 5 is a diagram showing the layout of the chip and turns of an embodiment of the mask of the present invention, in which the basic turns shown in FIG. 4 are repeatedly written in the horizontal direction at a period of XA+XB. If integrated circuits are formed on the wafer using this method, an integrated circuit wafer formed in the same pattern as shown in FIG. 5 can be obtained.

When this integrated circuit wafer is cut and separated using a dicing saw, LSI-
A, LSI-B, empty chip 2. Four types of chips are obtained: two integrated circuit chips with empty chips 3 and two empty chips. Chip A and LSI with LSI-A pattern
- Chip BK with pattern B contains no free space.
Therefore, assembly and environmental tests can be carried out in an unreasonable manner.

In the above embodiment, a case has been described in which two types of LSIs with different chip sizes are formed on one mask and one wafer, but the same can be applied to the case of three or more LSIs.

It is also possible to insert alignment patterns, device patterns for evaluating special characteristics of each glaze device, circuits for characteristic evaluation, etc. into at least some of the empty chips shown in Fig. 6 fa) to fd). A Q integrated circuit chip is created.

〔Effect of the invention〕

As explained above, according to the present invention, many types of LSI
is formed on a single wafer and cut with a cutting tool without leaving any inconvenient free space! LS that can be separated
A semiconductor integrated circuit wafer on which an I-chip is formed and a mask used for manufacturing the same can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a basic pattern layout diagram of an example of a combination of two types of conventional LSI chip patterns, FIG. 2 is a chip pattern layout diagram of an example of a conventional mask, and a pattern layout diagram of a conventional example. FIG. 4 is a schematic diagram of the basic pattern used for forming the mask of the present invention; FIG. 5 is a chip pattern layout diagram of an embodiment of the mask of the present invention; Figures 6(, l) to (dl are plan views of chips separated by #ilC from the integrated circuit wafer of the present invention. Turn, LSI-B, B...B chip or B LSI Pattern, B1 chip...B chip with 1 free area.

Claims (2)

[Claims] (1) In a semiconductor integrated circuit wafer in which a plurality of rectangularly designed integrated circuits of at least two different chip sizes are formed on a single semiconductor substrate and used by separating into chip units, Among them, integrated circuit chips of the same size are arranged in the same row or column with free space chips separated by scribe lines to separate individual integrated circuit chips and free space chips, and integrated circuits of different sizes are arranged through free space chips. The chips are arranged in separate rows or columns defined by the scribe line, and the adjacent chips of different sizes touch each other at the chip corners, and each chip is placed between the corners. ? 1. A semiconductor integrated circuit wafer, characterized in that a U layer V has 41 colors and one set of layouts is included in the RH layer 1. (2) At least part of the free area of the chip is provided with alignment patterns, devices for measuring various device characteristics, etc. (3) Integrated circuit patterns designed for at least two types of chip sizes are placed within a rectangle corresponding to each chip size. In a mask used for manufacturing a semiconductor integrated circuit in which a large number of rectangular patterns are formed and arranged on the same substrate, the integrated circuit chip patterns of the same size among the integrated circuit chip patterns are separated into individual integrated circuit chips. and integrated circuit chip patterns of different sizes are arranged in the same rows or columns demarcated by scribe lines to separate the free area chips, and integrated circuit chip patterns of different sizes are arranged in separate rows or columns demarcated by the scripe lines. The chip patterns that are arranged in the same direction and have different sizes are in contact with each other at the corner of the chip pattern, and the two sides of each chip pattern that sandwich the corner are perpendicular to each other (4) At least a part of the free area Batabe pattern for various device characteristic evaluation, characteristic evaluation