JPS63102236A - Output terminal test circuit - Google Patents

Abstract

PURPOSE:To improve the efficiency to check electric characteristics, for example, DC characteristics of output terminals, by providing a part between an internal circuit and an output buffer stage with a test circuit for checking the ouput terminals, and making it possible to set conditions of the output terminals in accordance with the output conditions of the test circuit. CONSTITUTION:An output terminal test circuit comprises an inverter 11, an AND circuit 12 and an OR circuit 13. Input terminals A and B are supplied with test signals constituted of H level and L level from the output of a decoder circuit, and receive the signals which have inverse polarity with each other. When L level or H level as a test signal is given to the input terminals of the output terminal test circuit in this manner, H level or L level can be output in accordance with the combination of inputs H and L and independently of the outputs H and L of an internal circuit. Consequently, in the case of, for example, checking DC characteristics of output terminals, desired output conditions can be obtained by controlling input conditions of the test circuit. The checking efficiency can be remarkably increased thereby.

Description

[Detailed Description of the Invention] [Summary] When testing the electrical characteristics of the output terminal of a semiconductor integrated circuit (hereinafter referred to as IC), an output terminal is connected between the internal circuit and the output buffer stage in order to perform the test efficiently. A test circuit for terminal testing is provided, and the state of the output terminal can be set in accordance with the output state of the test circuit.

[Industrial application field]

The present invention relates to an output terminal test circuit for testing electrical characteristics at an output terminal of an IC.

[Problems to be solved by conventional technology and invention] IC
One of the performance tests is to check whether the electrical characteristics of the output terminals, such as the output voltage at high (H) level, the output voltage at low (L) level, and each inflow current, have reached the specified level. Direct current (D) to check externally
C) There is a characteristic test. In this case, the electrical characteristic test of the output terminal is equivalent to the DC characteristic test of the immediately preceding output buffer stage. The output buffer is used to amplify the output level of internal circuits such as logic circuits and supply it to other IC chips, etc. Therefore, it is necessary to check whether the output terminal level has reached a predetermined value. There is.

Conventionally, in order to test an output terminal, when setting the output of an output buffer to a predetermined H or L level state, input signals from the outside to the internal circuit are changed to various states until a predetermined state is obtained at the output terminal. I needed to see it. That is, there is a problem in that the state of the output terminal corresponding to the test input cannot be determined until the logical configuration of the internal circuit is investigated, and this has significantly reduced the efficiency of DC characteristic testing.

[Means and operations for solving the problems] The present invention provides an output terminal test circuit for solving the above-mentioned problems. The output terminal test circuit is provided between an output buffer stage and an internal circuit, and includes an inverter that receives one test signal, and an inverter that receives the output of the internal circuit at one input and outputs the output of the inverter from the other. and an OR circuit that receives the output of the AND circuit at one input, receives the other test signal at the other input, and inputs the output to the output buffer stage. Features.

〔Example〕

FIG. 1 is a circuit diagram of an embodiment of an output terminal test circuit according to the present invention. In FIG. 1, OUT is an output terminal, BF is an output buffer stage, INC is an internal circuit such as a logic circuit, and the area inside the dotted line is an output terminal test circuit according to the present invention. The output terminal test circuit is composed of an inverter (INV) 11, an AND circuit 12, and an OR circuit 13. Input terminal A
, B are supplied with H level and L level test signals from the output of the decoder circuit shown in FIG. Input terminals A, H
It is assumed that test signals of opposite polarity are input to the terminals.

For example, when an L level signal is input to terminal A and an H level signal is input to terminal B, - Since the output of the inverter 11 becomes H level, corresponding to the H or L level of the output of the internal circuit INC, The output of the AND circuit 12 becomes H or L level.

On the other hand, since terminal B is at H level, OR circuit 13 always outputs H level regardless of whether the output of AND circuit 12 is H or L.

On the other hand, when terminal A is at H level and terminal B is at L level,
Since the output of inverter 11 is at L level, internal circuit INC
The output of the AND circuit 12 is at L level regardless of the H or L level of the output. Therefore, the output of the OR circuit 13 is always at L level.

In this way, if you input L level or H level as a test signal to the input terminals A and B of the output terminal test circuit, it will always correspond to the combination of input H and L, regardless of the output H and L of the internal circuit. It can output H level or L level. The output of this OR circuit 13 is input to the output buffer circuit BF, amplified, and appears at the output terminal OUT. Therefore, when testing the DC characteristics of the output terminal, by controlling the input state of the test circuit, a desired output state can be obtained, and the test efficiency is greatly improved.

FIG. 2 shows a decoder circuit for obtaining test signals of a predetermined level to the input terminals A and B of FIG. 1.

In FIG. 2, the decoder circuit includes an inverter (INV
) 21 and 22, and AND circuits 23-26. The output of the AND circuit 25 is supplied to the A terminal of the output terminal test circuit, and the output of the AND circuit 26 is supplied to the B terminal of the test circuit. An H level signal indicating the start of a test is input to the T terminal of the decoder circuit. On the other hand, an H signal or a combination of L and H signals is input to the input terminals IN and INK.

For example, when input terminal IN is at H level and input terminal INz is at L level, the output of inverter 21 is at L level, so the output of AND circuit 23 is at L level, and on the other hand, the output of inverter 22 is at H level, so A N D circuit 24
The output becomes H level.

Furthermore, since the test signal is at H level, the AND circuit 25
The output of the A N D circuit 26 is at L level, and the output of A N D circuit 26 is at H level.

On the other hand, input terminal IN is at L level and input terminal IN is at H level.
Since the output of the inverter 21 is at the H level, the output of the AND circuit 23 is at the H level, and since the output of the inverter 22 is at the L level, the output of the AND circuit 24 is at the L level.

Furthermore, since the test signal is at H level, the AND circuit 25
The output of the AND circuit 26 is at H level, and the output of the AND circuit 26 is at L level.

For test signals to terminals T, IN, and IN2, for example, a test bit pattern is prepared in advance in a register, and when this test bit pattern is output from the register, a DC characteristic test is performed. Even if the logical configuration of the internal circuit is unknown, the state of the output terminal can be known regardless of the level state of the output of the internal circuit, and testing can be performed efficiently.

〔Effect of the invention〕

As explained above, according to the present invention, since the state of the output terminal can be set arbitrarily, the DC characteristic test of the output terminal can be easily performed.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an embodiment of an output terminal test circuit according to the present invention, and FIG. 2 is a decoder circuit for supplying signals to the circuit of FIG. (Explanation of symbols) 11, 21, 22...inverter, 12, 23
~26...AND circuit, 13...OR circuit.

Claims (1)

[Claims] 1. An output terminal test circuit provided between an output buffer stage and an internal circuit for testing the electrical characteristics of an output terminal of a semiconductor integrated circuit, the circuit receiving one test signal. an inverter; an AND circuit that receives the output of the internal circuit at one input and receives the output of the inverter at the other input;
An output terminal test circuit comprising an OR circuit that receives the output of the AND circuit at one input, receives the other test signal at the other input, and inputs the output to the output buffer stage. 2. The circuit according to claim 1, wherein the one test signal and the other test signal have opposite polarities.