JPH01128611A - Mos integration circuit device - Google Patents

Abstract

PURPOSE:To obtain an MOS integration circuit device, which easily detects disconnection, by executing a wiring so that a signal to control the turning on and off of first and second transmission gates can be connected to the gate terminal of the second transmission gate at first and after that, connected to the gate terminal of the first transmission gate. CONSTITUTION:When the disconnection is generated between the part of a CLK and -CLK lines and a second transmission gate 7, for example, when the disconnection is generated in a point R15 and the gate of the Nch of the second transmission gate 7 and the gate of the Pch of a first transmission gate 4 are held by an 'L', the Nch of the second transmission gate 4 is always turned off and the Pch of the first transmission gate 4 is always turned on. Accordingly, when the drive ability of input data is higher than the drive ability of holding data, a disconnected part can be detected even when the gate is held by the 'L' or held by an 'H'. Then, detecting ability is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] This invention relates to MO8 integrated circuits, and more particularly to D-latches using transmission gates.

[Conventional technology]

An example of a conventional D latch using a transmission gate is shown in Fig. 5, and an example of its pattern diagram is shown in Fig. 6. By using a transmission gate, it is possible to create a latch with a small number of transistors and a small area. .

In FIG. 5, (1) is a data input section, (2) is a clock (hereinafter referred to as CLK) input section, (3) is a CLK input section, and (4) is a first transmission for controlling input data. , (5) (61 is an amplification means, and two inverters are connected in series to the first transmission gate, and (7) is connected in parallel to these two inverters (5) and (6). , a second transmission gate for controlling data retention;
In (8) and (9), the nodes P, Q, and αG are the output parts of the D latch, respectively. The CLK line and CLK@ are
It is divided in the middle into the first transmission gate and the one going to the second transmission gate,
The second transmission gate is wired to be ON only when no data is being received.

In FIG. 6, Ql) is polysilicon, (2) is a diffusion, (2) is an Ae metal tlA, and Q4 is a contact.

FIG. 7 also shows the portion of the circuit shown in FIG. 5 from the CLK line input to the second transmission gate (7), especially the portion from the CLK line input to the second transmission gate (7). This is an example of a circuit diagram in the case where a disconnection occurs between the part that separates into the opposite side and the transmission gate @2. FIG. 8 is a timing chart of this circuit. 01 is the CLK signal, (b) is the input data, (to) is the output when normal, and Q9 is the output when writing is desired but cannot be performed.

Next, the operation will be explained. In the circuit of Fig. 6, C
When the LK signal (2) is "Hl", the first transmission gate (4) is ON, and the second transmission gate (7) in the circulation path for data retention is OF.
Therefore, when the input data is output through two inverters and the CLK signal (2) changes to 1H1 or "L", the first transmission gate (4) turns OFF L and the second When the transmission gate (7) is turned on, the last input data is held in the circulation path and continues to be output. [Problem to be solved by the invention] In the conventional circuit, the second transmission CLK and CLK connected to the gate terminal of gate (7)
fi, in particular the first transmission gate (4)
and the second transmission gate (7
) Consider a case where a disconnection occurs between the part where the transmission gate splits into the opposite direction and the second transmission gate (7). For example, if ITTls occurs at point R (to) as shown in Figure 7. It is.

First, the Nch of the second transmission gate (7)
Assuming that the gate of the second transmission gate (7) is held at 1L'', the Nch of the second transmission gate (7) is always in the OFF state, but the Pch operates normally.At this time, the 11H
When the @ signal enters the second transmission gate (7), it is normally output as fi 'H', but the s L @ signal enters the second transmission gate (7). At this time, in order for current to flow through the second transmission gate (7), the potential on the output side must be higher than VTH, so the potential on the output side will rise to VTH due to a minute leakage current. In that case, in the inverter (5), Pch
A small amount of current flows from the Nch to the Nch, and power is consumed by the inverter (5). However, as the output of the D latch,
It is output normally in wLg. Also, assuming that the Nch gate of the second transmission gate (7) is held at IHL, the second transmission gate (7)
Nch 7) is always in the ON state, so that when writing is attempted, the input data and the held data collide at node (8). When the ability and shi are high, (as in II, when you want to write,
If no writing is done and vice versa, normal output is obtained.

In this way, in the conventional case, the disconnected part is held by IHL and is output normally except when the drive capacity of the held data is higher than the drive capacity of the input data.
Of the CLK and CLK lines connected to the gate terminals of the second transmission gate (7), especially those directed to the first transmission gate (4),
There is a problem in that it is difficult to detect a disconnection that occurs between the part where it splits toward the transmission gate (7) and the second transmission gate (7) because it requires checking the output.

This invention was made to solve the above-mentioned problems.
An MO3 integrated circuit device is provided in which a disconnection that occurs in the K line, especially from the part where it is divided into the part going to the first transmission gate and the part going to the second transmission gate, to the part leading to the second transmission gate is easily detected. The purpose is to obtain.

[Means for solving problems]

In the MO8 integrated circuit device according to the present invention, the CLK and CLK signal wiring connected to the gate terminals of two transmission gates are first connected to the gate terminal of the second transmission gate, and then the wiring for the CLK signal is connected to the gate terminal of the second transmission gate. The wiring is connected to the gate terminal of the gate.

[Effect]

In this invention, the CLK signal and the CLK signal wiring are first connected to the gate terminal of the second transmission gate, and then connected to the gate terminal of the first transmission gate. If a disconnection occurs in the part from the CLK and CLK line input to the second transmission gate, the effect will also be felt on the first transmission gate, so check the output to determine if the disconnection in this part occurs. Detection becomes easier by 1.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIG.

Figure 1 (here, (1) is the data input section, (2) is the C
The LK signal input section (3) is the CLK signal input section, (4)
is the first transmission game for controlling data input), (5) l (6) is the first transmission game as the amplification means.
two inverters connected in series with the transmission gate (4), (7) a second transmission gate for controlling data retention connected in parallel to the two inverters, (8) l (9) are nodes P and Q where the second transmission gate is connected in parallel.

αO is the output of the D latch. Then, the CLK line and the CLK line are first connected to the second transmission gate.
(7) and then the first transmission gate (4).

Figure 2 is an example of the pattern diagram of the circuit shown in Figure 1, where α is polysilicon, (2) is diffusion, and (to) is AI.
! Wiring, alpha cap, contact.

Figure 8 is a circuit diagram when a disconnection occurs in the circuit shown in Figure 1 from the CLK line input section to the second transmission gate), and Figure 4 is a circuit diagram of the circuit shown in Figure 8. 3 is a timing chart of the illustrated circuit.

σ0 is the CLK signal, α power is the input data, (goods) is the output when normal, 109 is the output when writing is not possible even though you want to write, and gradient is the output when writing is done even though there is no need to write. , (goods) is the output when a write delay occurs.

In the circuit of the present invention shown in FIG. 1, if a disconnection occurs between the CLK and CLK line input section and the second transmission gate (7), for example, the disconnection occurs at point R (b) as shown in FIG. Consider a time when this occurs. At this time, the Nch gate of the second transmission gate (7) and the Pch gate of the first transmission gate (4) are 1
If it is held at L1, the Nch of the second transmission gate (7) is always OFF! 0, fil
The Pch of the transmission gate (4) is always ON.
becomes. Therefore, when trying to hold data, the input data and the held data collide at node P(8), so when the drive ability of the input data is higher than that of the held data, (1) like,
The second transmission gate (7
) and the Pch gate of the transmission gate (4) of JLL are held at 'H6, then the Nc of the second transmission gate (7)
h is always ON, fi, and Pch of the first transmission gate (4) is always OFF. Therefore, when trying to rewrite, at node P(8),
Input data and retained data will collide. At this time, if the drive ability of the retained data is higher than the drive ability of the input data, it becomes impossible to write when desired, as in the case of Q scratches. Conversely, even when the drive capacity of the input data is higher, writing is performed, but
Normally, Yoshishi will also be written with a delay.

Therefore, compared to the conventional method, when the drive ability of the retained data is higher than that of the input data, the detection ability remains the same whether the disconnected part is held in %@ or IHI, but the drive ability of the input data is higher than that of the input data. When the capacity is higher than the drive capacity of the retained data, the vlT line part is
Detection is possible even when held at "L" or "1H", and the detection ability is improved. Therefore, in this circuit, if the drive ability of input data is made higher than the drive ability of retained data, it becomes possible to detect the H line.

Note that in the above embodiment, two inverters (5) #(6) are connected in series as amplification means, but four inverters may be used instead, or something other than the amplification means may be used. . For example, in place of the inverter (5), a two-man powered NOR gate can be used, one of the inputs is connected to this circuit, and the other is an input from the outside, and the SET can be directly set to the SET state by this external signal. With D
It can also be used as a latch. Conversely, a D-latch with RESET may be created by similarly connecting two NOR gates to the inverter (6) instead of the inverter (6), which can be set to the DRESET state by an external signal.

Regarding the input section, there are several input sections, and each input is equipped with a transmission gate, so that data is always input from one of them, and only when there is no input, a transmission gate is installed for data retention. It may also be used by turning on.

〔Effect of the invention〕

As described above, according to the present invention, the CLK and CLK lines are first connected to the gate terminal of the second transmission gate, and then connected to the gate terminal of the first transmission gate, so that the CLK and C
This has the effect of making it easier to detect a disconnection that occurs between the input of the LK line and the second transmission gate.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an MO3 integrated circuit device according to an embodiment of the present invention, FIG. 2 is an example of its pattern diagram, and FIG. Fig. 4 is a timing chart of the circuit shown in Fig. 8. Fig. 5 is an example of a circuit diagram of a conventional circuit. An example of a pattern diagram, FIG. 7, shows the part of the circuit shown in FIG. 5 from the CLK line input to the second transmission gate, especially the part going to the first transmission gate and the second transmission gate. An example of a circuit diagram in the case where a disconnection occurs between the part divided into the second transmission gate and the second transmission gate, FIG.
3 is a timing chart of the circuit shown in the figure. (1) is the data input part, (2) is the CLK input part, (
3) is the CLK input part, (4) is the first transmission gate, r5), (6) is the inverter, (7)
is the second transmission gate, (s), (9
) are nodes P and Q, respectively. αO is the output part 1 of the D latch. (b) is polysilicon,
(2) is diffusion, (to) is M wiring, α→ is contact, (
) is the point R1α・ is the CLK signal, αη is the input data, (
(goods) is the output of the D latch when it is normal, time a is the output when writing is desired but cannot be done, (transfer) is the output when writing is done even though there is no need to write, (
2) is the output when a write delay occurs.

Claims (1)

[Claims] a first transmission gate that controls data input; an amplification means connected in series with the first transmission gate; and an amplification means connected in parallel with the amplification means;
and a second transmission gate for controlling data retention by turning OFF when an input is taken in and turning ON when an input is not taken, and turning the first and second transmission gates ON and OFF. A MOS integrated circuit characterized in that the wiring is such that a signal for controlling the transmission gate is first connected to the gate terminal of the second transmission gate, and then connected to the gate terminal of the first transmission gate. circuit device.