JPS6299965A - Error correcting method - Google Patents

Abstract

PURPOSE:To prevent a useless correcting process so as to improve the error correcting capacity, by performing the next correcting process about one sequence containing words corrected by the other sequence of cross interleave code only. CONSTITUTION:The P sequence (solid lines) on one side of error correcting codes is that obtained by encoding simple parity codes on three words D0, D1, and D3 at every five blocks and the Q sequence (broken lines) on the other side is that obtained by encoding simple parity codes on three words of D0, D1, and D2 at every four blocks. When the number of error words in one sequence is one at the time of the 1st correcting process P1 about the P sequence, the error word is corrected and the base flag of the Q sequence containing the corrected error word is set to '1'. At the time of the 1st correcting process Q1 about the Q sequence, the base flag of the P sequence containing the corrected word is set to '1'. The 2nd correcting process P2 about the P sequence is performed on a sequence containing the corrected word at the correcting process Q1 only. Thereafter, the correcting process is alternately performed about the Q and P sequences.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an error correction method used in an audio PCM signal recording/reproducing device, a digital audio disc, and the like.

[Summary of the invention]

The present invention provides an error correction method for decoding a data signal in which a plurality of data words formed by a predetermined number of bits are provided with error correction codes according to a first series and a second series. The correction process based on the series and the second
When the correction processing using each series is repeated and the correction processing using each series is performed, the other series containing the word corrected using one series is written as 1. By setting the correction processing using the other series only on the stored series, the number of effective correction processing within a limited time can be increased, and the correction ability can be substantially reduced. In addition, by not performing unnecessary correction processing, it is possible to reduce power consumption.

[Conventional technology]

When recording a digital audio signal on a magnetic tape or the like, a cross interleave code is used as an error correction code. A cross-interleaved code is a cross-interleaved code that, for a plurality of data blocks consisting of a predetermined number of data words,
Error correction codes for a first sequence (referred to as P sequence) and a second sequence (referred to as Q sequence) are provided, and correction processing for the P sequence and correction processing for the Q sequence are repeated.

In conventional cross-interleave code decoding, correction processing is performed on all sequences in each of the correction processing for the P sequence that is performed multiple times and the correction processing for the Q sequence that is performed multiple times. Correction processing is performed by receiving (
This is done by storing the reproduced data in a memory, reading out the words in one series sequentially from the memory, and supplying them to an error correction circuit. When a stroke parity code is used as an error correction code, it is possible to correct an error word only when there is one error word in one series.

[Problem that the invention seeks to solve]

If a sequence read from memory for error correction contains an error word of two or more words,
In the case of simple parity codes, error correction is not possible. Therefore, the time and memory required to process this series,
The power consumed by the error correction circuit and the like is completely wasted. In addition, the time available for error correction processing is usually limited to a predetermined amount of time, so if there is a lot of wasted time as described in -F, the number of words that can be corrected will be reduced and the correction ability will be reduced. .

A sequence that has been corrected at least once has one error word.
Either there are no words or there are so many error words that they cannot be corrected.

Therefore, for a series that has undergone correction processing even once, the possibility that effective correction processing can be performed thereafter is limited to after the error words in this series are corrected by the Ike series. Therefore, the present invention performs the following correction process only on the Q (or P) sequence that includes the word corrected by the P (or Q) sequence, thereby at least correcting the sequence for which the number of correct words has not increased. You can prevent this from happening.

An object of the present invention is to provide an error correction method with improved correction capability by performing more effective correction processing within a limited time.

Another object of the present invention is to provide an error correction method that can reduce power consumption of a memory, an error correction circuit, etc.

Means for Solving Problem C] This invention forms a data word using a predetermined number of bits of a digital signal, uses the predetermined number of data words as a data block, and sets a first sequence for a plurality of data blocks. In an error correction method for decoding a data signal provided with an error correction code according to a second series, the correction processing of the first series is performed on all data blocks, and the data is corrected or the error point ink is rewritten. and storing a second series including the data word with the data corrected or the error pointer rewritten, and performing the correction process of the second series on all data blocks, and correcting the data or rewriting the error pointer. rewriting the error pointer and storing a first sequence containing the data word with the data corrected or the error pointer rewritten; In particular, it consists of a system that performs correction processing only on the stored second sequence and the stored first sequence. Mistake as t!
] This is a correction method.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings. This explanation is made according to the following items.

a. Code structure, error correction method C0 of one embodiment; structure of decoding device of one embodiment; d; operation of decoding device of one embodiment; e; modification a; code structure; FIG. It shows the structure of a code block of an error correction code. One code block consists of 4 words (digital audio data consists of 2 words Do, D
The data block is composed of 25 blocks, each having two words of parity (D2, D3). Cross-interleaving is performed that is completed within this code block.

One P sequence is obtained by encoding, for example, a simple parity code on three words, data words Do, D1, and parity D3 included in every five blocks, as shown by the solid line. The other Q series is, as shown by the broken line,
Data words Do included in every four blocks,
For example, the three words Di and parity D2 are encoded with a simple parity code. That is, DO■D1■D3=D2゜DO■D1■D2=D3 (■ means addition of (fflod.2).) Each of the (2 x 25) word data included in the code block is , included in mutually different combinations of P and Q sequences.

As shown in FIG. 2, the above-mentioned data has a block synchronization signal and a block address added to the beginning of each block, and the block address and data DO.

Dl, parity D2. For error checking for D3.

The data is sequentially recorded on a magnetic tape by a rotating head in a data structure with a CRC code added thereto.

Data reproduced from the magnetic tape is subjected to error checking using a CRC code, and then written to the RAM. R.A.
One block of reproduced data written in M is subjected to correction processing. On this RAM, a 1-bit error flag is provided for each word and is set to "1" in advance, and data words determined to be correct as a result of the CRC check from the magnetic tape are written to the RAM. ’ is cleared to “O”.

b. Error correction method according to one embodiment The error correction method for the above-mentioned cross-interleaved code will be explained in accordance with the order of error correction.

In this embodiment, 1-bit registers are provided for all bases of each of the P, series, and Q series, and all base flags in the registers are cleared to "0" (.

A base whose base flag is set to 1'' indicates that the base should undergo correction processing.The number of bits in the register is:
(number of blocks x 2) bits, and in this example,
The number of bits of the register is 50 bits.

(2) First, the first correction process P1 regarding the P sequence is performed for all bases in order. The block of data words Do is called the base of the sequence. Therefore, there are 25 bases in each of the P and Q sequences. In correction processing P1, if there is only one error word in one series,
This error word is corrected and the error flag is cleared (set to "O"). If all words in one series are correct or if there are two or more error words, no processing is performed. In this correction process P1, if the correction is successful, the base flag of the Q sequence including the corrected word is set to 1'.

As a result, there are only sequences in which all words are correct and sequences in which two or more words are in error in the P sequence.

(2) Next, the first correction process Q1 regarding the Q sequence is performed for all bases in order. In this correction process Ql, if the correction is successful, the base flag of the P series including the corrected word is set to "1". As a result of this correction process Q1, there are only sequences in which all words are correct and sequences in which there are error words of two or more words in the Q sequence. On the other hand, there is a sequence in the P sequence that may have newly caused a one-word error, and this sequence is indicated by the base flag.

(2) Next, a second correction process P2 for the P sequence is performed. This correction process P2 is performed only on sequences that include the words corrected in the correction process Q1. That is, the contents of the P series register are checked from the first base, and since there is no possibility of correcting a series whose base flag is "0",
Proceeding to the next base, for the sequence whose base flag is set to l'', the base flag is cleared to "0" and correction processing is performed. If the correction is successful, regarding the Q sequence containing this corrected word. Cent the base flag of 1”,
When the above-mentioned processing is completed for the last base to proceed to the next base, the process proceeds to the next step (2).

(2) In this step, a second correction process Q2 is performed on the Q sequence. This correction process Q2 is similar to the correction process P2 in step (2) above.

Thereafter, correction processing for the P sequence and correction processing for the Q sequence are performed alternately. Then, when it becomes impossible to correct the ■ word in the P series or the Q series, the correction ends. However, the processing up to step (2) described above is always performed.

An embodiment of the present invention will be described with reference to a specific example shown in FIG. FIG. 3 shows a part of one code block, where the series indicated by a broken line indicates a Q series, the series indicated by a solid line indicates a P series, white circles are correct words, and black circles are error words after correction processing Pi. are shown respectively.

In the correction process Q1, the (1st of n)th and (n +
2) If the Q-sequences of the base are processed sequentially, then (n
The +1)th base sequence contains two error words W1 and W2, and therefore cannot be corrected, and no correction processing is performed. In the (0 to 2)-th base sequence, only one word W3 has an error, so the error in this word W3 is corrected. Along with this, P containing word W3
The 'nth base flag of the series is set to "1".

In the next correction process P2, the n-th, (He1)-th, and (n+2)-th base P sequences are processed in order. Since the n-th base flag is set to 1'' as described above, this The base flag is cleared to "0" and correction processing for this series is performed.Since the error in word W3 has been corrected in correction processing Q1,
The P sequence of the nth base has a one word error, and the error in word W l is corrected. The (n-i-1)th base flag of the Q sequence that includes this word W1 is “1”
is set to

Since the (n+1)th base of the next P series and the next (n+2)th base consist of only originally correct words, the base flag is "0" and no correction processing is performed.

Furthermore, in the next correction process Q2, the error in word W2 is corrected using the n-th base Q sequence. Therefore, in the example shown in FIG. 3, [P1→Q1→P2-Q
All errors are corrected by the correction process 2).

According to the invention described above, the time it takes to repeat four times an error word that can be corrected by the conventional method (Pi-Ql-P2-
All corrections can be made within Q2).

The reason why all theoretically correctable error words can be corrected by this invention will be explained. When the error can be corrected, there are cases where there was only one word error in one sequence from the beginning, and cases where there were 9 2-word words in 1 sequence, and 1 word among them was corrected by Kuiya's sequence and became 1 word. There are only two possibilities: if an error occurs.

In the former case, the error word is always corrected because the correction process Pl and the correction process Q1 are performed on all blocks. In the latter case, if the error word becomes a one-word error due to the correction process P1, the correction process Q1 is performed on all blocks, so it is always corrected even if it is not immediately after. A one-word error caused by the correction process Q1 and subsequent steps is always corrected immediately thereafter.

Next, in the present invention, the reason why error words can be corrected only by the number of processing times (number of blocks x 4 times) will be explained. 1
Only one word can be corrected by the series, so
Even if the number of times of correction processing is increased, only a total of (number of blocks x 2) words of the P sequence and Q sequence can be corrected.

Since the correction processes P1 and Ql in steps 2 and 3 are performed on all bases, the total number of processing times in steps 2 and 2 is [(number of blocks) x
2]. After the correction process Q2 in step (2), the correction process is performed only on the series including the corrected word, so the number of times of processing is (the number of corrected words). Therefore, the total number of processing times N has the following relationship.

N = (Number of blocks) x 2 (Number of corrected words) In the above formula, (Number of corrected words) means what has been corrected after step ■, which is calculated from [(Number of blocks) x 2] , always small. Therefore, the following relationship holds true: N≦(number of blocks)×4. In other words, all errors can be corrected by providing a processing time equivalent to the number of processing times (number of blocks x 4 times).

Configuration of decoding device of C0 embodiment A decoding device corresponding to this embodiment will be described with reference to FIGS. 4 and 5.

In FIG. 4, 1 indicates a data RAM for storing data of one code block (see FIG. 1) reproduced from, for example, a magnetic tape, and 2 indicates a correction circuit. Data words of each P series or Q series read from the data RAMI (including a 1-bit error flag) are supplied to the correction circuit 2, where they undergo correction processing.

The corrected data word is transferred from the correction circuit 2 to data R.
The data is supplied to the AMI and the data is updated.

In the correction circuit 2, an error pulse SE corresponding to the error word is generated. A block address BK and a word address WD are supplied to the data RAMI.

The block address BK is formed by the adder circuit 3 of Cmod, 25), and the word address WD is taken out to the output terminal 7 of the inch circuit 4. (m.

When the addition of d, 25) becomes a value of 25 or more, the value obtained by subtracting 25 becomes the addition result. When subtracting (mod, 25), if the value becomes negative, the value obtained by adding 25 becomes the subtraction result. Therefore, the addition or subtraction result of (mod, 25) is (
Only values from 0 to 24) exist.

One input terminal of the adder circuit 3 is supplied with the base address from the output terminal 12 of the switch circuit 9, and the other input terminal is supplied with the output of the multiplier circuit 13. The multiplication circuit 13 multiplies the word address WD by D (the number of blocks at intervals of the P series, in this example, 4 blocks). A multiplication circuit 13 is composed of a ROM, a bit shifter, and the like.

The switch circuit 9 is controlled such that an input terminal 10 and an output terminal 12 are connected when processing a P sequence, and an input terminal 11 and an output terminal 12 are connected when processing a Q sequence.

A base address from a base counter 14 is supplied to the input terminal 10 .

The input terminal 11 has an addition/subtraction circuit 15 of (mod, 25).
output is supplied. The addition/subtraction circuit 15 adds or subtracts the output of the base counter 14 and the output of the multiplication circuit 16. When processing the P series, an addition operation is performed and the Q
Addition/subtraction circuit 1 performs subtraction operation when processing a series.
8 multiplication circuit 16 controlled by word address WD
d (the interval of the Q sequence is (D-d) blocks,
In this example, it is multiplied by d=1).

Reference numeral 17 indicates a word counter, and the word counter 17 is supplied with a word clock and a load pulse from a control circuit 18. A word address ADW that changes sequentially is generated from the word counter 17, and this word address AD
W is supplied to the error word flip-flop 19 in parallel. The error word flip-flop 19 is supplied with an error pulse SE from the correction circuit 2, and the word address of the error word is read into the error word flip-flop 19 by this error pulse SH.

be included.

As shown in FIG. 5, the carry output of the word counter 17 converts data words DO to D3 in one series into data RA.
It becomes "0" during the period Ta of three clocks read from MI, and becomes "1" during the period Tb of the last l clock. The carry output of this word counter 17 is the switch circuit 4.
is supplied as a control signal to Also, word counter 1
The carry output of 7 is supplied to the control circuit 18, and
The carry output of the word counter 17 is supplied to one input terminal of an EX-OR gate (exclusive OR gate) 20. The switch circuit 4 has a period T for inspection.
Input terminal 5 and output terminal 7 are connected at point a, and input terminal 6 and output terminal 7 are connected at period Tb for correction.

A clock pulse and a load pulse are supplied from the control circuit 18 to the base counter 14 . The base counter 14 generates a base number indicating the number of the base series (0, 1, 2, . . . 24).

This base number is one input terminal 2 of the switch circuit 21.
2. The output of the addition/subtraction circuit 15 is supplied to the other input terminal 23 of the sui-nochi circuit 21 . The switch circuit 21 is controlled so that the input terminal 22 and the output terminal 24 are connected during the inspection period Ta, and the input terminal 23 and the output terminal 24 are connected during the correction period Tb.

The output of the switch circuit 21 is supplied to the base register 25 as an address input. As an address input to the pace register 25, one bit of the output of the EX-OR gate 20 is supplied. The output of this EX-OR gate 20 is used to specify the base, P sequence and Q sequence of the register 25.

The pace register 25 stores l-bit base flags for all bases of each of the P and Q sequences. EX
The -OR gate 20 is supplied with the carry output of the word counter 17 (see FIG. 5) and the control pulse SS from the control circuit 18.

This control pulse SS is “0” during processing regarding the P sequence.
”, and becomes “l” when processing the Q sequence. Therefore, when processing the P sequence, the output of the EX-OR gate 2o becomes "0" during the period Ta and "1" during the period Tb. On the other hand, when processing the Q sequence, it is “1” in the period Ta.
, becomes 0 in period Tb. This EX-OR gate 20
When the output of EX-OR gate 20 is "O", the P-series base flag of the pace register 25 is accessed, and when the output of the EX-OR gate 20 is "1", the Q-series base flag of the pace register 25 is accessed. That is, during the inspection period Ta during correction processing, the base flag of the own series is accessed, and during the correction period Tb, the base flag of another series is accessed.

The data input of the pace register 25 is fed through a switch circuit 26. During the inspection period Ta, a “0” bit is input via the switch circuit 26, and during the correction period T
At b, a bit of 1" is input via the switch circuit 26. The base flag read from the pace register 25 is supplied to the control circuit 18. Also, the write pulse of the pace register 25 causes the switch circuit 27 to be input. Supplied via

The switch circuit 27 is connected to the control circuit 1 during the inspection period Ta.
In the correction period Tb, the write pulse from the correction circuit 2 is selected. A write pulse from the control circuit 18 causes the pace register 2 to
When the base flag read from 5 is "1", a base flag of "0" is written, and when corrected by the write pulse from the correction circuit 2, a base flag of 'l' is written. It will be done.

The control circuit 18 includes the circuits 9 and 9 other than the circuit 4. Switch circuit 21. A control signal for controlling the switch circuit 26 and the switch circuit 27 and a control signal for the arithmetic operation of the addition/subtraction circuit 15 are generated.

Also, although not shown, II? 11 A correction operation start signal is input to the circuit 18, and a correction operation end signal generated by the control circuit 18 causes the input of the clock to the correction circuit 2 to be prohibited +h, the clock input to the word counter 17 to be prohibited +h, etc. An action is taken.

d. In both step ■ and step ■ of the operation correction method of a decoding device according to an embodiment,
According to the output signal shown in FIG. 5 from the word counter 17, the word address ADW, which is incremented around 1 (0° 1.2.3), is transferred to the data RAM 1 through the switch circuit 4 for the first four clocks. word address W
D, the data word and error flag are read.

The read data words and error flags are supplied to a correction circuit 2, where the number of error words in one series is checked. Also, in the last one clock, the switch circuit 4 is switched and the address of the error word latched by the error pulse SE is transferred to the error word flip-flop knob 19 as the word address WD.
1.

The correction circuit 2 counts the number of "1" (errors) in the error flag of the read data and generates correction data.If there is only one error word in one series, the correction circuit 2 The corrected data from 2 and the error flag of 0'' are written into the data RAM1.

When the correction process P1 in step ■ is performed,
As shown in FIG. 4, the input terminal 10 and output terminal 12 of the switch circuit 9 are connected, and from the control circuit IB to the EX-O
The control signal supplied to the R gate 20 is set to "0".

In this correction processing P1, the base counter 14 is incremented by I. each time one correction processing is completed. The output of the base counter 14 and the output of the multiplication circuit 13 are supplied to the addition circuit 3, and the output of the addition circuit 3 is sent to the block address B.
K is taken out. Therefore, base counter 1a is O
When starting from and incrementing to 24, correction processing is performed for all the P sequences. The block address for the P sequence is PBK, the data word number is Dn (0, 1, 2 or 3), and the base number is PBK.
Then, a block address PBK for each data word is generated according to the following equation.

PBK=PB■DXDn ---(1) (However, ■
means addition of (mod-, 25). ) Also, in the correction process Q1 of step (2), when generating block addresses QBK for all Q sequences, when the base number is QB, the block address QBK of each data word is generated.

Q B K = Q BθdxDn − (21((
8, and e means subtraction of (mod, 25). ) That is, in the correction process Q1, the input terminal 11 of the switch circuit 9
and output terminal 12 are connected.

In each of step ■ and step ■, correction processing P
1 and Ql are completed, the - and - flags of the own series are all "0", and the base flag of the other series that corresponds to the base of the next series to be corrected is '1'.
It has been cents.

Writing of this base flag is performed by the El-OR game 120.
and address from switch circuit 21 and switch circuit 2
6 and a write pulse from switch circuit 27.

In each process of step (2) and step (2), the block address BK formed in the same manner as described above is transferred to the data RAMI.
supplied to However, the base flag output from the base register 25 is supplied to the control circuit 18, and the control circuit 18 determines whether the base flag is "0" or "1".If the base flag is 0, the base counter 14
A clock is added to the base flag, and correction processing is performed only on the series whose base flag is 1'.

After step ■, when the final 24th base is reached, the control signal SS is inverted and the correction process is repeated starting from the first base if the correction process is performed even once. . On the other hand, if the correction is not made even once, the correction operation ends, the clock supply is stopped, and power consumption is saved.

e. Modification The present invention is directed to an error correction method in which a pointer whose error or correctness is undetermined is assigned, repeated correction processing is performed without determining whether the word of this pointer is an error or correctness, and finally this determination is made. It can also be applied.

Furthermore, in the present invention, it is not necessary to provide an error check code (CRC code) based on a sequence within a data block. The present invention can be similarly applied to cross-interleaved codes that are not block-contained.

Furthermore, this invention uses two in one sequence as an error correction code.
The same can be applied to the case where a code capable of correcting errors of one word or more is used.

〔Effect of the invention〕

The present invention provides that only for one series of cross-interleaved codes containing words corrected by the other series,
Perform the following correction process. Therefore, at the very least, it is possible to prevent wasteful correction processing from being performed on sequences in which the number of correct words has not increased. According to this invention, it is possible to improve the correction ability by performing more effective correction processing within a limited time. Also, according to this invention,
Power consumption of error correction circuits and the like can be reduced.

[Brief explanation of drawings]

Fig. 1 is a route map used to explain the code structure to which the present invention can be applied, Fig. 2 is a route map showing an example of the data structure on a tape during recording/reproduction, and Fig. 3 is a route map used to explain the code structure to which the present invention can be applied. FIG. 4 is a block diagram of an example of a decoding device used to implement the present invention, and FIG. 5 is a waveform diagram used to explain the operation of the decoding device. Explanation of main symbols in the drawings 1: Data RAM, 2: Correction circuit, 3: (m. d, 25) addition circuit, 13, 16: Multiplication circuit, 1
4: Base counter, 17: Word counter. Agent Patent Attorney Tadashi Sugiura Cross Interleave Figure 1 Error Tadashi Yoshicho's 14th row Figure 3 Figure 4

Claims (1)

Claims: A data word is formed by a predetermined number of bits of a digital signal, the predetermined number of the data words is a data block, and a first sequence and a second sequence are applied to a plurality of the data blocks. In an error correction method for decoding a data signal provided with an error correction code, the correction process of the first series is performed on all the data blocks, the data is corrected or the error pointer is rewritten, and the storing the second series including the data word in which the data has been corrected or the error pointer has been rewritten; and performing the correction process on the second series with respect to all the data blocks to correct the data. or rewriting the error pointer and storing the first series including the data word with the data corrected or the error pointer rewritten; and the stored second series. and a step of performing correction processing only on the stored first sequence.