JPS62120671A - Method for correcting error of data - Google Patents

Abstract

PURPOSE:To remove a useless data reading time by executing parity check only in a series having no error pointer. CONSTITUTION:At the execution of parity check, error correction is executed only for a series having one error pointer and parity check is executed only for a series having no error pointer. A detecting circuit 6 is turned on by a detection control circuit 14 in the 1st and 4th 123 series reading periods and a switch 9 is turned by the detecting circuits 6, 5 in accordance with the number of error pointers, i.e. '1' or '0', to execute parity check and error correction. In other periods, e.g. the 2nd, 3rd and 5th periods, the detecting circuit 6 is turned off and the switch 9 is turned to the contact (b) side to repeat the correction of the P and Q series alternately.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an error correction method for digital data such as digital audio signals.

[Summary of the invention]

In the case of performing a parity check and error correction using an error pointer, the present invention performs the error correction for a sequence in which the number of error pointers is one during the parity check, and also performs the error correction using the error pointer. By performing a parity check only on sequences that do not have a parity, it is possible to avoid wasting data read time.

[Conventional technology]

2. Description of the Related Art A VTR has been proposed in which, when recording and reproducing video and audio signals, the audio signal is converted into PCM and recorded at the time of recording. In such a VTR, a tape is wound around a drum at an angle greater than 1806, so that video signals and digital audio signals are recorded in predetermined areas of tracks formed diagonally on the tape. In that case, the digital audio signal is recorded in a data format using loss interleaving as shown in FIG. 4 to enable error correction. Furthermore, this figure 4 is for NTS
In the case of the C method, data written on the memory map for each field is shown.

The data is divided into 132 data blocks, each data block consists of a 3-bit synchronization signal, 5YNC, an 18-bit address signal, an 8-bit Q parity, 4 data words of 8 bits each, an 8-bit P parity, each 8
4 data words of bits and 16 bits 0CRCC
(error detection code). The above data word is
A user's word (control word) represented by IDo, IDI-----I D , and L
o Ro, L + R+ '-'-"---Ls
There are L channel and R channel words represented by za Rsza. The 132 data blocks are divided into groups of 44 blocks each.
The above user's word and R channel word are:
They are sequentially written to each group intermittently.

Error correction of data during playback is performed as follows.

In FIG. 5, white circles and black circles indicate P, Q parity and data words, each of 8 bits. Also 12
．． Numbers such as 14 and 15 indicate deviations of 12, 14, and 15 words, respectively. In this Figure 6,
A Q parity sequence and a P parity sequence with mutually different slopes are defined, and Q0 to QI3 . and P0 to P13. Error correction is performed for each series. In this case, since an error pointer detected by the CRCC is set in each data block, error correction is performed using the pointer laser method based on this error pointer. By repeating this error correction for Q correction and P correction, the error pointers are cleared one after another, and the amount of error data decreases. Such a data transmission system is disclosed in, for example, Japanese Patent Laid-Open No. 198935/1983.

The CRCC sets an error pointer to the data block where error data exists, but this CRCC
For example, the error detection ability of this method is almost perfect for burst errors of 16 bits or less and random errors of 3 bits or 7 bits or less, but there is a possibility of false detection for errors exceeding this.

That is, an error pointer may not be set for a data block in which an error exists. If no compensation is made for such erroneous detection, scratch noise will occur. Furthermore, if correction processing is performed using this erroneous data, erroneous correction will occur and the erroneous data will further expand.

In order to solve this problem, we have traditionally
Error correction methods disclosed in Japanese Patent Application Laid-open No. 964 and Japanese Patent Application Laid-Open No. 60-52965 have been proposed. In this method, a parity check is performed using Q parity or P parity before performing error correction processing.

[Problems to be solved by the invention] In the conventional method described above, a parity check is performed before error correction processing, but the parity check
Since we check whether the syndrome becomes zero when there are no errors in one series, parity checking is possible only when there are no error pointers for one series, and error pointers If there is even one, parity check becomes impossible. If this parity check is not possible, the time required to read the series is completely wasted time. In the case of the above-mentioned VTR, it is necessary to correct as many erroneous data as possible by performing correction processing as many times as possible between fields. This will significantly impede efficiency.

[Means for solving problems]

In the present invention, when performing the parity check, the error correction is performed for the series in which the number of error pointers is 1, and the parity check is performed only for the series in which there is no error pointer. There is.

[Effect]

When performing a parity check, if a correction process can be performed, it is corrected at that time, so the above-mentioned wasted time does not occur.

〔Example〕

In this embodiment, when performing a parity check before error correction processing, the parity check is performed when the number of error pointers in one series is 0, and when there is only one error pointer, the parity check is performed. Error correction processing is performed based on the pointer. By doing so, the above-mentioned wasted time can be eliminated.

FIG. 1 shows an embodiment of a circuit for performing the above-mentioned error correction.

In Figure 1, 1 is a control circuit that controls the overall operation timing, 2 is an address generation circuit that generates addresses according to each series, 3 is a memory in which data and error pointers are written, and 4 is an error pointer counter. , memory 3
The error pointer existing in one series read from the 1 series is counted, and is reset by a signal given from the control circuit 1 every time the reading of the 1 series is completed. 5
is a detection circuit that detects that the number of error pointers in one series counted by the counter 4 is one; 6 is a detection circuit that detects that the number of error pointers is zero; 8 is a switch control circuit; Upon detection by the detection circuit 5, the switch 9 is closed to the parity check side contact a,
Upon detection by the detection circuit 6, the switch 9 is closed to the correction processing side contact. 10 is a circuit that performs a parity check on data read from the memory 3, and 11 is a circuit that performs a correction process on the data. A repetition counter 12 counts a signal given from the control circuit 1 as a clock each time reading of the 132 series is completed. 13 is a decoder for the count value of the counter 12, and 14 is a circuit for controlling the detection operation of the detection circuit 6, which is used to determine when to perform both the parity check and the correction process based on the counter 12. It is. 15 is an input terminal for data and error pointer. The memory 3 includes the input terminal 15 and the circuit 10.
．． Data from 11 is written and read based on the address generated by address generation circuit 2.

Figure 2 shows the timing chart of Figure 1.
As an example, a parity check is performed at the same time as the fourth and fourth correction processes. That is, during the first and fourth 132-series read periods, the detection circuit 6 is turned on by the detection control circuit 14, and the detection circuit 6 and the detection circuit 5 are turned on.
Accordingly, the parity check and correction process are performed by switching the switch 9 depending on whether the number of error pointers is one or zero. Also other 2.3.5
...--In the first period, the detection circuit 6 is turned OFF, the switch 9 is fixed to the contact side, and the correction of the P sequence and the Q sequence is repeated alternately. That's what I do.

As mentioned above, the correction ability increases by repeating the correction of the P sequence and Q sequence, but in general, the closer to the beginning of the repetition, the greater the number of data to be corrected, and as the correction progresses, the number of data to be corrected decreases. go. That is, in the initial stage, the number of data to be corrected in the correction process is large, and this means that in the initial stage, in a sequence with one or more error pointers (a sequence in which parity cannot be checked), there is only one error pointer. In other words, there are many cases where correction is possible. Therefore, instead of performing the parity check for all 32 series as in the past, if the parity check is also performed during the first correction process as in this embodiment, the above-mentioned wasted time can be eliminated and the correction You can use your time effectively and increase the number of times corrections are repeated.

FIG. 3 is a flowchart showing operations within one series.

In FIG. 3, the number of error pointers is counted from one series of data read from memory 3, and when there is one error pointer, correction processing is performed based on that error pointer, and then the next series Read out. If there is no error pointer, perform a parity check. Note that when there are two or more error pointers, neither parity check nor correction is possible, so in that case nothing is done and the process proceeds to the next series.

〔Effect of the invention〕

When performing a parity check, if there is only one error pointer, correction processing is performed immediately, so no memory read time is wasted. Therefore, it is possible to increase the number of repetitions of the correction process and perform more efficient error correction.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a circuit for implementing the method of the present invention, FIG. 2 is a timing chart of FIG. 1,
FIG. 3 is a flowchart of FIG. 1, FIG. 4 is a diagram showing a data format to which the present invention can be applied, and FIG. 5 is a diagram showing a P sequence and a Q sequence. In addition, in the symbols used in the drawings, 3.
−・−・・−・−・−−−−One error detection circuit 6−
・−・−・−−−−1=−Error-free detection circuit 9−・−
...−・・−・・−Switch 10−・−−−1−−−
−・−Correction processing circuit 11・−・−1−−−～−−−・・
This is a parity check circuit.

Claims (1)

[Claims] In a data error correction method that performs a parity check and error correction using an error pointer, when performing the parity check, a series in which the number of error pointers is one is present. A data error correction method characterized in that the above error correction is performed for the above, and a parity check is performed only for the series without the above error pointer.