JPS62133547A - Memory error correcting circuit - Google Patents

Abstract

PURPOSE:To execute an operation at high speed by constituting a memory circuit of two circuits, and operating the read/write modes of its two circuits so that they become opposite to each other. CONSTITUTION:The address signal of an address generating circuit 3 is counted up at every one clock period, and supplied to the first and the second memory circuits 1, 2. Also, a read/write signal (c) and a read/write signal (d) which are outputted from a read/write control circuit 4 are supplied to the memory circuit 1 and the memory circuit 2, respectively. In this case, a control is executed so that when the memory circuit 1 is read (or write), the memory circuit 2 becomes a write (or read) mode. Also, switching to the write mode from the read mode and vice versa are executed after the address generating circuit 3 completes the scanning of all addresses of the memory circuits.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a memory error correction circuit, and particularly to a memory error correction circuit that requires high-speed operation when rewriting a memory using corrected data. It is related to.

[Conventional technology]

An example of a conventional memory error correction circuit of this type is shown in FIG. 3. In the figure, 11 is a random access type memory circuit, 12 is an address generation circuit for supplying address data to the memory circuit 11, 13 is a decoding circuit for decoding the error correction signal output from the memory circuit 11; 14 is a latch circuit for temporarily holding the output of this decoding circuit 13; 15 is this latch circuit 1.
An encoding circuit 16 generates a correct error correction code from the data latched again and supplies it to the memory circuit 11. A read/write circuit 16 controls the operation mode of the memory circuit 11 to be set to read mode or write mode. This is a light control circuit.

Then, after periodically and repeatedly reading out the data stored in the memory circuit 11 in the form encoded with the error correction code, the error correction code is decoded by the decoding circuit 13 into data before error correction encoding, and then decoded. At the same time as outputting data, if there is a correctable error in the read error correction code, the correct error correction code is reproduced and rewritten in the memory circuit 11.

The operation of the memory error correction circuit configured as described above will be explained with reference to FIG.

This Figure 4 shows the operating waveforms of the main parts of the circuit shown in Figure 3, where (a) shows the clock signal, (b) the address signal, (e) the read/write signal, ( d) shows the output data.

First, the address signal shown in FIG. 4(b) shows the output of the address generation circuit 12, and is configured so that a different address is output every two clocks. Further, the read/write signal C shown in FIG. 4(e) is the output of the read/write control circuit 16, and is set by switching between a read mode and a write mode every clock. Therefore, data is read from the memory circuit 11 during the first half clock period of the two clock period in which the address signal is kept constant, and data is written to the memory circuit 11 during the second half clock period.

In this circuit, if there is an error in the data stored in the memory circuit 11, the decoding circuit 13 corrects the error and outputs correct data. Further, this correct data is again encoded into a correct error correction code and written into the memory circuit 11 during the next write mode clock period.

In this way, by using the circuit shown in FIG. 3, correct data can always be held in the memory circuit 11.

[Problem that the invention seeks to solve]

In the above-mentioned conventional memory error correction circuit, data reading and writing are performed alternately, so the data reading cycle is equal to the time required for memory reading or writing operations, the so-called memory access time α. The drawbacks were that it required twice as much time and that high-speed operation was difficult.

[Failure to solve the problem]

A memory error correction circuit according to the present invention is connected to a first memory circuit, a second memory circuit, and data output lines of the first and second memory circuits.

A data output line switching circuit that selects and outputs one of both data lines, and +i4b connected to this data output line switching circuit.
a decoding circuit for decoding the correction code and outputting the decoded data; an encoding circuit connected to this decoding circuit for converting the decoded data into an error correction code and outputting it; a data input line switching circuit for switching and connecting to the data input line of the first or second memory circuit; and switching the read/write mode of the first memory circuit and the second memory circuit and the data output line switching circuit; Lead/lead for controlling the circuit and data input line switching circuit
a write control circuit; and an address generation circuit for supplying address data to the first and second memory circuits, when the first memory circuit is in a read mode (write mode), the second memory circuit The circuit is in light mode (
read mode), the data output line switching circuit selects the data output line of the first (second) memory circuit,
The data input line switching circuit is configured to switch to select the data input line of the second (first) memory circuit.

[Effect]

In the present invention, two memory circuits are provided, and the read/write modes of the two circuits are operated in opposite directions.

〔Example〕

Embodiments of the present invention will be described in detail below based on the drawings.

FIG. 1 is a block diagram showing an embodiment of a memory error correction circuit according to the present invention, and only the parts necessary for explanation are shown.

In the figure, 1 is a first memory circuit, 2 is a second memory circuit, 3 is an address generation circuit for supplying address data to the first and second memory circuits 1 and 2, respectively, and 4 is a first memory circuit. The operations of the second memory circuits 1 and 2 are such that when the first memory circuit 1 is in the read mode, the second memory circuit 2 is in the write mode, and when the first memory circuit 1 is in the write mode, the second memory circuit 2 is in the write mode. A read/write control circuit 5 is connected to the data output lines of the first and second memory circuits 1 and 2 and is connected to both data lines. The output of a data output line switching circuit that selects and outputs one of the two and an encoding circuit (to be described later) is sent to the first or second memory circuit 1 or 2.
A data input/output line switching circuit 6 is connected to the data output line switching circuit of the data input/output line switching circuit 5 to decode the error 9 correction code. A decoding circuit 7 is connected to the decoding circuit 6 and is an encoding circuit that converts the decoded data into an error correction code and outputs it.

Therefore, the data input/output line switching circuit 5 selects the output data of the memory circuit in the read mode state from among the first or second memory circuits 1 and 2 and supplies it to the decoding circuit 6. , is configured to supply the output from the encoding circuit 7 to the memory circuit in the write mode state.

Next, the operation of the embodiment shown in FIG. 1 will be explained with reference to FIG. 2.

This FIG. 2 shows the operating waveforms of the main parts of the circuit shown in FIG. 1, and (i) shows the clock signal a, C1 (
b) is the address signal b, (e) is the read/write signal e supplied to the first memory circuit 1, and (d) is the read/write signal d supplied to the second memory circuit 2.
, (e) shows the output data phrase.

The address signal shown in FIG. 2(b) is the output of the address generation circuit 3, but is counted up every clock cycle and supplied to the first and second memory circuits 1.2. , Fig. 2 (c), (d) K f')
)''/write signal C (memorina 1) and read/write signal d (memorina 2) are read/write control circuit 4.
The read/write signal C is supplied to the first memory circuit 1, and the read/write signal d is supplied to the second memory circuit 2. Here, when the first memory circuit 1 is reading (writing), the second memory circuit 2 is writing (writing).
read) mode. Further, the switching from the read mode to the write mode or vice versa is configured to be performed after the address generation circuit 3 finishes scanning all the addresses of the memory circuit.

Therefore, in the first scan, the first memory circuit 1
If data is being read from the second
Correct error-correction encoded data is written in the memory circuit 2 of .

Next, when the first scan is completed, data reading from the second memory circuit 2 begins, but this data is newly written during the first scan, and any errors have occurred since then. Correct data will be output as long as it does not occur. In addition, even if an error occurs, the key υ is that the error υ is a correctable error υ.
The data is corrected and then written to the first memory circuit 1 as correct data.

In this way, by having two memory circuits and using the memories alternately, correct data can always be held in both memories. Furthermore, the data read cycle is one clock cycle, which can be reduced to the memory access time.

〔Effect of the invention〕

As explained above, according to the present invention, the memory circuit can be
By operating the read/write modes of the two circuits in opposite directions, the data read cycle can be reduced to one clock cycle, which is half the conventional rate, achieving high-speed operation. Therefore, the practical effect is extremely large.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the memory error correction circuit according to the present invention, FIG. 2 is a waveform diagram showing operation waveforms of the main parts used to explain the operation of FIG. 1, and FIG. 3 is a conventional memory error correction circuit. FIG. 4 is a block diagram showing an example of a correction circuit, and FIG. 4 is a waveform diagram showing operating waveforms of main parts to explain the operation of FIG. 3. l, 2 @ II 111 + memory circuit, 3 @...
- Address generation circuit, 4... ψ read/write control circuit, 5... data input/output line switching circuit, 6... decoding circuit, T... encoding circuit.

Claims (1)

[Claims] After periodically and repeatedly reading data stored in a memory circuit in a form encoded with an error correction code, decoding the error correction code into data before error correction encoding and outputting the same as decoded data, A memory error correction circuit that reproduces a correct error correction code and rewrites it into the memory circuit when there is a correctable error in the read error correction code, a first memory circuit;
a second memory circuit; a data output line switching circuit that is connected to the data output lines of the first and second memory circuits and selects and outputs one of both data lines; and a data output line switching circuit that is connected to the data output line switching circuit. a decoding circuit for decoding the error correction code and outputting decoded data; an encoding circuit connected to this decoding circuit for converting the decoded data into an error correction code and outputting the same; a data input line switching circuit for switching and connecting to the data input line of the first or second memory circuit; a read/write mode of the first memory circuit and the second memory circuit; and switching of the data output line. A read/write control circuit for controlling the circuit and a data input line switching circuit, and an address generation circuit for supplying address data to the first memory circuit and the second memory circuit, When the memory circuit is in a read mode (write mode), the second memory circuit is in a write mode (read mode), and the data output line switching circuit selects the data output line of the first (second) memory circuit. , wherein the data input line switching circuit is configured to be able to switch to select the data input line of the second (first) memory circuit.