JPH0233330Y2 - - Google Patents

Description

[Detailed explanation of the invention] [Industrial application field] This invention is applicable to 800RPI NRZI, 1600RPI, PE
and 6250RPI GCR, which modulates three types of modulation methods using a common modulation circuit.

[Conventional technology]

When the data to be written on the magnetic tape is transferred from the channel to the buffer memory of the magnetic tape controller, the data is transferred at 6250 RPI (Row Per,
In the GCR (Group Coded Recording) recording method, 1 byte is recorded in units of 7 bytes.
After adding ECC (Error Correcting Code) 4
Data is converted from bit to 5 bits, and NRZI (Nonreturn to
The data is modulated using the Zero Change on Ones (Zero Change on Ones) method, a postamble, preamble, etc. are added, and the data is transferred to the magnetic tape unit MTU and written onto the magnetic tape by the write head. When writing,
To indicate that it is a GCR method of 6250RPI,
A 6250RPI recording density indicator is recorded near the BOT (Beginning of tape) marker at the beginning of the tape, followed by an ARA for adjusting the amplification degree of the reading circuit.
Signal (Automatic Read Amplification Burst)
Record.

In addition, in the 1600RPI PE (Phase, Encoding) and 800RPI NRNI methods, when write data is transferred from the channel to the buffer memory of the controller, it is phase modulated or NRZI modulated by the modulation circuit and sent to the magnetic tape device. .
When writing, at 1600RPI recording density, loading and
Distinguish it from 800RPI tape by writing a recording density indicator near the point. Also,
In the 1600 RPI data block configuration, a preamble and postamble are written before and after the data byte, while in the 800 RPI data block configuration, the CRC byte and LRC byte are written after the data.

Like this, 6250RPI (GCR) and 1600RPI (PE)
Since each modulation circuit based on 800RPI (NRZI) and 800RPI has different write processing and writing style, three types of hardware must be installed, which is extremely uneconomical.

[Problem that the invention attempts to solve]

The purpose of this invention is to solve this problem,
An object of the present invention is to provide a modulation circuit that can create write data using the same circuit for three types of modulation methods.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a modulation circuit showing an embodiment of the present invention.

The modulation circuit of the present invention includes a first register having a 4-bit area for setting i-bit write data BITi and write format instruction signal FRM in synchronization with clock _CLK1 .
REG1, convert 4 bit data to 5 bits,
Or diagnostic mode data write instruction signal
Create defective data by changing the content to be converted by DMW, or use the inverted write instruction signal INV,
1600RPI mode instruction signal M1600, 800RPI mode instruction signal M800, format write instruction signal
A PROM generates a data pattern specified by inputting FRMW, etc., and the generated data is transferred to a second register set by clock CLK ₂ and parallel load instruction WTCTL.
Register REG ₂ by REG ₂ and clock CLK ₃
A data modulation system consists of flip-flop FF ₁ that creates a modulated write signal WTDi from the output of the checker CHK, which performs a parity check by inputting the modulated write signals WTD ₀ to ₈ , and flip-flop FF _2. -Equipped with a 6250RPI signal check system consisting of FF ₃ and exclusive OR gates EOR ₁ and ₂ . The clock CLK ₃ is constantly supplied here, and when the output of the second register REG ₂ becomes "1", the output of the flip-flop FF ₁ is inverted. In FIG. 1, only one track of the data writing system is shown.

Figure 2 shows 6250RPI modulation operation, Figure 3 shows
Figure 4 is a time chart showing a modulation operation of 1600RPI and a modulation operation of 800RPI.

At 6250RPI, 4 bits are converted to 5 bits, so extra processing is required.

As shown in FIG. 1, the first register REG ₁ is supplied with a format code FRM representing the type of format pattern or write data Di (DTA, BITi) supplied from the host device.

As shown in Figure 2, at 6250 RPI, the format code input signal FRMS (see also Figure 1) becomes "1", and the format code FRM (F ₀ , F ₁ , F ₂ , F ₃ ) are loaded in parallel into each cell of the first register REG ₁ . Also, write data given from the host device
Di (D ₀ , D ₁ , D ₂ , D ₃ ) is serially set in the cells of the first register REG ₁ in synchronization with the clock CLK ₁ .

Now, the 4 bits of format code FRM
F ₀ , F ₁ , F ₂ , and F ₃ are read into the PROM, and this is converted into write patterns f ₀ to f ₄ (5 bits) corresponding to the above format codes F ₀ to F ₃ (4 bits). , are loaded in parallel into the second register REG ₂ in synchronization with the parallel load instruction WTCTL.

After that, the contents of register REG ₂ in Figure 2 are shifted in synchronization with clock CLK ₂ , and the write pattern is
_f4 to _f0 are sequentially supplied to flip-flop _FF1 to create write data WTDi. In addition, the light
When the first 4 bits D ₀ to D ₃ of the data Di are arranged in the first register REG ₁ , they are read out and
Enter the PROM and write the corresponding 5-bit
The signals are converted into patterns d ₀ to _{d 4} and loaded in parallel into the second register REG ₂ in synchronization with the parallel load instruction WTCTL.

As before, the contents of the second register REG ₂ are shifted in synchronization with clock CLK ₂ , and bits d ₀ to d ₄ forming the write pattern are sequentially flipped.
Feeds to flop FF ₁ and creates WTDi.

During data writing, clock CLK ₁ is output 4 times and then 1
Suspends production.

Thereafter, write data D ₄ - are processed in the same manner. .

Next, write instruction signal DMW in diagnostic mode is
When given to PROM, inverted write instruction signal
In combination with INVi, the content converted by PROM is changed appropriately and defective data is output.

Next, in the case of 1600RPI, the clock CLK ₁ ,
CLK ₃ and parallel load indication signal WTCTL
The timing can be changed slightly. and,
1600RPI mode indication signal M1600 for PROM
As shown in FIG. 3, the write data Ai (i=0,
1, 2, 3...) are serially set in the first register _REG1 in synchronization with the clock _CLK1 .
When the write data Ai is set in the first register REG ₁ , the PROM reads the write data Ai.
In response to this, data ai and phase bit a′i indicating the magnetization reversal of the corresponding data are generated. The generated data ai, a'i are set in the second register REG ₂ in synchronization with the parallel load command WTCTL.

Thereafter, the contents of the second register REG ₂ are shifted and sequentially supplied to the flip-flop FF ₁ in synchronization with the clock CLK ₃ as in FIG. 2, thereby creating write data WTDi.

In the above, when converting data to create phase bit a'i, the previous data A _i-1 set in the first register REG ₁ is referred to.

In the PE method, depending on the direction of magnetization reversal, for example, "1" is written with upward magnetization and "0" with downward magnetization, but when "1" or "0" are consecutive,
During this time, it is necessary to reverse the magnetic flux once again. Data a′ ₀ for this phase bit,
A′ ₁ and a′ ₂ are set in parallel in register REG ₂ by clock CLK ₂ and parallel set instruction signal WTCTL, and clock CLK ₃ applied to flip-flop FF ₁ can be added at the timing when different from the previous one. However, when the data is the same, it is added at that timing to invert it and create modulated write data WTDi.

When the write instruction signal DMW in the diagnostic mode is applied to the PROM, various types of defective data are output, such as data with no phase inversion at all or data with phase inversion inserted between different data.

Then for 800RPI, for PROM
By giving the 800RPI mode instruction M800, the clock CLK ₁ register is set as shown in Figure 4.
The write data A ₀ to _{A 4} set in REG ₁ are
It is directly set in register REG ₂ by clock CLK ₂ and parallel load instruction WTCTL, and becomes modulation data a ₀ to a ₄ . In the NRZI method,
The write current can be reversed when it is “1” and maintained as it is when it is “0”, so the data
If the clock _CLK3 is applied to the flip-flop _FF1 only when _a0 to _a4 are "1", the write data WTDi modulated by the NRZI method is output from the flip-flop _FF1 .

On the other hand, the write instruction DMW in diagnostic mode is
When applied to the PROM, defective data such as inversion when it is "0" is output.

Next, in the 6250RPI/GCR method, when checking the signal after modulation, the data sub-
The sum of the parities of tracks 0 to 8 of the group is
By checking whether the first and last of the group match, it is determined whether the modulated signal is normal or abnormal.

In the 6250RPI/GCR method, a 4-bit data sub-group is converted to 5 bits, and the write current is reversed when the information is "1" and the state is maintained when the information is "0". Even if the current is at a high level at the beginning of a sub-group, the last level of the 5 bits will be the same high level or the opposite low level depending on the number of "1"s. Therefore, if the sum of the parities for 9 tracks is taken from the beginning to the end of the data sub-group, depending on the nature of the data sub-group, the first parity and the last parity may be the same, or It's going to be different.

The data sub-group contains write data and format data, so the PROM
These types are sent to the check system exclusive OR gate EOR ₁ to correct the initial parity.

First, when the modulated write signal WTDi is input to the parity checker CHK, the parity checker CHK checks the data in tracks 0 to 8.
Take the sum of the first parities of the sub-groups,
For example, when the number is odd, "1" is stored in the flip-flop FF2, and when the number is even, "0" is stored in the flip-flop _FF2 . and,
Depending on whether the data is from PROM or the format, the output of exclusive OR gate EOR ₁ is output as is for data group, reciprocal group and CRC group, and as is for sync, mark, mark and end mark. is reversed.

Next, at Paritei Chietska CHK, 0
The sum of the last parities of the data sub-groups in ~8 tracks is taken, and an inverted output, for example "0" for an odd number and "1" for an even number, is sent to the exclusive OR gate EOR ₂ . The exclusive OR gate EOR ₂ takes the exclusive OR of the first parity and the last parity of the data sub-group and sets the flip-flop FF ₃ with an output "1" to give an error output ERR. . In this case, an error can occur either when the first and last parities of the group are the same, or when they are different.

In this manner, by performing the first and last parity checks, it is possible to determine whether data modulation has been performed correctly.

[Effect of idea]

As explained above, according to the present invention,
Since the pattern generated from the PROM and the clock output are changed, three types of modulation are possible with the same modulation circuit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a modulation circuit showing an embodiment of the present invention, and FIGS.
This is a time chart showing the modulation operations of 6250RPI, 1600RPI, and 800RPI in the figure. REG ₁ , ₂ ...Register, PROM...Programmable read-only memory, FF ₁ , ₂ , ₃ ...Flip-flop, EOR ₁ , ₂ ...Exclusive OR gate, CHK...Parity checker, ERR...
Error display signal, WTDi...Modulated write signal bit i, WTCTL...Parallel load instruction signal, FRMW...Format write instruction signal,
INVi...Inverted write instruction signal, FRM...Write format instruction signal, BITi...i bit write data, CLK ₁ , ₂ , ₃ ...Clock signal,
M1600...1600RPI mode instruction signal, M800...
800PRPI mode instruction signal.

Claims (1)

[Claims for Utility Model Registration] A modulation circuit for a magnetic tape device operating with GCR, PE and NRZI modulation methods, comprising a 4-bit first register for temporarily storing input data to be modulated; Data is input from register 1,
and a PROM that receives a modulation mode instruction and converts input data into modulation data determined by the modulation mode instruction; and 5 that temporarily stores the modulation data from the PROM.
a second register of bits; and receiving data from the second register;
The PROM is equipped with a modulation circuit that performs modulation using the NRZI modulation method, and when GCR mode is specified as the modulation mode, the PROM uses the 4-bit data stored in the first register as an address and transfers the 5-bit data to the Second
When PE mode is specified as the modulation mode, outputs 2-bit data to the second register using the 2-bit data stored in the first register as an address. and when the NRZI mode is instructed as the modulation mode, the 1-bit data stored in the first register is used as an address, and 1-bit data is output to the second register and set. A modulation circuit characterized by: