JPS6232824B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to error control schemes for data storage devices, particularly mass storage devices.

FIG. 1 shows the format of a magnetic tape used in a mass storage device with a rotating head and performing diagonal scanning.

In the figure, reference numeral 1 indicates an identification track for recording an identification code of a stripe described later; reference numerals 2, 3, 5 and 6 indicate servo signal tracks used for positioning the magnetic tape; and reference numeral 4 indicates a data stripe for recording data. There are 13,544 data stripes, and each stripe can store 4K bytes of data.

FIG. 2 shows the bit structure of the stripe.
One stripe is a 16-byte burst signal (BS),
It consists of a 2-byte beginning mark (BM) and 20 segments. Each segment consists of 15 sections, and each section consists of 16 bytes. Each segment is provided with two types of error correction codes (ECC1 and ECC2) for correcting data in each segment, and the 20th segment is equipped with an error correction code for error detection by redundancy check on data of one stripe. A cyclic code is provided.

In such a large capacity storage device using magnetic tape, data error control has conventionally been performed using a readout circuit as illustrated in FIG.

In FIG. 3, 11 is a decoding circuit that decodes data read by a magnetic head (not shown), and 12 is an error correction circuit that detects and corrects decoded errors using error correction codes (ECC1 and ECC2). , 13 is an input side selection circuit for sending the output of the decoding circuit 11 and the output of the error correction circuit 12 to either of the two segment buffers described later, and 14 is a first segment buffer that temporarily stores data for each segment. Buffer 15 is also a second segment buffer; 16 is an output side selection circuit which selects the outputs of the first segment buffer 14 and the second segment buffer 15 and sends them to the read register or error correction circuit described later; 17
18 is a read register that temporarily stores the output data of the output side selection circuit 16, and 18 is a redundancy check using a cyclic code, that is, a cyclic redundancy check (CRC) to detect errors in data of one stripe.
This is a CRC check circuit.

FIG. 4 is a time chart of data error control in the readout circuit of FIG. , and D indicates the storage content of the read register 17. SEG1 is the sequence in which the data of the first segment is output or stored.
SEG1ECC indicates the sequence in which error correction is performed on the data of the first segment.
(same as below). Further, 1, 2, . . . , 22 indicate sequence numbers.

That is, the output of the decoding circuit 11 is alternately stored in the first segment buffer 14 and the second segment buffer 15 by the input side selection circuit 13. First, the data of the first segment is transmitted from the decoding circuit 11 to the selection circuit 13 and then to the first segment.
is stored in the segment buffer 14 of. At the same time, the error correction circuit 12 detects an error in that segment. If there is an error in the data of this first segment, the next second segment
Using the sequence, the data of the segment is fed back to the error correction circuit 12 and error correction is performed.

Meanwhile, in this second time sequence, the data of the second segment is stored in the second segment buffer 15. Subsequently, in the third time sequence, the data of the first segment after error correction is sent from the first segment buffer 14 to the read register 17 via the output side selection circuit 16, and the data of the third segment is sent out from the first segment buffer 14 to the read register 17. It is stored in the segment buffer 14.

The process continues in the same manner up to the 20th segment data. During this time, the CRC check circuit 18
performs error detection for the entire data of one stripe. Therefore, the CRC check circuit 18
The error detection is completed by the decoding circuit 11.
is two time sequences after decoding the data of the last or 20th segment of the stripe.

Data transfer in such a mass storage device is performed as follows.

When executing a data write command, the stripe identification code recorded on the identification track 1 of the magnetic tape is first read for each stripe, and after this is confirmed, data is written to the data stripe 4. At this time, the read circuit shown in FIG. 3 reads the written data and performs error control. Thereafter, the magnetic tape is fed in steps by one stripe, the next stripe identification code is read, and data writing and error control are performed in the same manner. (See FIG. 6) When a data read command is executed, the data recorded on the data stripe 4 of the magnetic tape is read and error control is performed, but the stripe identification code is not read.

By the way, one way to increase the data transfer speed is to increase the rotation speed of the rotating head to increase the data writing and reading speed. The time it takes to step to a stripe must be shortened accordingly. In this way, there is a relatively large amount of time when executing a data read command, but when executing a data write command, the stripe identification code must be read, so there is a relatively large amount of time when executing a data write command. This makes it difficult to increase the rotational speed of the rotating head to increase the data transfer rate.

The present invention was made to solve such problems, and in order to increase the data transfer speed by increasing the rotation speed of the rotary head, the data error control time is shortened. ,
The purpose is to provide more time for step feeding of magnetic tape.

That is, the present invention switches the data input path for the cyclic redundancy check performed on the entire data of one stripe depending on whether the data storage device is executing a write command or a read command. and when a write command is being executed, when storing data in the first segment buffer or the second segment buffer,
At the same time, by performing error detection by the CRC check circuit 18, the end time of error detection is brought forward.
This provides ample time for stepping the magnetic tape when executing a write command.

Hereinafter, the main points of the present invention will be specifically explained using the embodiment shown in FIG.

In FIG. 5, the symbols used in FIG. 3 are applied as they are. A CRC check signal selection circuit 19 selects either the output of the decoding circuit 11 or the output of the read register 17 and supplies the selected signal to the CRC check circuit 18.

When executing a data read command, the data storage device needs to guarantee the read data to the data transfer destination. Therefore, error detection by the CRC check circuit 18 is performed immediately before data transfer as in the conventional case. Therefore, the CRC check signal selection circuit 19 selects the output of the read register 17 and supplies it to the CRC check circuit 18.

Furthermore, when executing a data write command, the data storage device only needs to guarantee the written data, so error detection by the CRC check circuit 18 is performed on the output of the read register 17 as in the conventional case. It is not necessary and may be performed when sending the read data to the first segment buffer 14 or the second segment buffer 15. Therefore, the CRC check signal selection circuit 19 selects the output of the decoding circuit 11 and performs the CRC check signal selection circuit 19.
Supplied to check circuit 18. In this way, the data of the last segment of the stripe, that is, the 20th segment, will be transferred to the second segment buffer 1.
5, the CRC check circuit 18 can complete error detection for the data of the entire stripe. When a write command is executed, error correction using an error correction code is not performed, so this is the end of error control. That is, error control is completed two time sequences earlier than in the conventional example.

In the above embodiment, one CRC check circuit is provided, but the object of the present invention can also be achieved by separately providing a dedicated CRC check circuit for executing a write command. .

As explained above, according to the present invention, data error control for each stripe can be completed quickly when executing a data write command, so the time margin required for step feeding of the magnetic tape can be increased accordingly. I can do it. This allows the rotation speed of the rotary head to be increased and the data transfer rate to be increased.

Furthermore, although a step-feeding type device has been described, it is clear that the effects of the present invention are not dependent on the tape feeding method.

[Brief explanation of the drawing]

Fig. 1 shows the format of the magnetic tape used in the mass storage device according to the present invention, Fig. 2 shows the data structure of one stripe, Fig. 3 shows a conventional example of a reading circuit, and Fig. 4 shows a data error control time chart. FIG. 5 shows an embodiment of a reading circuit according to the present invention. 3 and 5, 11 is a decoding circuit, 12 is an error correction circuit, 14 is a first segment buffer, 15 is a second segment buffer, 17 is a read register, and 18 is a
CRC check circuit 19 is a CRC check signal selection circuit. Figure 6 shows the data as seen from the read head.

Claims (1)

[Claims] 1. Data is divided into segments, an error correction code is attached to each segment, and a cyclic code is attached to each predetermined number of segments for writing and reading, and error correction is performed using the error correction code. An error correction circuit 12, a CRC check circuit 18 that performs a redundancy check using a cyclic code, and a plurality of segment buffers 14 and 15 that temporarily store the data before or after the error correction in units of the segments are provided. In a data storage device that performs error correction for each segment and redundancy check for each of the predetermined number of segments, the data input path to the CRC check circuit 18 is switched depending on data write operation and read operation. A selection circuit 19 is provided to select the error-corrected data during read operation.
By supplying input data to the CRC check circuit 18, and directly supplying the input data to the segment buffers 14 and 15 to the CRC check circuit 18 during a write operation, the error control time to be performed for each predetermined number of segments during a write operation can be reduced. A data storage device error control method characterized in that it is shortened.