JP2604713B2 - Error correction method - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error correction method used for an audio PCM signal recording / reproducing apparatus, a digital audio disk, and the like.

[Summary of the Invention]

The present invention relates to an error correction method for decoding a data signal in which an error correction code is provided by a first sequence and a second sequence for a plurality of data words formed by a predetermined number of bits. By performing correction processing only on the other series including the data word corrected by one of the series and the second series in a chain,
Correction processing for a series in which correct words are not increased is prevented, and only effective correction processing can be performed.

[Conventional technology]

When a digital audio signal is recorded on a magnetic tape or the like, a cross interleave code is used as an error correction code. The cross interleave code is used for a plurality of data blocks consisting of a predetermined number of data words, for a first sequence (referred to as a P sequence) and a second sequence (Q sequence).
An error correction code is provided for the P sequence, and the correction process for the Q sequence is repeated.

Decoding of the conventional cross-interleave code is performed by correcting a P sequence performed a plurality of times and Q processing performed a plurality of times.
In each processing of the correction processing for the series, the correction processing has been performed for all the series. The correction process is performed by storing the received (or reproduced) data in a memory, reading out the words in one sequence in order from the memory, and supplying the words to an error correction circuit. When a simple parity code is used as the error correction code, the error word can be corrected only when the number of error words in one sequence is one.

[Problems to be solved by the invention]

If two or more error words are included in one sequence read from the memory for error correction, error correction becomes impossible with a simple parity code. Therefore, the time required for this series of processing and the power consumed by the memory, the error correction circuit, and the like are completely wasted. Further, the time that can be used for the error correction processing is usually limited to a predetermined time. Therefore, if there is a large amount of useless time as described above, the number of words that can be corrected decreases, and the correction capability decreases.

A sequence that has been corrected at least once is either a state in which there is no error word or a state in which error words are so many that they cannot be corrected. Therefore, for a sequence that has been corrected at least once, the possibility that a valid correction process can be performed thereafter is limited only after an error word in this sequence has been corrected by another sequence. Therefore, the present invention performs the following correction processing only on a Q (or P) sequence including a word corrected by a P (or Q) sequence, thereby performing correction processing on a sequence in which correct words have not increased at least. Can be prevented from being performed.

SUMMARY OF THE INVENTION An object of the present invention is to provide an error correction method in which the correction capability is improved by performing more effective correction processes within a limited time.

Another object of the present invention is to provide an error correction method that can reduce power consumption of a memory, an error correction circuit, and the like.

[Means for solving the problem]

According to the present invention, a data word is formed by a predetermined number of bits of a digital signal, a predetermined number of data words is used as a data block, and a plurality of data blocks are subjected to an error correction code based on a first sequence and a second sequence. An error correction method for decoding a data signal provided, comprising: performing a correction process by performing a correction process of a first sequence on all data blocks; and performing one of a first sequence and a second sequence. An operation of obtaining the position of the other sequence including one data word corrected in a certain sequence and performing a correction process on the other sequence, and each time one word is corrected, continuously obtaining the position of the other sequence and performing a correction process. , Starting from the start sequence and alternately repeating the sequence one by one as long as the correction is continued.

〔Example〕

Hereinafter, embodiments of the present invention will be described with reference to the drawings. This description is made according to the following items.

a. Code configuration b. Error correction method of one embodiment c. Configuration of decoding device of one embodiment d. Operation of decoding device of one embodiment e. Error correction method of another embodiment f. Modification a. Code 1. Configuration FIG. 1 shows the configuration of a code block of an error correction code according to this embodiment. One code block is 4
Word (Digital audio data is 2 words D0, D
1, the parity is 2 words D2, D3) as a data block,
It consists of 25 blocks. Cross interleaving is completed within this code block.

On the other hand, as shown by a solid line, one P-sequence includes data words D0 and D1 and parity D3 included in every five blocks.
Are subjected to, for example, simple parity code encoding. As shown by the broken line, the other Q sequence is obtained by, for example, coding a simple parity code on three words of data words D0 and D1 and parity D2 included in every four blocks. That is, D0D1D3 = D2, D0D1D2 = D3 (means the addition of (mod.2).) Each of the (2 × 25) word data included in the code block has a different combination of the P sequence and Q Included in the series.

As shown in FIG. 2, a block synchronization signal and a block address are added to the head of the data, and a CRC code for error checking for the block address, data D0, D1, and parity D2, D3 is added to the data. The recorded data is sequentially recorded on the magnetic tape by the rotating head.

The data reproduced from the magnetic tape undergoes an error check process using a CRC code, and is written to the RAM. One block of reproduction data written in the RAM undergoes a correction process. In this RAM, a 1-bit error flag is provided for each word, and is set to "1" in advance. When a data word determined to be correct as a result of the CRC check from the magnetic tape is written to the RAM, , Are cleared to “0”.

b. Error Correction Method of One Embodiment The above-described error correction method of the cross interleave code will be described in the order of error correction.

First, the first correction process P1 for the P sequence is performed for all bases. The block of data words D0 is called the base of the sequence. Therefore, there are 25 bases for each of the P sequence and the Q sequence. In the correction process P1, if there is only one error word in one series, this error word is corrected and the error flag is cleared (set to "0"). If all the words in one series are correct or two or more error words, no processing is performed.

Next, a first correction process Q1 for the Q sequence is performed for the first base. If the correction is successful, a second correction process P2 for the P sequence including the corrected word is performed. Further, if the correction is successful in the correction process P2, a second correction process Q2 for the Q sequence including the corrected word is performed. Hereinafter, as long as the correction can be performed, the correction processing for each of the P sequence and the Q sequence is alternately repeated.

Then, in the correction processing after the correction processing Q1, if there are two or more error words in one series, or if there is no error word at all, and therefore correction cannot be performed, a chain of correction processing is performed there. abort. Next, a correction process Q1 is performed on the second base of the Q sequence,
The same chained processing as described above is performed. Thereafter, the same operation is repeated, and when the processing from the 25th base of the Q sequence ends, the correction ends.

An embodiment of the present invention will be described with reference to a specific example shown in FIG. FIG. 3 shows a process when the correction process Q1 is performed on the n-th base and the data words W11, W22, and W13 indicated by black circles are error words.

In the n-th base Q sequence, only the data word W11 is an error word, and the error of this word W11 is corrected in the correction process Q1.

Next, a P-series correction process P2 including the data word W11 is performed. In this P sequence, only the data word W22 is an error word, and the error of this word W22 is corrected.

The correction process Q2 of the Q sequence including the data word W22 is performed, and the error of the data word W13 of one word in the Q sequence is corrected. A correction process P3 of the P sequence including the data word W13 is performed. However, this data word W13
Has no error word, and the correction cannot be continued any more. Therefore, the following (n + 1)
The processing shifts to the correction processing of the Q base of the th base.

According to the above-described invention, the time for repeating the error word that can be corrected by the conventional method four times (P1 → Q1 → P2 → Q2)
All can be corrected within.

The reason why all the theoretically correctable error words can be corrected by the present invention will be described. The error can be corrected when there is only one word error in one line from the beginning, or when two words are wrong in one line and one of them is corrected by another line and becomes one word error. There are only two cases.

The error words in the former case are corrected P1 and corrected
Since Q1 is performed for all blocks, it is always corrected. In the latter case, an error word that has become a one-word error due to the correction process P1 is always corrected even if it is not immediately after, since the correction process Q1 is performed for all blocks. A one-word error resulting from the correction process Q1 and thereafter is always corrected immediately thereafter.

Next, in the present invention, the reason why the error word is corrected by the number of processing times of (the number of blocks × 4) will be described.
Since only one word can be corrected by one sequence, even if the number of correction processes is increased, only the (number of blocks × 2) words of the P sequence and the Q sequence can be corrected. In addition, the number of times of the correction process Q1 in the step of this embodiment is [(corrected word number) +1] for each base. Therefore, the total number of times of the processing in the step is [(number of blocks) + (number of corrected words)].

Since the correction processing P1 in the step is performed for all the bases, the number of processings N obtained by summing the number of processings in the step and the number of processings is expressed by the following equation.

N = (number of blocks) × 2 + (number of corrected words) In the above expression, (number of corrected words) means the value corrected in the step, which is [(number of blocks) × 2]
Always smaller. Therefore, the following relationship holds: N ≦ (number of blocks) × 4. That is, if a processing time corresponding to the (number of blocks × 4) processing times is prepared, all possible errors can be corrected.

c. Configuration of Decoding Device of One Embodiment With reference to FIGS. 4 and 5, a decoding device corresponding to the one embodiment will be described.

In FIG. 4, reference numeral 1 denotes a data RAM for storing data of one code block (see FIG. 1) reproduced from a magnetic tape, for example, and reference numeral 2 denotes a correction circuit. A data word (including a 1-bit error flag) of each of the P-sequence or the Q-sequence read from the data RAM 1 is supplied to the correction circuit 2 and subjected to a correction process. The corrected data word is supplied from the correction circuit 2 to the data RAM 1, and the data is updated.

In the correction circuit 2, an error pulse SE corresponding to the error word and an uncorrectable signal SJ indicating that the error is uncorrectable, that is, there is no error, or that the error is two or more words are generated. The data RAM1 is supplied with a block address BK and a word address WD.

The block address BK is formed by the adder 3 of (mod. 25), and the word address WD is taken out to the output terminal 7 of the switch circuit 4. When the addition of (mod. 25) becomes a value of 25 or more, a value obtained by subtracting 25 becomes the addition result. (Mo
If the subtraction in d.25) becomes negative, the value obtained by adding 25 is the subtraction result. Therefore, the addition result or the subtraction result of (mod. 25) has only the value of (0 to 24).

The base address from the output terminal 12 of the switch circuit 9 is supplied to one input terminal of the adder circuit 3, and the output of the multiplier circuit 13 is supplied to the other input terminal. The multiplication circuit 13 multiplies the word address WD by D (the number of blocks at intervals of the P sequence, in this example, 5 blocks). The multiplication circuit 13 is constituted by a ROM, a bit shifter, and the like.

The switch circuit 9 has an input terminal 10 and an output terminal 12 connected during processing of the P series, and an input terminal 11 during processing of the Q series.
And the output terminal 12 is connected. The input terminal 10 is supplied with a base address from the base flip-flop 14. The output of the (mod. 25) addition / subtraction circuit 15 is supplied to the input terminal 11. The addition / subtraction circuit 15 adds or subtracts the output of the base flip-flop 14 and the output of the multiplication circuit 16. The addition / subtraction circuit 15 is controlled so that an addition operation is performed during processing of the P sequence and a subtraction operation is performed during processing of the Q sequence. The multiplication circuit 16 multiplies the word address WD by d (the interval of the Q sequence is (D−d) blocks, in this example, d = 1).

Reference numeral 17 denotes a word counter, to which a word clock is supplied from a terminal 18. From the word counter 17, a sequentially changing word address ADW is generated,
The word address ADW is supplied to the error word flip-flop 19 in parallel. The error pulse SE from the correction circuit 2 is supplied to the error word flip-flop 19, and the word address of the error word is taken into the error word flip-flop 19 by the error pulse SE.

As shown in FIG. 5, the carry output of the word counter 17 becomes "1" during the four clock periods Ta during which the data words D0 to D3 in one system are read from the data RAM1, and the last one is output.
It becomes "0" during the clock period Tb. This word counter
The carry output of 17 is supplied to the switch circuit 4 as a control signal. The carry output of the word counter 17 is supplied as a clock input to the base flip-flop 14, and the carry output of the word counter 17 is supplied to one input terminal 21 of the switch circuit 20. In the switch circuit 4, the input terminal 5 and the output terminal 7 are connected in a period Ta for inspection, and the input terminal 6 and the output terminal 7 are connected in a period Tb for correction.

The uncorrectable signal SJ from the correction circuit 2 is supplied to the input terminal 22 of the switch circuit 20. The switch circuit 20 is controlled such that the input terminal 21 and the output terminal 23 are connected at the time of the step of the error correction method according to this embodiment, and the input terminal 22 and the output terminal 23 are connected at the time of the step. The output signal of the switch circuit 20 is supplied to the base counter 24 as a clock input.

The base counter 24 has a base sequence (0, 1, 2,.
4) Generate a base number indicating the number. This base number is supplied to one input terminal 26 of the switch circuit 25.
The output of the addition / subtraction circuit 15 is supplied to the other input terminal 27 of the switch circuit 25. The switch circuit 25 performs correction processing P1 and Q1.
At this time, the input terminal 26 and the output terminal 28 are connected, and at the time of the correction process P2, the input terminal 27 and the output terminal 28 are controlled to be connected. The output of the switch circuit 25 is supplied to the base flip-flop 14.

Reference numeral 29 denotes a control signal generator. The control signal generator 29 generates a control signal for the switch circuits 9, 20, and 25 and a control signal for the operation of the addition / subtraction circuit 15. The control signal generator 29 includes a carry output of the base counter 24, an uncorrectable signal SJ and an input terminal 30.
And a correction operation start signal. Further, a correction operation end signal is generated at the output terminal 31. In response to the correction operation end signal, operations such as prohibition of clock input to the correction circuit 2 and prohibition of clock input to the word counter 17 are performed.

d. Operation of the Decoding Apparatus of One Embodiment In both the steps and the steps of the correction method, the first four clocks are (0, 1, 2, 3) by the output signal shown in FIG. The word address ADW which is sequentially incremented is supplied as the word address WD of the data RAM 1 via the switch circuit 4,
The data word and the error flag are read. The read data word and the error flag are supplied to the correction circuit 2, and the number of error words in one series is checked. In addition, the last one clock is such that the switch circuit 4 is switched and the error pulse SE is supplied to the error word flip-flop 19.
Is supplied to the data RAM 1 as the word address WD.

The correction circuit 2 counts the number of error flags “1” (with error) of the read data and generates corrected data. If there is only one error in one series, the correction data from the correction circuit 2 and the error flag of "0" are written to the data RAM1. In other cases, that is, when there is no error in one stream and when there is an error of two or more words, the uncorrectable signal SJ is output.

When the correction process P1 in the step is performed,
As shown in FIG. 4, the input terminal 10 and the output terminal 12 of the switch circuit 9 are connected, the input terminal 21 and the output terminal 23 of the switch circuit 20 are connected, and the input terminal 26 of the switch circuit 25 is connected.
And the output terminal 28 are connected.

In the correction process P1, the base counter 24 is incremented each time one correction process is completed, and the contents of the base counter 24 are latched in the base flip-flop 14. The output of the base flip-flop 14 and the output of the multiplication circuit 13 are supplied to the addition circuit 3, and the output of the addition circuit 3 extracts the block address BK. Therefore, when the base counter 24 is incremented from 0 to 24, correction processing is performed on all the P series. When the block address for the P sequence is PBK, the data word number is Dn (0, 1, 2, or 3), and the base number is PB, the block address PBK for each data word is generated according to the following equation. Is done.

PBK = PBD × Dn (1) (However, means addition of (mod.25).) In addition, when generating block addresses QBK for all Q sequences, the base number is QB Then, the block address QBK of each data word is generated according to the following equation.

QBK = QBd × Dn (2) (However, means the subtraction of (mod.25).) In the step of the error correction method, the base of the other series including the corrected word can be obtained. is necessary.
With respect to the corrected word, the block address of the data block including this word becomes the same. Therefore, QB = PBd × Dn (3) PB = QBd × Dn (4) In this embodiment, since (d = 1), QB = PBDn (5) PB = QBDn (6) That is, when the correction can be made in the P sequence, the base value PB is Add the data word number Dn and add the base of the next Q sequence
On the other hand, if the correction can be made with the Q sequence, the base PB of the next P sequence may be subtracted.

In the correction process step Q1 and subsequent processes of the correction method,
First, the input terminal 11 and the output terminal 12 of the switch circuit 9 are connected. Further, the input terminal 22 and the output terminal 23 of the switch circuit 20 are connected, and the input terminal 26 and the output terminal 28 of the switch circuit 25 are connected. The adder 3 generates a block address QBK represented by the equation (2) and performs a correction process Q1. If the base counter 24 corrects the error based on the Q sequence of the generated base QB, the switch circuit 25 is switched, the input terminal 27 and the output terminal 28 are connected, and the output of the addition / subtraction circuit 15 is latched by the base flip-flop 14. , The base PB of the next correction process P2. At the time of the P series correction process, the addition / subtraction circuit 15 performs an addition operation.

In the step, as long as the correction continues, the switch circuit 9 is alternately switched, and the correction process is repeated in the order of Q2 → P3 → Q3. An uncorrectable signal SJ is generated when all the data words in one series are correct or an error of two or more words occurs. This uncorrectable signal SJ is supplied to the base counter 24 via the switch circuit 20, and the content of the base counter 24 becomes 1
move on. The contents of the base counter 24 are supplied to the base flip-flop 14 via the switch circuit 25, and are latched by the base flip-flop 14. At the same time, the switch circuit 9 is switched to a state of selecting the input terminal 11 side, and the correction process Q1 is started from a new base. When the content of the base counter 24 exceeds 24, the correction ends, and a correction end signal is generated at the output terminal 31 of the control signal generation circuit 29.

e. Error correction method of another embodiment In the step of the correction method of the above-described one embodiment, the sequence that cannot be corrected is either a sequence having no error in all words or an error of two or more words. is there. Therefore, the series that has been processed once,
An error in the sequence cannot be corrected, and starting a correction process from this sequence is useless. Therefore, in another embodiment, a series that has been corrected at least once is remembered,
The correction process is not started from the series. In another embodiment, a register for storing a 1-bit flag for each of the bases of the P sequence and the Q sequence is provided, and the flag is cleared to “0” in advance. The register has twice the number of bits as the number of blocks.

An error correction method according to another embodiment will be described in the order of error correction.

When the correction process P1 is performed, the contents of the registers related to the base of the first sequence are checked in order from the base of the first sequence. If the flag is set to “1”, the sequence is
Without doing anything, the process proceeds to the next base sequence, and if it has been reset to "0", it is set to "1" and the correction process for that sequence is performed. If the correction is successful, the flag corresponding to the base of the Q sequence including the word is set to "1" and the correction process Q1 is performed. Further, as long as the correction can be performed, the flag is set and the correction process is performed. When the correction cannot be continued, the process proceeds to the base of the next P sequence and performs the same process. The same processing is performed up to the last base of the P sequence.

The correction process Q1 is performed from the base of the first Q sequence in the same manner as the above-described correction process. When the processing is performed up to the base of the last Q sequence, the correction ends.

According to the other embodiment, all the errors that can be corrected can be corrected by the (number of blocks × 4) processing times. Needless to say, since the correction processing is not started from the series once processed, the number of times of the correction processing can be made smaller than that in the embodiment.

f. Modifications In the steps of the above-described embodiment, a flag for the Q sequence may be prepared, and the sequence subjected to the correction processing may be stored when performing the sequential correction processing.

In the other embodiments described above, it is not necessary to store the series subjected to the correction processing.

The present invention also relates to an error correction method in which a pointer for which an error or a correct is undecided is assigned, the iterative correction processing is performed without determining whether the word of this pointer is incorrect or correct, and finally this determination is made. Can be applied.

Further, in the present invention, it is not necessary to provide an error check code (CRC code) based on a sequence in a data block. The present invention can be similarly applied to a cross interleave code which is not a block complete type.

〔The invention's effect〕

According to the present invention, the following correction processing is performed only on the other series including the word corrected by one series of the cross interleave code. Therefore, it is possible to prevent useless correction processing for a sequence in which correct words have not increased at least. According to the present invention, the correction capability can be improved by performing more effective correction processes within a limited time. Further, according to the present invention, it is possible to reduce the power consumption of the error correction circuit and the like.

[Brief description of the drawings]

FIG. 1 is a schematic diagram used to explain a code configuration to which the present invention can be applied, FIG. 2 is a schematic diagram showing an example of a data configuration on a tape at the time of recording / reproduction, and FIG. FIG. 4 is a schematic diagram used for explaining one embodiment of the present invention, FIG. 4 is a block diagram showing an example of a decoding device provided for embodying the present invention, and FIG. 5 is a waveform diagram used for explaining the operation of the decoding device. Explanation of main symbols in the drawings 1: data RAM, 2: correction circuit, 3: (mod. 25) addition circuit, 1
3, 16: multiplication circuit, 17: word counter, 24: base counter.

Claims (1)

(57) [Claims] A data word is formed by a predetermined number of bits of a digital signal, and a predetermined number of the data words is used as a data block, and a plurality of the data blocks are error-corrected by a first sequence and a second sequence. In an error correction method for decoding a data signal provided with a correction code, a step of performing correction by performing a correction process on the first sequence for all of the data blocks; and a process for correcting the first sequence and the second sequence. The position of the other sequence including the one data word corrected by one of the sequences is determined, and the correction process is performed on the other sequence. Starting from the start sequence and repeating the operation for correcting the position one by one as long as the correction continues. Ri correction method.