JPS6296824U - - Google Patents

Info

Publication number
JPS6296824U
JPS6296824U JP18818085U JP18818085U JPS6296824U JP S6296824 U JPS6296824 U JP S6296824U JP 18818085 U JP18818085 U JP 18818085U JP 18818085 U JP18818085 U JP 18818085U JP S6296824 U JPS6296824 U JP S6296824U
Authority
JP
Japan
Prior art keywords
electrodes
insulating layer
wiring board
capacitor
multilayer wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18818085U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP18818085U priority Critical patent/JPS6296824U/ja
Publication of JPS6296824U publication Critical patent/JPS6296824U/ja
Pending legal-status Critical Current

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  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、本考案の多層配線基板の一実施例の
断面図であり、第2図は、従来の多層配線基板の
一例の断面図である。 1,10:多層配線基板、2:絶縁層、2a:
最上層の絶縁層、3,11:電極、5,12:コ
ンデンサ。
FIG. 1 is a sectional view of an embodiment of a multilayer wiring board of the present invention, and FIG. 2 is a sectional view of an example of a conventional multilayer wiring board. 1, 10: Multilayer wiring board, 2: Insulating layer, 2a:
Top insulating layer, 3, 11: electrode, 5, 12: capacitor.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 3層以上積層された絶縁層の層間と最上層の絶
縁層の上面とに平面投影でほぼ重さなり合うよう
に電極をそれぞれ配設し、これらの電極を一枚置
きに電気的接続して噛合する2つの櫛状としてコ
ンデンサを形成した多層配線基板において、最上
層の絶縁層の上下に配設された電極を他の電極よ
り広い面積で配設し、最上層の絶縁層の上面に配
設した電極の面積をトリミングして前記コンデン
サの容量値を調整することを特徴とする多層配線
基板。
Electrodes are arranged between the layers of three or more laminated insulating layers and on the upper surface of the top insulating layer so that they almost overlap each other in planar projection, and these electrodes are electrically connected every other layer. In a multilayer wiring board in which a capacitor is formed as two interlocking combs, the electrodes placed above and below the top insulating layer have a larger area than the other electrodes, and the electrodes are placed on the top surface of the top insulating layer. A multilayer wiring board characterized in that the capacitance value of the capacitor is adjusted by trimming the area of the provided electrode.
JP18818085U 1985-12-05 1985-12-05 Pending JPS6296824U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18818085U JPS6296824U (en) 1985-12-05 1985-12-05

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18818085U JPS6296824U (en) 1985-12-05 1985-12-05

Publications (1)

Publication Number Publication Date
JPS6296824U true JPS6296824U (en) 1987-06-20

Family

ID=31139302

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18818085U Pending JPS6296824U (en) 1985-12-05 1985-12-05

Country Status (1)

Country Link
JP (1) JPS6296824U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03154404A (en) * 1989-11-10 1991-07-02 Sumitomo Metal Ind Ltd High frequency resonator

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03154404A (en) * 1989-11-10 1991-07-02 Sumitomo Metal Ind Ltd High frequency resonator

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