JPS6293960A - Package structure employing silicon carbide - Google Patents

Package structure employing silicon carbide

Info

Publication number
JPS6293960A
JPS6293960A JP60233266A JP23326685A JPS6293960A JP S6293960 A JPS6293960 A JP S6293960A JP 60233266 A JP60233266 A JP 60233266A JP 23326685 A JP23326685 A JP 23326685A JP S6293960 A JPS6293960 A JP S6293960A
Authority
JP
Japan
Prior art keywords
chip
sic
gold
silicon
thermal expansion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60233266A
Other languages
Japanese (ja)
Inventor
Koichi Inoue
井上　広一
Yasutoshi Kurihara
保敏 栗原
Komei Yatsuno
八野　耕明
Mamoru Sawahata
沢畠　守
Masaaki Takahashi
正昭 高橋
Takanobu Yamamoto
隆宣 山本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP60233266A priority Critical patent/JPS6293960A/en
Publication of JPS6293960A publication Critical patent/JPS6293960A/en
Pending legal-status Critical Current

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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/15—Ceramic or glass substrates
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    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29111—Tin [Sn] as principal constituent
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Abstract

PURPOSE:To obtain package structure with low thermal resistance and high reliability by a method wherein the 1st dielectric which is made of material containing at least SiC and has a predetermined thermal expansion coefficient and on which a semiconductor substrate is fixed is mechanically coupled with the 2nd dielectric. CONSTITUTION:A wiring member 7 in which conductive paths 11 are formed, an SiC member 301 which is metallized with Mo, a W member 302, adhesive metal 303 and an adhering member 6 (Al coated with Al alloy containing Si on both sides) are combined and pressed and heated in vacuum to bond the wiring member 7 and the members 301 and 302. Then a die-bonding part and wire bonding electrodes 13 are formed by nonelectrolytic plating of gold. The gold film on the backside of a chip 1 is heated and converted into a gold-Si eutectic solder film and the Si chip 1 is bonded. gold wires 14 are connected between the wire bonding electrodes on the front side of the chip 1. A sealing member 9 is bonded to the member 7 by an adhering member 8, which is Au-Sn eutectic solder, to complete a package.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は半導体基体を第１誘電体基板に固定し。[Detailed description of the invention] [Field of application of the invention] In the present invention, a semiconductor substrate is fixed to a first dielectric substrate.

該第１誘電体基板を、外周部に該半導体基体を外部と電
気的に結合するための端子群を配置した第２誘′ａ体基
板と機械的に結合した半導体パンケージ構造体に係り１
％に該第１誘電体基板が該第２誘電体基板と異なる材質
で構成されており、しかも該第１誘電体基板が炭化珪素
の焼結体を含む一つ以上の材質からなる半導体パッケー
ジ構造体に関する。Relating to a semiconductor pancage structure in which the first dielectric substrate is mechanically coupled to a second dielectric substrate having a group of terminals disposed on the outer periphery for electrically coupling the semiconductor substrate to the outside,
%, the first dielectric substrate is made of a different material from the second dielectric substrate, and the first dielectric substrate is made of one or more materials including a sintered body of silicon carbide. Regarding the body.

〔発明の背景〕[Background of the invention]

半導体集積回路は近年１すます高密度化、高集積化に拍
車がかかり、ＬＳＩチップは大型化の傾向が著しいと同
時にその発熱密ｔ）ｔも増７Ｊｌ］の一途をたどってい
る。このような状況に対応するため、ＬＳＩチップを外
部回路に接続するための半４体パッケージもその構造及
び材・實に大幅な改嵜が要求されている。近年注目を集
めている、いわゆるピノ・グリッド・アレーは上記の情
勢に対応して開発されたものである。Semiconductor integrated circuits have become increasingly dense and highly integrated in recent years, and LSI chips have shown a remarkable tendency to become larger, and at the same time their heat density t) is also increasing. In order to cope with such a situation, the structure, material, and actuality of semi-quad packages for connecting LSI chips to external circuits are also required to be significantly modified. The so-called Pinot Grid Alley, which has been attracting attention in recent years, was developed in response to the above situation.

一般的なビ／・グリッド・アレーの構成を第２図に示す
。ビン・グリッド・アレーの主要部分は第２図に示すよ
うに大きく分けて３つの部分から成り立っている。ＩＣ
支持部材３はＬＳＩチップを機械的に支え、しかもＬＳ
Ｉチップで発生する熱を効率よく逃がす働きをする。配
線用部材７はＬＳＩチップ・＼の電力の供給やＬＳＩチ
ップからの信号の増りたしを、その内部に形成した。４
東経路１１により行う。密閉用部材９はＬＳＩチップを
外界から遮蔽するための蓋である。これらの３つの部分
が一体化したとき全体で気密の容器を形成する。この容
器は外界からＬ　Ｓ　Ｉチップを遮断し、その性能を外
界の状態に関係なく常に維持するｆ動きをする。FIG. 2 shows the configuration of a general bi/grid array. The main part of the bin grid array is roughly divided into three parts as shown in FIG. IC
The support member 3 mechanically supports the LSI chip, and also supports the LSI chip.
It works to efficiently dissipate the heat generated by the I-chip. The wiring member 7 is configured to supply power to the LSI chip and increase signals from the LSI chip. 4
This will be done via East Route 11. The sealing member 9 is a lid for shielding the LSI chip from the outside world. When these three parts are integrated, the whole forms an airtight container. This container insulates the LSI chip from the outside world and provides a f-motion that always maintains its performance regardless of the conditions of the outside world.

ビン・グリッド・アレーの構成材料に対する要求は上述
の３つの部分によりそれぞれ異なる。ＩＣ支持部材３で
は熱を効率よく逃がすグこめに高熱伝導率が、シリコノ
（Ｓｉ　）との接着の信頼性確保のためＳｌに近い熱膨
張係数が、また、システムの設計の自由度を確保するた
めには電気絶縁性が望まれる。この部分には従来ベリリ
ア（Ｂｅｄ）、アルミナ（Ａ１２０３）、銅−タングス
テン合金（Ｃｕ−Ｗ）　　などが使用されてきた。配線
用部材７では４電経路１１を高密度に形成する必要があ
り、高密度多層配線の可能な材料が要求される。The requirements for the materials of construction of the bin grid array are different for each of the three sections mentioned above. The IC support member 3 has a high thermal conductivity to efficiently dissipate heat, a thermal expansion coefficient close to Sl to ensure reliability of bonding with silicone (Si), and a high degree of freedom in system design. Therefore, electrical insulation is desired. Conventionally, materials such as beryllia (Bed), alumina (A1203), and copper-tungsten alloy (Cu-W) have been used for this part. In the wiring member 7, it is necessary to form four electric paths 11 at high density, and a material that allows high-density multilayer wiring is required.

この部分には従来アルミナ（Ａ１２０３）、ベリリア（
Ｂｅｄ）などが使用されてきた。密閉用部材９では配線
用部材７との熱膨張係数の適合曲がその構成材料に要求
きれるｇ質で、ちる。この部分にはコバール（Ｆｔ士−
２９Ｎｉ　−１７Ｃｏ）、アルミナなどが１更用されて
きた。これらの３つの部分が一体化したとき、パッケー
ジ全体と［７て信頼的三を確保−するためにはこれらの
３つの部分の熱膨張係数がお互いに近い値であることが
望捷し５い。ＩＣ支持部材３では既に述べたように８１
と熱膨張係数が近くないといけないので総ての部分を構
成する材料はＳｌと熱膨張係数が近い＋ｔｉ″′Ｃある
ことが望ましいということになる。Conventionally, this part was made of alumina (A1203), beryllia (
Bed) etc. have been used. The sealing member 9 has a thermal expansion coefficient compatible with that of the wiring member 7, and is of a material that meets the requirements for its constituent materials. In this part, Kobar (Ft.
29Ni-17Co), alumina, etc. have been used for some time. When these three parts are integrated, it is desirable that the coefficients of thermal expansion of these three parts be close to each other in order to ensure reliability of the overall package. . In the IC support member 3, as already mentioned, 81
Since the coefficient of thermal expansion must be close to that of Sl, it is desirable that the material constituting all the parts be +ti'''C, which has a coefficient of thermal expansion close to that of Sl.

ここで、上記各材料の特徴、欠点について述べる。特に
高性能ではない半導体装置のＩＣ支持、配線及び密閉用
部材によく使われる材料はアルミナである。その最大の
理由はアルミナが比較的安価であるということである。Here, the characteristics and drawbacks of each of the above materials will be described. Alumina is a material often used for IC support, wiring, and sealing members of semiconductor devices that are not particularly high-performance. The biggest reason for this is that alumina is relatively inexpensive.

しかしながら、アルミナにはシリコンと熱膨張係数が合
わない（６，５ＸＩＯ−’）、そして熱伝導率が小さい
（１７Ｗ、／ｍＫ）という欠点がめる。これらの欠点の
うち特に熱伝導率について改善し、半導体装置を高性能
化する場合にけべ１７１Ｊアが使用さｔする。ベリリア
の熱伝導率は２６０　Ｗ／ｍＫもめるため、ＩＣ支持部
材３に使用すると、同一のパッケージサイズで大幅に発
熱量を大きくすることができる。しかし、ベリリアは高
価でアリ、シリコンと熱膨張係数が合わない（７，５Ｘ
１０−’）、さらに有毒であるという大きな欠点を持っ
ている。ＬＳＩとパッケージの外部とを電気的に絶縁す
る必要かない場合には、ＩＣ支持部材３に銅とタングス
テンの合金（ＣＩ−Ｗ）が使われる。よく使われるタン
グステン２０重量壬の物を例にとると、熱伝導率は２８
０　Ｗ／ｍ　ＫでべＩＪ　ＩＪアやＳｉＣとほぼ同じで
あり充分大きい。しかしながら、熱膨張係数はべりリア
やアルミナ並の７．０Ｘ１０−’であり、シリコノと合
わない。However, alumina has drawbacks such as a coefficient of thermal expansion that does not match that of silicon (6,5XIO-') and a low thermal conductivity (17 W,/mK). Among these drawbacks, Kebe 171JA is used to improve the thermal conductivity and improve the performance of semiconductor devices. Since beryllia has a thermal conductivity of 260 W/mK, when used in the IC support member 3, the amount of heat generated can be significantly increased with the same package size. However, beryllia is expensive, and its coefficient of thermal expansion does not match that of silicon (7.5X
10-'), which also has the major drawback of being toxic. If it is not necessary to electrically insulate the LSI from the outside of the package, an alloy of copper and tungsten (CI-W) is used for the IC support member 3. For example, the thermal conductivity of a commonly used tungsten material weighing 20 kg is 28.
0 W/mK is almost the same as IJA and SiC and is sufficiently large. However, the coefficient of thermal expansion is 7.0×10-', which is similar to Berria and alumina, and does not match that of silicone.

以上述べたように従来の材料には総ての面で要、７性能
を満足出来る物はない。特に、熱伝導率が大きく、高性
能の半導体装置用として使用出来る材料としてはＢｅＯ
Ｌかなく、有毒であるため代替材料が望まれていた。こ
のような要求に応える材料として例えば、浦、安置”　
Ｌ　Ｓ　Ｉ実装への応用が始まったＳｉＣセラミック”
、日経エレクトロニクス１９８４．９．２４．　ｐｐ、
　２６５−２９４　　に開示されているよって炭化珪素
（ＳｉＣ）が開元された。５ｉｃｕ熱伝導率が２７０Ｗ
／ｍＫとＨｅ　Ｏ並みであり、しかも熱膨張係数がシリ
コンに近い３．７ＸＩＦ’であり、さらに毒性がないと
いう大きな特徴を持っている。しかしながら、多層配線
ができないために配、線用部材７には１吏用出来ない。As mentioned above, there is no conventional material that can satisfy the seven requirements in all aspects. In particular, BeO is a material that has high thermal conductivity and can be used for high-performance semiconductor devices.
Since it has no L and is toxic, an alternative material has been desired. Examples of materials that meet these demands include ura, enki”
SiC ceramics have begun to be applied to LSI packaging”
, Nikkei Electronics 1984.9.24. pp,
265-294, silicon carbide (SiC) was discovered. 5ICU thermal conductivity is 270W
/mK, which is comparable to that of He 2 O, and its coefficient of thermal expansion is 3.7XIF', which is close to that of silicon, and it also has the great feature of being non-toxic. However, since multilayer wiring is not possible, the wiring member 7 cannot be used in one piece.

従って、配線用部材７と何等かの方法で接ＫＷ　Ｌなけ
ればならない。ところが、配線用部材７に通常側われ、
るアルミナ、その他の材料と熱膨張係数が合わないため
に特に信頼性の高い接着方式か必要である。ＳｉＣはア
ルミナ等、酸化物系のセラミックスに比べて接着力が弱
いが、比較的低温（約３５０Ｃ以下）の温度粂件ではチ
タン−白金−金膜をＳｉＣ表面に形成し、はんだ付けす
る方法等、信頼性の高い方式が既に開発されている。し
かしながら、５０００程度の高温に耐える接着方式がな
かった。Therefore, it must be connected to the wiring member 7 in some way. However, when the wiring member 7 is usually placed on the side,
Because the coefficient of thermal expansion does not match that of alumina and other materials, a particularly reliable bonding method is required. SiC has weak adhesive strength compared to oxide-based ceramics such as alumina, but at relatively low temperatures (approximately 350C or less), it is possible to form a titanium-platinum-gold film on the SiC surface and solder it. , a highly reliable method has already been developed. However, there was no adhesive method that could withstand high temperatures of about 5,000 ℃.

一方、ビン・グリッド・アレーの構造に関しては、特例
シリコン・チップ１のワイヤボンディング酸についての
問題分抱えている。第３図に第１図のシリコン・チップ
１を含むビン・グリッド・アレーの中心部を拡大して示
す。寸法ａはシリコン・ウェハのサイズによって差はあ
るものの、はぼ０．５〜０．６ｒｒｖｎ″′Ｃある。こ
れに対し、て１寸法す及び寸法Ｃはグリーン・ノート・
プロセス及び配線容量上の制約から、通常０．５〜０．
７　ｒａｎであ６゜その結果１図のようにワイヤホンデ
ィングを２列にわたって行うｅζは２列目１４２のボン
ディング段差が犬きく実用に耐えないという問題が生ず
るのである。勿論、ワイヤボンディングが１列のみであ
れば問題はないが、ここではＩＣ支持部材３にＳｉＣを
使用する特に高性能なビン・グリッド・アレーを扱うの
で当然ワイヤボンディングは２列でなければならない。On the other hand, regarding the structure of the bin grid array, there are problems related to the wire bonding acid of the special silicon chip 1. FIG. 3 shows an enlarged view of the central portion of the bin grid array containing the silicon chips 1 of FIG. Although dimension a varies depending on the size of the silicon wafer, it is approximately 0.5 to 0.6rrvn'''C.On the other hand, dimension
Due to process and wiring capacity constraints, it is usually 0.5 to 0.
As a result, as shown in Fig. 1, eζ in which wire bonding is performed over two rows has a problem in that the bonding level difference in the second row 142 is too large to be practical. Of course, there is no problem if there is only one row of wire bonding, but since we are dealing here with a particularly high-performance bin grid array that uses SiC for the IC support member 3, it is natural that there must be two rows of wire bonding.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、半導体基体を第１誘醒体基板に固定し
、該第１誘心体基板を、外周部に該半導体基体を外部と
電気的に結合するための端子群を配置し７た第２誘電体
基板と機械的に結合した半導体パッケージ構造体に於い
て、上記した構成材料及び構造上の欠点を解消した半導
体パッケージ構造体を提供することである、 〔発明の概要〕 本発明は、半導体基体を固定した第１誘畦体基板を、シ
リコンに近い熱膨張係数を有する少なくとも炭化珪素を
含む一つ以上の材料で構成し、該炭化珪素と第１誘電体
基板の他の構成材料成いは外向部に該半４体基体を外部
と電気的に結合するだめの端子群を配置した第２誘直体
基板々の高信頼性の接着構造として高融点の活性金属（
銅、アルミニウム、ニッケル及びそれ等とシリコノとの
合金）を柑いた点及び、第１誘奄体基板の該半導体基体
を接着する領域の厚さを他の部分より大きくした点に特
徴がある。An object of the present invention is to fix a semiconductor substrate to a first dielectric substrate, and arrange a group of terminals on the outer periphery of the first dielectric substrate for electrically connecting the semiconductor substrate to the outside. SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor package structure which is mechanically coupled to a second dielectric substrate and which eliminates the above-described drawbacks in terms of constituent materials and structure. The first dielectric substrate on which the semiconductor substrate is fixed is made of one or more materials containing at least silicon carbide having a coefficient of thermal expansion close to that of silicon, and the silicon carbide and other compositions of the first dielectric substrate are The material consists of a high melting point active metal (
The present invention is characterized by the fact that copper, aluminum, nickel, and alloys of these and silicone are used, and that the region of the first dielectric substrate to which the semiconductor substrate is bonded is thicker than other parts.

〔発明の実施例〕[Embodiments of the invention]

本発明の一実施例を第１図に従って貌明する。 An embodiment of the present invention will be explained with reference to FIG.

本実施例では、第２図に示したような一般的なビン・グ
リッド・アレーに於けるＩＣ支持部材３を、ＳＩＣ部材
３０１とタングステン部材３０２とで構成した。また、
配線用部材７としては、比誘電率が約６と小さく、シか
も、熱膨張係数が４．５〜５．０Ｘ１０＝と比較的シリ
コンに近いムライト（３Ａ１２０３・２Ｓｉ０２）　　
を用いた。In this embodiment, the IC support member 3 in a general bin grid array as shown in FIG. 2 is composed of an SIC member 301 and a tungsten member 302. Also,
The wiring member 7 is made of mullite (3A1203/2Si02), which has a small dielectric constant of about 6 and a coefficient of thermal expansion of 4.5 to 5.0X10, which is relatively similar to silicon.
was used.

ここで、ＩＣ支持部材３をＳｉＣ部材３０１とタングス
テン部材３０２とで構成したことによシ以下のような特
徴が得られた。１６／リコン・チップ１は外部とＳＩＣ
により電気的に絶縁される。Here, by constructing the IC support member 3 from the SiC member 301 and the tungsten member 302, the following characteristics were obtained. 16/Recon chip 1 is external and SIC
electrically isolated by

２、シリコンからムライトに至るまで熱膨張係数が緩や
かに増加し、それぞれの接着部に無理がかからない（シ
リコン：　３．　　ｓｒｃ　：　３．７．タングステン
：４．５．ムライト＝４．５〜５．　ＯＸ　１０−’／
Ｃ）。2. The coefficient of thermal expansion gradually increases from silicon to mullite, and no strain is applied to each bonding part (silicon: 3. src: 3.7. tungsten: 4.5. mullite = 4.5 to 5. OX 10-'/
C).

３、ＳｉＣのみで構成するよりもＳＩＣの形状が簡単に
なり、加工が浴易である。ｔｓｉｃ　やタングステンの
熱伝導率は、はんだよりも大きいので。3. The shape of the SIC is simpler than that made of only SiC, and processing is easier. The thermal conductivity of tsic and tungsten is higher than that of solder.

シリコン・チップ１から空冷フィン５（第２図参照）ま
での熱抵抗は、ＩＣ支持部材３をＳＩＣのみで構成する
場合と殆ど変わらず、その差は実、＠誤差の範囲内であ
った。The thermal resistance from the silicon chip 1 to the air cooling fins 5 (see FIG. 2) was almost the same as when the IC support member 3 was composed of only SIC, and the difference was actually within the range of error.

なお、ここでいう熱抵抗とは、シリコン・チップ１に通
′這しシリコン・チップ１の湛ＩＷが充分安定したとき
におけるシリコン・チップ１の表面温度と空冷フィン５
の表面温度との差をシリコン・チップ１の発熱量で除し
た商である。The thermal resistance here refers to the surface temperature of the silicon chip 1 and the air cooling fin 5 when the IW of the silicon chip 1 is sufficiently stable.
This is the quotient obtained by dividing the difference from the surface temperature of the silicon chip 1 by the amount of heat generated by the silicon chip 1.

シリコン・チップ１の厚さく寸法ａ）は０．５　ｍｍで
ある。また、配線用部材７の段差（寸法す及びＣ）は０
．６４簡である。したがって、ＳｉＣ部材３０１の厚さ
を０．４６ｍｍとした。こうすることにより、ワイヤボ
ンディング時の段差は最も小さく。The thickness dimension a) of the silicon chip 1 is 0.5 mm. Also, the level difference (dimensions and C) of the wiring member 7 is 0.
．． It is 64 simple. Therefore, the thickness of the SiC member 301 was set to 0.46 mm. By doing this, the step difference during wire bonding is minimized.

０．３２ｍｍとなる。配線用部材７の中心部には一辺１
０■の正方形の穴が開けてあり、−辺１５聴のＩＣ支持
部材３が接着部材６で接着されている。It becomes 0.32 mm. One side is placed in the center of the wiring member 7.
A square hole with a size of 0.0 mm is made, and an IC support member 3 with a -side of 15 holes is adhered with an adhesive member 6.

その中心部７Ｍ角（シリコン・チップ１の寸法よりＩＢ
大きい）にはシリコン・チップ１の接着のための金のメ
タライズが施しである。きらに１階段状に成形された部
分には、内部の導電路１１に接続した金のメタライズに
よるワイヤボンディング電極（基板側）１３が導＋［路
１１に対応した数だけ形成さ７１ている。特に本実施例
では、密閉用部材９の材質をコバール（Ｆｅ−２９Ｎｉ
−１７Ｃｏ）とした。コバールは熱膨張係数が４．５Ｘ
１０−’と、シリコンに近い。従って１本実施例ではパ
ンケージの構成材料は総てシリコンと熱膨張係数が近い
もの（最大で差が２．０Ｘ１０”’）になり、パッケー
ジ内のどの部分でも部材間の熱膨張係数の違いによる熱
疲労は問題にならない。The center part is 7M square (IB from the size of silicon chip 1)
(large) is coated with gold metallization for adhesion of the silicon chip 1. Wire bonding electrodes (substrate side) 13 made of gold metallization and connected to internal conductive paths 11 are formed 71 in the part formed in a single step shape in a number corresponding to the conductive paths 11. In particular, in this embodiment, the material of the sealing member 9 is Kovar (Fe-29Ni).
-17Co). Kovar has a coefficient of thermal expansion of 4.5X
10-', close to silicon. Therefore, in this example, all the constituent materials of the pan cage have thermal expansion coefficients close to that of silicon (maximum difference is 2.0 x 10''), and any part of the package will be affected by the difference in thermal expansion coefficient between the members. Heat fatigue is not a problem.

本発明によるパッケージを得るには、まず内部にタング
ステンによる導電路１１を形成した配線用部材７と、厚
さ０．４６　ｗｎ、−辺９聰の、中上・部−辺７＋ｍ＋
の領域にモリブデンによる金属化を施したＳｉＣ部材３
０１と厚さ０．３順、−辺１５酎のタングステン部材３
０２と、それら分接着するための接着金属３０３及び接
着部材６として厚さ１随の純アルミニウムの両面に１２
Ｍ惜％のシリコンを含有したアルミニウム合金を０．１
ｍコーティングしたものを用意する。次に、これらを組
み合わせ、適当な圧力（５〜５０ＭＰ　ａ　）を加えな
がら５７７Ｃ（アルミニウム合金の融点）を越え。To obtain a package according to the present invention, first, a wiring member 7 with a conductive path 11 made of tungsten formed therein, a middle upper part with a thickness of 0.46 wn and a side of -9 length, a side of 7+m+
SiC member 3 with molybdenum metallization in the area
01 and thickness 0.3 order, - side 15 tungsten member 3
02, adhesive metal 303 and adhesive member 6 for adhering these parts, 12 on both sides of pure aluminum with a thickness of about 1.
Aluminum alloy containing 0.1% silicon
Prepare a coated one. Next, combine these and exceed 577C (melting point of aluminum alloy) while applying appropriate pressure (5 to 50 MPa).

６６０Ｃ（アルミニウムの融点）未満の一定温度でＸ仝
中又は非酸化性ガス雰囲気中で３０分保持する。その結
果、配線用部材７と、ｓＩｅ部材３０１とタングステン
部材３０２が接着される。Hold at a constant temperature below 660C (melting point of aluminum) for 30 minutes in an atmosphere of X or non-oxidizing gas. As a result, the wiring member 7, the sIe member 301, and the tungsten member 302 are bonded together.

ここで、１２重９１のシリコンを含・仔したアルミニウ
ム合金は浴融１７、蝋剤として作用する。また。Here, the aluminum alloy containing 12 times 91 silicon acts as a bath melting agent 17 and a waxing agent. Also.

厚ジ１朋の純アルミニウムは、各部材間の接着間隙のば
らつきを吸収する緩衝材どして、及び一部はアルミニウ
ム合金或いはＳＩＣ基板或いにムライト基板から供給官
ｎ、たシリコン（でよって融点が下がり、溶融するこさ
によって燻材として働く。Pure aluminum with a thickness of 1 mm is used as a cushioning material to absorb variations in the bonding gap between each member, and some of it is made from aluminum alloy, SIC substrate, or mullite substrate. It has a lower melting point and works as a smoking material due to its hardness.

次に、金の無′諷屏めつきを施し、シリコ／・チップ１
のダイボンディング部（−辺７順）及びワイヤボアディ
ング′成極（基板側）１３を形成する。Next, add a gold plate and apply silicone/chip 1.
A die bonding part (in the order of -side 7) and a wire boring' polarization (substrate side) 13 are formed.

次にシリコン・チップ１の裏１ｆｉ］に被着さハ、た金
１１悼を加熱により万一シリコン共晶はんだに変化させ
。Next, the metal 11 deposited on the back side 1fi of the silicon chip 1 is heated to transform it into silicon eutectic solder.

ダイボンド部材２としてシリコン・チップ１を接着する
。シリコン・チップ１の表面側にはワイヤボンディング
を極（基板側）１３と同じ数のワイヤボンディング電極
（チップ側）１５が形成されており、それらの間を金の
細線であるワイヤ１４で接続する。最後に密閉用部材９
を金−錫の共晶はんだであるキャップ接着部材８で配線
用部材７に接着し、本発明によるパッケージを完成する
。A silicon chip 1 is bonded as a die-bonding member 2. The same number of wire bonding electrodes (chip side) 15 as wire bonding electrodes (substrate side) 13 are formed on the surface side of the silicon chip 1, and these are connected with wires 14, which are thin gold wires. . Finally, the sealing member 9
is adhered to the wiring member 7 using a cap adhesive member 8 made of gold-tin eutectic solder to complete the package according to the present invention.

この実施例の変形として、ＩＣ支持部材３をＳＩＣのみ
とする構成もありうる。この場合は、接着金属３０３を
省略でさる上にもともと８ＩＣは熱伝導率が大きいため
、熱的な性能は本実施例よりも優れるが、ＳＩＣの加工
が複雑に々る欠点がある。また、タングステンの代替材
料とＬ７ては、モリブデン、タングステ／と銅との合金
、銅と炭素の複合体、等の低熱膨張、高熱伝導絶縁材料
の他に。As a modification of this embodiment, there may be a configuration in which the IC support member 3 is made of only SIC. In this case, since the adhesive metal 303 is omitted and the 8IC has high thermal conductivity, the thermal performance is superior to that of this embodiment, but there is a drawback that the processing of the SIC is complicated. In addition, tungsten alternative materials include molybdenum, tungsten/copper alloys, copper-carbon composites, and other low thermal expansion, high thermal conductivity insulating materials.

ダイヤモンド、窒化アルミニウム、窒化はう素、等の低
熱膨張、高熱伝導絶縁材料も挙げられる。Also included are low thermal expansion, high thermal conductivity insulating materials such as diamond, aluminum nitride, boron nitride, and the like.

′また。アルミニウムと同様にセラミックスに対して活
性な金属である銅及び銅とシリコンの合金をアルミニウ
ム及びアルミニウム合金の代わりに使用する方法もあり
うる。この場合は加熱温度範囲が８２０Ｃを越え、１０
８３Ｃ未満となる。長所は耐熱温度がアルミニウムによ
る接着よりも約２５００高いことである。銅以外にはニ
ッケルが使える。ニッケルでは銅よりさらに高γ島にな
り。'Also. It is also possible to use copper and an alloy of copper and silicon, which are metals that are active toward ceramics like aluminum, instead of aluminum and aluminum alloys. In this case, the heating temperature range exceeds 820C and 10
It will be less than 83C. The advantage is that the heat resistance temperature is about 2,500 degrees higher than that of aluminum bonding. Nickel can be used instead of copper. Nickel has an even higher γ island than copper.

加熱温度範囲が１１５２Ｇを越え、　　１４５３ｔｌｌ
ｌ’未満となる。銅或いｉはニッケルを接着金［３０３
として用いた構成では、アルミニウムを用いた構成では
不可能な硬礒付け（作業湛ｉ：６（１０〜９ｎＯＵ）を
後工程に採用できることか最も顕著な特徴で、ちる。Heating temperature range exceeds 1152G, 1453tll
It becomes less than l'. Copper or i is nickel bonded with gold [303
The most notable feature of the structure used as a metal oxide film is that it is possible to use hard coating (work load i: 6 (10 to 9 nOU) in the subsequent process, which is impossible with a structure using aluminum).

また、ダイボンド部材２及び密閉用部材９の接着部材Ｂ
Ｖｉ本実施例のものである必要はなく、一般的なはんだ
材から適宜選んでよい。たたし、ダイボンド部材２の融
点はキャップ接！身部材８の作業湯度（通常融点より約
５ＤＣ高い）よりも高くなければならない。なぜをらば
密閉用部材９の接着時にダイボンド部材２か溶けてはい
けないからである。Moreover, the adhesive member B of the die bonding member 2 and the sealing member 9
Vi need not be the one used in this embodiment, and may be appropriately selected from general solder materials. However, the melting point of die bonding member 2 is the cap contact! It must be higher than the working temperature of the body part 8 (usually about 5 DC above the melting point). This is because the die-bonding member 2 must not melt when the sealing member 9 is bonded.

〔追加実施例〕[Additional examples]

将来は第４図から第６図に示すような、マルチチップ・
ビン・グリッド・アレーが現われることか予想され丞。In the future, multi-chip chips as shown in Figures 4 to 6 will be used.
It is expected that a bin grid array will appear.

第４図及び第５図の構造はある程度までの高密度化には
対応可能であるが、さらに密度が高くなると、第６図に
示すように複数個のチップを纏めて実装する必要が生じ
る。このような構造では、シリコンを含めて総ての構成
材料の熱膨張係数が近い値を持っていることが必須要件
となるので、本発明の構造は現状よりもづらに有効にな
る。The structures shown in FIGS. 4 and 5 can accommodate high density to a certain extent, but if the density increases further, it becomes necessary to mount a plurality of chips at once, as shown in FIG. 6. In such a structure, it is essential that all the constituent materials including silicon have similar coefficients of thermal expansion, so the structure of the present invention becomes more effective than the current situation.

〔発明の効果〕〔Effect of the invention〕

半導体基体を第１誘電体基板て固定し、該第１ｇ成体基
板を、外周部に該半導体基体を外部と電気的に結合する
ための端子群を配置した第２誘電体基板と機械的に結合
した半導体パンケージ構造体に於いて、第１誘電体基板
がシリコンに近い熱膨張係数を有する少なくとも炭化珪
素を含む一つ以上の材料で構成されていることにより、
熱抵抗が小さく、しかも、接続部分での熱膨張検数の差
が小さいために信頼性の高いパンケージ構造体が得られ
る。A semiconductor substrate is fixed to a first dielectric substrate, and the first g adult substrate is mechanically coupled to a second dielectric substrate, which has a group of terminals disposed on the outer periphery for electrically coupling the semiconductor substrate to the outside. In the semiconductor pancage structure, the first dielectric substrate is made of one or more materials containing at least silicon carbide having a coefficient of thermal expansion close to that of silicon,
A highly reliable pancage structure can be obtained because the thermal resistance is low and the difference in thermal expansion coefficients at the connecting portions is small.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明による一実施例を示す拡大断面図、第２
図は本発明が扱うパッケージの一般的構造を示す一部断
面斜視図、第３図は第２図の一部拡大断面図、第４図〜
第６図はマルチチップ構造に関する説、四回である。 １・・・７リコン・チップ、２・・・ダイボンド部材、
３・・・ＩＣ支持部材、３０１・・・ＳｉＣ部材、３０
２・・・タングステン部材、３０３・・・接着金属、４
・・・フィンの接着部材、５・・・空冷フィン、６・・
・接着部材。 ７・・・配線用部材、８・・・キャップ接着部材、９・
・・密閉用部材、１０・・・ビン、１１・・・導電路、
１３・・・ワイヤボンディング電極（基板側）、１４・
・・ワイヤ。 １４Ｉ・・・１列目のワイヤ、１４２・・・２タリ目の
ワイヤ、１５・・・ワイヤボンディング電極（チップ側
）。FIG. 1 is an enlarged sectional view showing one embodiment of the present invention, and FIG.
The figure is a partially sectional perspective view showing the general structure of the package handled by the present invention, FIG. 3 is a partially enlarged sectional view of FIG. 2, and FIGS.
Figure 6 is the fourth lecture on the multi-chip structure. 1...7 recon chip, 2...die bonding member,
3...IC support member, 301...SiC member, 30
2... Tungsten member, 303... Adhesive metal, 4
...Fin adhesive member, 5...Air cooling fin, 6...
・Adhesive parts. 7... Wiring member, 8... Cap adhesive member, 9...
... sealing member, 10 ... bottle, 11 ... conductive path,
13... wire bonding electrode (substrate side), 14...
...Wire. 14I... Wire in the first row, 142... Wire in the second row, 15... Wire bonding electrode (chip side).

Claims (1)

【特許請求の範囲】[Claims] １、半導体基体を第１誘電体基板に固定し、該第１誘電
体基板を、外周部に該半導体基体を外部と電気的に結合
するための端子群を配置した第２誘電体基板と機械的に
結合した半導体パッケージ構造体に於いて、特に該第１
誘電体基板がシリコンに近い熱膨張係数を有する少なく
とも炭化珪素を含む一つ以上の材料で構成されているこ
とを特徴とする炭化珪素を用いたパッケージ構造体。1. A semiconductor substrate is fixed to a first dielectric substrate, and the first dielectric substrate is connected to a second dielectric substrate in which a group of terminals for electrically connecting the semiconductor substrate to the outside is arranged on the outer periphery of the first dielectric substrate, and a machine. In a semiconductor package structure in which the first
1. A package structure using silicon carbide, wherein the dielectric substrate is made of one or more materials containing at least silicon carbide having a coefficient of thermal expansion close to that of silicon.
JP60233266A 1985-10-21 1985-10-21 Package structure employing silicon carbide Pending JPS6293960A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60233266A JPS6293960A (en) 1985-10-21 1985-10-21 Package structure employing silicon carbide

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60233266A JPS6293960A (en) 1985-10-21 1985-10-21 Package structure employing silicon carbide

Publications (1)

Publication Number Publication Date
JPS6293960A true JPS6293960A (en) 1987-04-30

Family

ID=16952390

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60233266A Pending JPS6293960A (en) 1985-10-21 1985-10-21 Package structure employing silicon carbide

Country Status (1)

Country Link
JP (1) JPS6293960A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01162353A (en) * 1987-12-18 1989-06-26 Fujitsu Ltd Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01162353A (en) * 1987-12-18 1989-06-26 Fujitsu Ltd Semiconductor device

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