JPH01162353A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH01162353A JPH01162353A JP62321804A JP32180487A JPH01162353A JP H01162353 A JPH01162353 A JP H01162353A JP 62321804 A JP62321804 A JP 62321804A JP 32180487 A JP32180487 A JP 32180487A JP H01162353 A JPH01162353 A JP H01162353A
- Authority
- JP
- Japan
- Prior art keywords
- recess
- substrate
- hole
- internal
- substrates
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 39
- 239000000758 substrate Substances 0.000 claims abstract description 51
- 238000000034 method Methods 0.000 abstract description 2
- 230000010485 coping Effects 0.000 abstract 1
- 238000012986 modification Methods 0.000 abstract 1
- 230000004048 modification Effects 0.000 abstract 1
- 239000000919 ceramic Substances 0.000 description 7
- 239000007788 liquid Substances 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 238000007747 plating Methods 0.000 description 4
- 229910017309 Mo—Mn Inorganic materials 0.000 description 1
- 229910000990 Ni alloy Inorganic materials 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 235000012771 pancakes Nutrition 0.000 description 1
- 238000007665 sagging Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Abstract
Description
【発明の詳細な説明】
〔概要〕
半導体装置に関し７
半導体素子のサイズ変更に対して柔軟に対応出来る構造
を有する多目的型半導体パンケージと。[Detailed Description of the Invention] [Summary] Relating to a semiconductor device 7. A multi-purpose semiconductor package having a structure that can flexibly respond to changes in the size of semiconductor elements.
それに素子を搭載した半導体装置を目的とし。It is intended for semiconductor devices equipped with elements.
（１）凹み（１）が形成された下段の基板（２）と、該
下段の基板表面に形成された複数の内部リ−Ｆ（３）よ
りなる下段の内部リード群と、前記凹みに対応する領域
に前記凹みより大きい孔を持ち且つ液孔が漸次大きく形
成された一個以上の基板からなる中段の基板（４）と、
該中段の基板の各表面に形成された複数の内部リード（
３）よりなる中段各層の内部リード群と、前記中段の基
板の最も大きい孔より更に大きい孔を持つ終段の基板（
５）とを有し、前記下段の基板、前記中段の基板５前記
終段の基板が積層され、且つ前記下段の内部リード群と
前記中段各層の内部リード群の内部リードが共通に外部
導出端子（６）に電気的に接続されてなることを特徴と
する半導体パッケージと。(1) A lower board (2) on which a recess (1) is formed, a lower internal lead group consisting of a plurality of internal leads (3) formed on the surface of the lower board, and a group corresponding to the recess. a middle substrate (4) consisting of one or more substrates having a hole larger than the recess in the area where the liquid hole is formed, and in which the liquid hole is formed to gradually become larger;
A plurality of internal leads (
3) a group of internal leads in each middle layer, and a final substrate having a hole larger than the largest hole in the middle substrate (
5), wherein the lower substrate, the middle substrate 5, the final substrate are stacked, and the internal leads of the lower internal lead group and the internal lead groups of each middle layer are commonly connected to external lead terminals. (6) A semiconductor package characterized by being electrically connected to.
（２）凹み（１）が形成された下段の基板（２）と、該
下段の基板表面に形成された複数の内部リード（３）よ
りなる下段の内部リード群と、前記凹みに対応する領域
に前記凹めより大きい孔を持ち且つ液孔が漸次大きく形
成された一個以上の基板からなる中段の基板（４）と、
該中段の基板の各表面に形成された複数の内部リード（
３）よりなる中段各層の内部リード群と、前記中段の基
板の最も大きい孔より更に大きい孔を持つ終段の基板（
５）とを有し、前記下段の基板、前記中段の基板、前記
終段の基板が積層され、且つ前記下段の内部リード群と
前記中段各層の内部リード群の内部リードが共通に外部
導出端子（６）に電気的に接続されていて、前記凹み（
１）に素子（７）が配設されてなるか、或いは前記凹み
（１）に底面を持ち、前記凹みより広い上面を前記孔内
に持つ素子搭載ブロック（８）の該上面に該上面より小
さい外形の素子（７）を搭載してなることを特徴とする
半導体装置をもって構成とする。(2) A lower substrate (2) on which a recess (1) is formed, a lower internal lead group consisting of a plurality of internal leads (3) formed on the surface of the lower substrate, and a region corresponding to the recess. a middle substrate (4) consisting of one or more substrates each having a hole larger than the recess and having liquid holes formed gradually larger;
A plurality of internal leads (
3) a group of internal leads in each middle layer, and a final substrate having a hole larger than the largest hole in the middle substrate (
5), wherein the lower board, the middle board, and the final board are stacked, and the internal leads of the lower internal lead group and the internal lead groups of each middle layer are commonly connected to external lead terminals. (6) and is electrically connected to the recess (
1) in which the element (7) is disposed, or the element mounting block (8) has a bottom surface in the recess (1) and an upper surface wider than the recess in the hole; The present invention is constituted by a semiconductor device characterized in that it is equipped with a small external element (7).
本発明は半導体装置に係り、特に半導体素子のナイズ変
更に対して柔軟に対応出来る構造を有する多目的型半導
体パッケージ及びそこに素子を搭載した半導体装置に関
する。The present invention relates to a semiconductor device, and more particularly to a multipurpose semiconductor package having a structure that can flexibly respond to changes in the size of a semiconductor element, and a semiconductor device in which the element is mounted.
半導体パッケージに関して従来よりセラミックパッケー
ジはその信頼性が高いことから高信頼度用途として多く
使用されている。しかし、セラミックパッケージはその
製造方法がグリーンシート積層焼成という高価な方法で
あり、また開発製造に要する期間が長いため、新品種開
発に対して大きなネックとなっていた。Regarding semiconductor packages, ceramic packages have traditionally been used for high reliability applications because of their high reliability. However, ceramic packages are manufactured using an expensive method of laminating and firing green sheets, and the time required for development and manufacturing is long, creating a major bottleneck in the development of new products.
特に、素子（チップ）のサイズが変わった時はパッケー
ジのキャビティ・サイズを変更し、新たにパンケージを
作り直す必要がある。即ち、同一のパンケージに搭載で
きる素子はワイヤボンディングのワイヤー長さの制限等
により、許容サイズが限定される。従って、これまで新
素子（新チップ）を開発するに際し、それに対応するバ
・７ケージも開発しなければならなかった。In particular, when the size of the element (chip) changes, it is necessary to change the cavity size of the package and rebuild a new pancage. That is, the allowable size of elements that can be mounted on the same pancage is limited due to restrictions on the length of wire bonding, etc. Therefore, when developing a new element (new chip), it has been necessary to develop a corresponding baggage.
第６図は従来の半導体装置である。多層セラミック・ブ
ロック内部の四角形の凹み１に素子７を配置し、素子７
と該ブロックの内部リード３をワイヤ９で結ぶ。該ブロ
ックの上部には気密封止キャンプ１０が取り付けられて
いる。FIG. 6 shows a conventional semiconductor device. The element 7 is placed in the rectangular recess 1 inside the multilayer ceramic block, and the element 7
and the internal lead 3 of the block are connected with a wire 9. A hermetically sealed camp 10 is attached to the top of the block.
しかし、ワイヤ同志の接近、垂れ下がり２曲がり等を避
けるため、ワイヤ長さは最長３ｍｍ位に制限される。ま
た、素子を四角形の凹みに信頼性よく搭載するためには
、凹みのサイズと素子のサイズの差は最低１龍必要であ
る。However, in order to avoid wires coming close to each other, sagging, and bending, the wire length is limited to a maximum of about 3 mm. Furthermore, in order to reliably mount an element in a rectangular recess, the difference between the size of the recess and the size of the element must be at least one.
従来は新素子（新チップ）の開発製造の度毎にかかるパ
ッケージも合わせて開発製造することが必要で、開発費
用と期間が大きな問題であった。Conventionally, it was necessary to develop and manufacture a package every time a new element (new chip) was developed and manufactured, and development costs and time were a major problem.
上記の問題に対処するため、素子のサイズが多少変化し
ても、同一パッケージで対応できる多目的型（汎用型）
半導体パッケージの開発が望まれ本発明の目的はかかる
多目的型（汎用型）半導体パッケージ及びそこに素子を
搭載した半導体装置を提供することにある。In order to address the above issues, a multi-purpose type (general-purpose type) that can be used in the same package even if the element size changes slightly.
The development of semiconductor packages is desired, and an object of the present invention is to provide such a multi-purpose (general-purpose) semiconductor package and a semiconductor device in which an element is mounted thereon.
第１図は本発明になる半導体パッケージ、第２図は本発
明になる半導体装置を示す。FIG. 1 shows a semiconductor package according to the invention, and FIG. 2 shows a semiconductor device according to the invention.
（１）凹み（１）が形成された下段の基板（２）と、該
下段の基板表面に形成された複数の内部リード（３）よ
りなる下段の内部リード群と、前記凹みに対応する領域
に前記凹みより大きい孔を持ち且つ液孔が漸次大きく形
成された一個以上の基板からなる中段の基板（４）と、
該中段の基板の各表面に形成された複数の内部リード（
３〉よりなる中段各層の内部リード群と、前記中段の基
板の最も大きい孔より更に大きい孔を持つ終段の基板（
５）とを有し、前記下段の基板、前記中段の基板、前記
終段の基板が積層され、且つ前記下段の内部リード群と
前記中段各層の内部リード群の内部リードが共通に外部
導出端子（６）に電気的に接続されてなる半導体パッケ
ージと。(1) A lower substrate (2) on which a recess (1) is formed, a lower internal lead group consisting of a plurality of internal leads (3) formed on the surface of the lower substrate, and an area corresponding to the recess. a middle substrate (4) consisting of one or more substrates each having a hole larger than the recess and having gradually larger liquid holes;
A plurality of internal leads (
3), and a final stage substrate (
5), wherein the lower board, the middle board, and the final board are stacked, and the internal leads of the lower internal lead group and the internal lead groups of each middle layer are commonly connected to external lead terminals. (6) A semiconductor package electrically connected to the semiconductor package.
（２）凹み（１）が形成された下段の基板（２）と、該
下段の基板表面に形成された複数の内部リード（３）よ
りなる下段の内部リード群と、前記凹みに対応する領域
に前記凹みより大きい孔を持ち且つ液孔が漸次大きく形
成された一個以上の基板からなる中段の基板（４）と、
該中段の基板の各表面に形成された複数の内部リード（
３）よりなる中段各層の内部リード群と、前記中段の基
板の最も大きい孔より更に大きい孔を持つ終段の基板（
５）とを有し、前記下段の基板、前記中段の基板、前記
終段の基板が積層され、且つ前記下段の内部リード群と
前記中段各層の内部リード群の内部リードが共通に外部
導出端子（６）に電気的に接続されていて、前記凹み（
１）に素子（７）が配設されてなるか、或いは前記凹み
（１）に底面を持ち、前記凹みより広い上面を前記孔内
に持つ素子搭載ブロック（８）の該上面に該上面より小
さい外形の素子（７）を搭載してなる半導体装置によっ
て上記問題点は解決される。(2) A lower substrate (2) on which a recess (1) is formed, a lower internal lead group consisting of a plurality of internal leads (3) formed on the surface of the lower substrate, and a region corresponding to the recess. a middle substrate (4) consisting of one or more substrates each having a hole larger than the recess and having gradually larger liquid holes;
A plurality of internal leads (
3) a group of internal leads in each middle layer, and a final substrate having a hole larger than the largest hole in the middle substrate (
5), wherein the lower board, the middle board, and the final board are stacked, and the internal leads of the lower internal lead group and the internal lead groups of each middle layer are commonly connected to external lead terminals. (6) and is electrically connected to the recess (
1) in which the element (7) is disposed, or the element mounting block (8) has a bottom surface in the recess (1) and an upper surface wider than the recess in the hole; The above-mentioned problems can be solved by a semiconductor device equipped with a small external element (7).
第２図において、半導体パッケージの内部に形成された
凹み１及び階段状の孔■、■等は各種サイズの素子を収
容するためのものである。素子搭載ブロック８ば各種サ
イズのものを準備しておき。In FIG. 2, a recess 1 and step-shaped holes (2), (2), etc. formed inside the semiconductor package are for accommodating elements of various sizes. Prepare element mounting blocks 8 of various sizes.
目的とする素子に応じて適当なものを選んで使用する。Select and use an appropriate one depending on the intended device.
即ち、目的とする素子よりやや広い上面を持つ素子搭載
ブロックで、素子と内部リードを結ぶワイヤの長さが３
１１以下となるようにし、しかも素子の両側は素子を信
頼性良く搭載するため。In other words, it is an element mounting block with a top surface slightly wider than the target element, and the length of the wire connecting the element and internal leads is 3.
11 or less, and in order to mount the elements with good reliability on both sides of the element.
１鶴以上の空きを有するような配置を選ぶ。Choose an arrangement that has at least one crane available.
素子７と内部リード３をワイヤ９でボンディングし、半
導体パッケージの上部に気密封止キャンプ１０を配して
半導体装置となる。The element 7 and the internal leads 3 are bonded with wires 9, and a hermetically sealed camp 10 is placed on the top of the semiconductor package to form a semiconductor device.
かくして、最下段の凹み（１’）より小さいサイズの素
子から中段の基板の最上段の孔よりやや小さいサイズの
素子に至るまで、各種サイズの素子の取り付けに応しる
半導体装置が実現する。In this way, a semiconductor device is realized that can accommodate elements of various sizes, from elements smaller than the bottom recess (1') to elements slightly smaller than the top hole of the middle substrate.
以下１図により本発明の実施例について説明するが１本
発明はこれに限るものでない。An embodiment of the present invention will be described below with reference to Figure 1, but the present invention is not limited thereto.
第１図に示すように、凹み１と■、■の如く階段状に孔
の形成された下段の基板２と中段の基板４と終段の基板
５からなる多層セラミック・ブロックに、各段毎に内部
リード３が形成され、この内部リードは積層セラミック
・ブロックの外側に取り付けられている外部導出端子４
に導通する。As shown in Fig. 1, a multilayer ceramic block consisting of a lower substrate 2, a middle substrate 4, and a final substrate 5 in which holes are formed in a step-like manner as indicated by recesses 1, An internal lead 3 is formed on the laminate, and this internal lead connects to an external lead terminal 4 attached to the outside of the laminated ceramic block.
conducts to.
内部リードのパターンの外部導出端子に導通する部分は
例えば第３図のような形状を持つ。The portion of the internal lead pattern that is electrically connected to the external lead-out terminal has a shape as shown in FIG. 3, for example.
第３図に示す如く、外部導出端子４の各端子間の間隔は
取扱いを容易にするため素子端子のそれよりも広げられ
、左右に分けて配置される。As shown in FIG. 3, the intervals between the external lead-out terminals 4 are wider than those of the element terminals to facilitate handling, and they are arranged separately on the left and right sides.
第４図に素子搭載ブロックを示す。図に示すように搭載
する素子のサイズに応じて各種のサイズの素子搭載ブロ
ックを用意する。図（ａ）は孔■用の１図（ｂ）は孔■
用の素子搭載ブロックである。Figure 4 shows the element mounting block. As shown in the figure, element mounting blocks of various sizes are prepared depending on the size of the element to be mounted. Figure (a) is for hole ■. Figure (b) is for hole ■.
This is an element mounting block for.
第５図に半導体パンケージ内の素子搭載プロソりの配置
を示す。図＜ａ＞は孔■用の２図（ｂ）は孔■用の素子
搭載ブロックの配置である。凹み１より小さい素子の場
合は素子搭載ブロックを使用せずに凹み１に直接素子を
配置する。素子サイズが凹み１と孔■の間にある素子に
対しては、孔■用の素子搭載ブロックを使用する。素子
サイズが更に大きくなり、孔■と孔■の間にある場合は
。FIG. 5 shows the arrangement of the device mounting prosthesis inside the semiconductor pancake. Figure <a> shows the arrangement of the element mounting block for the hole (2), and Figure (b) shows the arrangement of the element mounting block for the hole (2). In the case of an element smaller than recess 1, the element is placed directly in recess 1 without using an element mounting block. For an element whose element size is between recess 1 and hole (2), use the element mounting block for hole (2). If the element size becomes even larger and is located between holes ■ and holes ■.
孔■用の素子搭載ブロックを使用する。以下同様にして
、よりサイズの大きい素子に対処する。Use the element mounting block for hole ■. Thereafter, larger-sized elements are dealt with in the same manner.
以上述べたように素子搭載ブロックを用途によって選び
、それを凹み１の底面に接合しその上に素子を搭載する
。素子搭載ブロックに搭載された素子はワイヤ９で内部
リード３にボンディングされる。このようにして、各種
のサイズの素子搭載ブロックを用いるごとにより、同一
の半導体パッケージで、大小いろいろなサイズの素子に
対処することが出来る。As described above, an element mounting block is selected depending on the purpose, and it is bonded to the bottom of the recess 1, and the element is mounted on it. The elements mounted on the element mounting block are bonded to the internal leads 3 with wires 9. In this way, by using element mounting blocks of various sizes, the same semiconductor package can accommodate elements of various sizes.
素子搭載ブロックとして、金属製ブロックまたはセラミ
ック製ブロックを使用することが出来る。A metal block or a ceramic block can be used as the element mounting block.
金属製ブロックはｐｅ／Ｎｉ合金又はＭｏ等であり、
Ｎｉめっきの上に肋めっきを施す。このような金属性ブ
ロックを用いると、素子からの熱放散の点で有利である
。また、金属性ブロックを用い、その素子を搭載する上
面を第２図のように下の凹みより大きく形成する場合に
は、その凹みの周辺に形成された内部リードパターンに
金属性ブロックが接触しないように１例えば所定の隙間
が形成されるようにしなければならない。The metal block is made of pe/Ni alloy or Mo, etc.
Rib plating is applied on top of Ni plating. Use of such a metallic block is advantageous in terms of heat dissipation from the device. In addition, when using a metal block and forming the upper surface on which the element is mounted to be larger than the recess below as shown in Figure 2, the metal block does not come into contact with the internal lead pattern formed around the recess. For example, a predetermined gap must be formed.
セラミック製ブロックは上面及び下面にＭｏ−Ｍｎ又は
Ｗメタライズし、その上にＮｉめっき及び篩めっきを施
す。The ceramic block is metallized with Mo-Mn or W on the upper and lower surfaces, and Ni plating and sieve plating are applied thereon.
素子搭載ブロックは半導体パッケージの凹の１底部に高
融点はんだ等で蝋付は接合する。素子搭載ブロックの上
の素子はＡｕ／Ｓｉ反応により、またはＡｇペースト等
を使用して固着される。ワイヤはＡＩ線または篩線、
Ｃｕ線を使用する。The element mounting block is soldered to the bottom of the concave portion of the semiconductor package using high melting point solder or the like. The elements on the element mounting block are fixed by Au/Si reaction or by using Ag paste or the like. The wire is AI wire or sieve wire,
Use Cu wire.
小さな素子のワイヤボンディングは必要の数のみボンデ
ィングし、残りは未ボンディングのまま残す。For wire bonding of small elements, only the required number is bonded, and the rest are left unbonded.
上述の如く本発明によれば、一つの基本半導体パッケー
ジと各種サイズの素子搭載ブロックを製作して組合せる
ことにより、素子サイズの変更に対して柔軟に即応でき
る多目的型半導体パッケージを提供出来る。これにより
、パッケージ設計開発製作の期間及び費用の節約が大き
く、産業への寄与が大きい。As described above, according to the present invention, by manufacturing and combining one basic semiconductor package and element mounting blocks of various sizes, it is possible to provide a multipurpose semiconductor package that can flexibly respond to changes in element size. This greatly reduces the time and cost of package design, development, and production, and greatly contributes to industry.
第１図は半導体パンケージ。
第２図は半導体装置。
第３図は内部リードパターンと外部導出端子。
第４図は素子搭載ブロック。
第５図は素子搭載ブロックの配置。
第６図は従来の半導体装置
である。 図において。
１は凹み。
２は下段の基板。
３は内部リード。
４は中段の基板。
５は終段の基板。
６は外部導出端子、
７は素子。
８は素子搭載ブロック。
９はワイヤ。
１０は気密封止キャップ
Ａ−Ａ軒面図 Ａ−Ａ断面図
（６つ 孔 ■目可 （１）
ン 了し ■目］素子搭載ブロック
竿 ４ 目
（ρ）孔■甲
（Ｉ）） 孔 ■唱
従来の牛博９奎設置
４ζ ろ 〔］Figure 1 shows the semiconductor pancage. Figure 2 shows a semiconductor device. Figure 3 shows the internal lead pattern and external lead-out terminal. Figure 4 shows the element mounting block. Figure 5 shows the arrangement of the element mounting blocks. FIG. 6 shows a conventional semiconductor device. In fig. 1 is a dent. 2 is the lower board. 3 is an internal lead. 4 is the middle board. 5 is the final board. 6 is an external lead-out terminal, and 7 is an element. 8 is the element mounting block. 9 is a wire. 10 is the airtight sealing cap A-A eaves view A-A cross-sectional view (6 holes, eyes allowed (1)
[End ■] Element-mounted block rod 4th hole (ρ) hole ■Ko (I)) hole ■Cho Conventional Ushibo 9 Kyu installation 4ζ Ro []
Claims (2)
下段の基板表面に形成された複数の内部リード（３）よ
りなる下段の内部リード群と、前記凹みに対応する領域
に前記凹みより大きい孔を持ち且つ該孔が漸次大きく形
成された一個以上の基板からなる中段の基板（４）と、
該中段の基板の各表面に形成された複数の内部リード（
３）よりなる中段各層の内部リード群と、前記中段の基
板の最も大きい孔より更に大きい孔を持つ終段の基板（
５）とを有し、前記下段の基板、前記中段の基板、前記
終段の基板が積層され、且つ前記下段の内部リード群と
前記中段各層の内部リード群の内部リードが共通に外部
導出端子（６）に電気的に接続されてなることを特徴と
する半導体パッケージ。(1) A lower substrate (2) on which a recess (1) is formed, a lower internal lead group consisting of a plurality of internal leads (3) formed on the surface of the lower substrate, and an area corresponding to the recess. a middle substrate (4) consisting of one or more substrates each having a hole larger than the recess, and the hole being gradually enlarged;
A plurality of internal leads (
3) a group of internal leads in each middle layer, and a final substrate having a hole larger than the largest hole in the middle substrate (
5), wherein the lower board, the middle board, and the final board are stacked, and the internal leads of the lower internal lead group and the internal lead groups of each middle layer are commonly connected to external lead terminals. (6) A semiconductor package characterized by being electrically connected to.
下段の基板表面に形成された複数の内部リード（３）よ
りなる下段の内部リード群と、前記凹みに対応する領域
に前記凹みより大きい孔を持ち且つ該孔が漸次大きく形
成された一個以上の基板からなる中段の基板（４）と、
該中段の基板の各表面に形成された複数の内部リード（
３）よりなる中段各層の内部リード群と、前記中段の基
板の最も大きい孔より更に大きい孔を持つ終段の基板（
５）とを有し、前記下段の基板、前記中段の基板、前記
終段の基板が積層され、且つ前記下段の内部リード群と
前記中段各層の内部リード群の内部リードが共通に外部
導出端子（６）に電気的に接続されていて、前記凹み（
１）に素子（７）が配設されてなるか、或いは前記凹み
（１）に底面を持ち、前記凹みより広い上面を前記孔内
に持つ素子搭載ブロック（８）の該上面に該上面より小
さい外形の素子（７）を搭載してなることを特徴とする
半導体装置。(2) A lower substrate (2) on which a recess (1) is formed, a lower internal lead group consisting of a plurality of internal leads (3) formed on the surface of the lower substrate, and a region corresponding to the recess. a middle substrate (4) consisting of one or more substrates each having a hole larger than the recess, and the hole being gradually enlarged;
A plurality of internal leads (
3) a group of internal leads in each middle layer, and a final substrate having a hole larger than the largest hole in the middle substrate (
5), wherein the lower board, the middle board, and the final board are stacked, and the internal leads of the lower internal lead group and the internal lead groups of each middle layer are commonly connected to external lead terminals. (6) and is electrically connected to the recess (
1) in which the element (7) is disposed, or the element mounting block (8) has a bottom surface in the recess (1) and an upper surface wider than the recess in the hole; A semiconductor device characterized by being equipped with a small external element (7).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62321804A JP2535572B2 (en) | 1987-12-18 | 1987-12-18 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62321804A JP2535572B2 (en) | 1987-12-18 | 1987-12-18 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01162353A true JPH01162353A (en) | 1989-06-26 |
| JP2535572B2 JP2535572B2 (en) | 1996-09-18 |
Family
ID=18136599
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62321804A Expired - Lifetime JP2535572B2 (en) | 1987-12-18 | 1987-12-18 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2535572B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5828126A (en) * | 1992-06-17 | 1998-10-27 | Vlsi Technology, Inc. | Chip on board package with top and bottom terminals |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6293960A (en) * | 1985-10-21 | 1987-04-30 | Hitachi Ltd | Package structure employing silicon carbide |
-
1987
- 1987-12-18 JP JP62321804A patent/JP2535572B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6293960A (en) * | 1985-10-21 | 1987-04-30 | Hitachi Ltd | Package structure employing silicon carbide |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5828126A (en) * | 1992-06-17 | 1998-10-27 | Vlsi Technology, Inc. | Chip on board package with top and bottom terminals |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2535572B2 (en) | 1996-09-18 |
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