JPS6292429A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6292429A
JPS6292429A JP23240585A JP23240585A JPS6292429A JP S6292429 A JPS6292429 A JP S6292429A JP 23240585 A JP23240585 A JP 23240585A JP 23240585 A JP23240585 A JP 23240585A JP S6292429 A JPS6292429 A JP S6292429A
Authority
JP
Japan
Prior art keywords
film
single crystal
silicon
substrate
nitride film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP23240585A
Other languages
Japanese (ja)
Other versions
JPH0738408B2 (en
Inventor
Masayuki Takeda
正行 武田
Kunihiko Wada
邦彦 和田
Seiichiro Kawamura
河村 誠一郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP23240585A priority Critical patent/JPH0738408B2/en
Publication of JPS6292429A publication Critical patent/JPS6292429A/en
Publication of JPH0738408B2 publication Critical patent/JPH0738408B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Drying Of Semiconductors (AREA)
  • Element Separation (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

PURPOSE:To prevent cracks and crystal defects from being generated in the process of recrystallization, by exposing both sides of side walls on grooves formed in a silicon wafer to make single crystal silicon grow on the single crystal. CONSTITUTION:A number of parallel groove 12 partitioned by side walls 13 are formed in a silicon wafer 11. A silicon nitriding film 14 and an SiO2 film 15, which are sued as masks during formation of the grooves, are left as they are, and a nitriding film 16 is made to grow all over the surface, and then the nitriding film 16 is left on only sides walls 13 on the grooves. And, the bottom surface of the groves are oxidized to form an insulating film 17, whose thickness T has a relation W/2<=T with width W of the side wall on the grooves. Then, the nitriding film 16, SiO2 film 15, and nitriding film 14 are removed and a single crystal silicon 18 is made to grow all over the surface so that a desirable isolation layer 19 is formed to make element-formation region 20. Hence, single crystal silicon, in which cracks and crystal defects are prevented from invading the insulating film, can be formed.

Description

【発明の詳細な説明】 〔概要〕 絶縁膜上に単結晶シリコンを形成するシリコン・オン・
インシユレータ(Silicon on In5ula
tor+SOI )技術の改良である。
[Detailed Description of the Invention] [Summary] A silicon-on-silicon method that forms single crystal silicon on an insulating film.
Insulator (Silicon on In5ula)
tor+SOI) technology.

[産業上の利用分野〕 本発明は半導体装置の製造方法に関するもので、更に詳
しく言えば、選択エピタキシャル成長技術を使用し、側
壁からエピタキシャル成長(エビ成長)することにより
絶縁膜上に単結晶を成長する技術に関するものである。
[Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device. More specifically, the present invention relates to a method for manufacturing a semiconductor device. More specifically, a selective epitaxial growth technique is used to grow a single crystal on an insulating film by epitaxial growth (epitaxial growth) from the sidewall. It's about technology.

〔従来の技術〕[Conventional technology]

シリコンウェハ上に酸化膜〔二酸化シリコン(S’r0
2)膜〕・を形成し、その上に多結晶シリコン(ポリシ
リコン)を成長し、レーザアニールでポリシリコンを溶
融し、再結晶化して5iO2N上に単結晶シリコンを形
成する501と呼称される技術は知れらている。
Oxide film [silicon dioxide (S'r0
2) Form a film], grow polycrystalline silicon (polysilicon) on it, melt the polysilicon by laser annealing, and recrystallize it to form single crystal silicon on 5iO2N.It is called 501. The technology is known.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上記した技術において、再結晶後に単結晶シリコンにク
ランクや結晶欠陥が発生することがあって、絶縁膜上に
単結晶シリコンを形成することはきわめ電離しい。
In the above-mentioned technique, cranks and crystal defects may occur in single crystal silicon after recrystallization, and it is extremely difficult to form single crystal silicon on an insulating film.

本発明はこのような点に鑑みて創作されたもので、絶縁
膜上にクランクや結晶欠陥の入らない単結晶シリコンを
形成する技術に関するものである。
The present invention was created in view of these points, and relates to a technique for forming single crystal silicon without cracks or crystal defects on an insulating film.

〔問題点を解決するための手段〕[Means for solving problems]

第1図ialないしIg+は本発明方法を実施する工程
における本発明実施例の断面図、第2図は前記実施例の
平面図である。
FIGS. 1 ial to Ig+ are cross-sectional views of an embodiment of the present invention in the process of carrying out the method of the present invention, and FIG. 2 is a plan view of the embodiment.

本発明実施例においては、シリコンウェハ11に側壁1
3で区切られた複数の平行な満13を形成し、この溝の
形成においてマスクとし′ζ用いたシリコン窒化膜(S
i3N、lI’ll、以下窒化膜という)14と5i0
2膜15はそのまま残し、全面に窒化111i16を成
長し、溝の側壁13上にのみ窒化膜16を残し、溝の底
面を酸化して厚さ′「が溝の側壁の幅Wに対しW/2<
Tの関係にある絶縁膜17を形成し、次いで窒化膜16
.5i02欣15、窒化膜14を除去し、全面に単結晶
シリコン、1日を成長し、所望のアイソレーション層(
分離11)+9を形成し素子形成領域20を作る。
In the embodiment of the present invention, a side wall 1 is attached to a silicon wafer 11.
A silicon nitride film (S) was used as a mask in forming the grooves.
i3N, lI'll, hereinafter referred to as nitride film) 14 and 5i0
2 film 15 is left as it is, nitride film 111i16 is grown on the entire surface, the nitride film 16 is left only on the side wall 13 of the trench, and the bottom surface of the trench is oxidized so that the thickness '' is W// with respect to the width W of the side wall of the trench. 2<
An insulating film 17 having a relationship of T is formed, and then a nitride film 16 is formed.
.. 5i02 15, nitride film 14 is removed, single crystal silicon is grown on the entire surface for 1 day, and a desired isolation layer (
Isolation 11)+9 is formed to form an element formation region 20.

〔作用〕[Effect]

上記方法においては、シリコンウェハにJF[した溝と
側壁を利用し、側壁の両側を露出してその単結晶上に単
結晶シリコンを成長するので、従来のSOI技術におけ
る如くアニールすることがないので、従来の再結晶化工
程におけるクランクや結晶欠陥の発生が防止されるので
ある。   ゛〔実施例〕 以下、図面を参照して本発明実施例を詳細に説明する。
In the above method, the grooves and sidewalls formed by JF in the silicon wafer are used, and both sides of the sidewalls are exposed and single crystal silicon is grown on the single crystal, so there is no need for annealing as in conventional SOI technology. This prevents the occurrence of cracks and crystal defects in the conventional recrystallization process.゛[Embodiments] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

第1図(a)参照: 半導体基板例えばウェハ11上に窒化膜14、SiO2
膜15膜形5し、これらの膜をパターニングし、第1図
に示される如く窒化膜14、SiO+膜15をマスクに
して側壁13の間に溝12を形成する。前記した工程は
第2図の平面図に部分的に示される如く、ウェハ11に
複数の平行な溝12を形成することによってなされる。
See FIG. 1(a): A nitride film 14, SiO2 on a semiconductor substrate, for example, a wafer 11.
The film 15 is formed into a film shape 5, and these films are patterned to form a groove 12 between the side walls 13 using the nitride film 14 and the SiO+ film 15 as a mask, as shown in FIG. The process described above is accomplished by forming a plurality of parallel grooves 12 in wafer 11, as partially shown in the plan view of FIG.

溝の幅りは5〜30μm1深さHは約2μm、側壁の幅
Wは1.0μm程度に設定するが、本発明実施例におい
て溝の幅D°は6μmとした。  ゛ 第1図(bl参照: 次に、全面に窒化膜16を2000人の膜厚に成長する
The width of the groove is set to 5 to 30 μm, the depth H is set to about 2 μm, and the width W of the side wall is set to about 1.0 μm. In the embodiment of the present invention, the width D° of the groove is set to 6 μm. 1 (see BL) Next, a nitride film 16 is grown on the entire surface to a thickness of 2000 nm.

第1図(C1参照: 次いで、異方性エツチングで側壁の上部と溝12の底面
上の窒化膜を除去する。異方性エツチングでは、平坦な
面上の窒化膜が均一にエツチングされるので、溝の底面
上の窒化11ii16が除去されウェハが露出された後
でも側壁13の両側面上には窒化II!16が残ってい
る。
FIG. 1 (see C1: Next, the nitride film on the top of the sidewall and the bottom of the groove 12 is removed by anisotropic etching. With anisotropic etching, the nitride film on the flat surface is etched uniformly. Even after the nitride 11ii16 on the bottom of the trench is removed and the wafer is exposed, nitride II!16 remains on both sides of the sidewall 13.

第1図(dl参照: 次に、熱酸化によって底面の露出したウェハ表面を酸化
してSIO+の絶縁膜17を形成する。このとき、側壁
13の表面は全面が窒化膜で覆われているので酸化され
ないが、側壁の基部で図示の如くS’i 0’2膜が連
続するように(切れ目が発生“しないように)、絶縁膜
の最も厚い中央部分の厚さTは、側壁の幅Wに対しW/
2<Tなる条件を満足するように酸化する。
FIG. 1 (see dl: Next, the wafer surface with the exposed bottom is oxidized by thermal oxidation to form the SIO+ insulating film 17. At this time, since the entire surface of the side wall 13 is covered with a nitride film, Although not oxidized, the thickness T of the thickest central portion of the insulating film is equal to the width W of the sidewall so that the S'i 0'2 film is continuous as shown in the figure at the base of the sidewall (so that no cuts occur). Against W/
Oxidize to satisfy the condition 2<T.

第1図tel参照: 次に、りん酸ボイルで側壁上の窒化膜16を除去し、次
いで5i02膜15、窒化膜14を除去し、側壁13を
露出する。
Refer to FIG. 1, tel: Next, the nitride film 16 on the sidewalls is removed using phosphoric acid boiling, and then the 5i02 film 15 and nitride film 14 are removed to expose the sidewalls 13.

第1図(fl参照: 次いで、SiHα3ガスを用い、数十Torrの真空内
で、900℃〜1000℃の温度で選択エビ成長を行う
と、側壁13の両側上の露出したシリコン面から横方向
へも単結晶シリコン18が成長される。本発明実施例で
は、溝の幅を5μmにして単結晶シリコンを側壁13上
に4.8〜5,5μmの厚さに成長し、溝13を単結晶
シリコンで完全に埋めただけでなく、単結晶シリコン表
面もほぼ平坦に形成した。単結晶シリコン表面に多少の
凹凸がある場合、それは表面のみをレーザアニールで溶
融するか、または熔融後ドライエツチングまたはポリッ
シングをなして平坦化し、しかる後に所望の厚さまでコ
ントロールエソチンクラ行つ。
FIG. 1 (see fl: Next, selective shrimp growth is performed using SiHα3 gas at a temperature of 900°C to 1000°C in a vacuum of several tens of Torr. In the embodiment of the present invention, the width of the groove is 5 μm, and single crystal silicon is grown on the side wall 13 to a thickness of 4.8 to 5.5 μm. Not only was it completely filled with crystalline silicon, but the single-crystal silicon surface was also made almost flat.If the single-crystal silicon surface has some unevenness, it can be solved by melting only the surface with laser annealing or by dry etching after melting. Alternatively, it can be polished and flattened, followed by a controlled etching process to the desired thickness.

第1図fgl参照: 次いで、例えば選択酸化法(LOGO3)で所望のアイ
ソレーション[19を形成し、絶縁膜で囲まれた素子形
成領域20を作る。
Refer to FIG. 1fgl: Then, a desired isolation [19] is formed by, for example, selective oxidation (LOGO3) to form an element formation region 20 surrounded by an insulating film.

〔発明の効果〕〔Effect of the invention〕

以上述べてきたように、本発明によれば、絶縁膜上に単
結晶シリコンを形成することによりSOI技術をデバイ
スに実現できるとともに、ビームアニール法に比べ再現
性の良い単結晶シリコンを形成でき、本発明の方法は、
CMO3,バイポーラデバイス等へと広範囲に応用可能
である。
As described above, according to the present invention, SOI technology can be realized in devices by forming single crystal silicon on an insulating film, and single crystal silicon can be formed with better reproducibility than beam annealing method. The method of the present invention includes:
It can be widely applied to CMO3, bipolar devices, etc.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(alないしくglは本発明実施例断面図、第2
図は本発明実施例の平面図である。 第1図と第2図において、 11はウェハ、 12は溝、 13は側壁、 14は窒化膜、 15は SiO2膜、 16は窒化膜、 17は 5i02膜、 18は単結晶シリコン、 19はアイソレーション1−1 l   (8) 20は素子形成領域である。 4ζ発!Ilf 惨〔北l砂り☆11−5ムP2A;噌
く、@ep+@ リyl イp+qhrfB第2図 $を朗を艶I]ダ面ヱ 第1図
Figure 1 (al or gl is a sectional view of an embodiment of the present invention,
The figure is a plan view of an embodiment of the present invention. In Figures 1 and 2, 11 is a wafer, 12 is a groove, 13 is a side wall, 14 is a nitride film, 15 is a SiO2 film, 16 is a nitride film, 17 is a 5i02 film, 18 is single crystal silicon, and 19 is an isolator. ration 1-1 l (8) 20 is an element formation region. 4ζ departure! Ilf misery [Kita l sand ☆ 11-5mu P2A; 噌く, @ep+@ りyl ip+qhrfB 2nd figure $ wo wo wo I] Damen ヱ 1st figure

Claims (2)

【特許請求の範囲】[Claims] (1)半導体基板(11)上に形成したシリコン窒化膜
(14)、絶縁膜(15)をパターニングして得られた
膜をマスクにして該基板(11)に側壁(13)で分離
された溝(12)を形成する工程、 該基板(11)全面上にシリコン窒化膜(16)を成長
する工程、 異方性エッチングで窒化膜(16)を側壁(13)上に
は残存するが溝の底面では該基板(11)を露出する如
くにエッチングする工程、 露出した該基板(11)の表面を酸化して該基板(11
)表面に絶縁膜(17)を形成する工程、側壁(13)
の両側に残ったシリコン窒化膜(16)を除去する工程
、 選択エピタキシャル成長で単結晶シリコンを側壁(13
)の横方向へも成長し溝(13)を単結晶シリコンで埋
めることを特徴とする半導体装置の製造方法。
(1) Using the film obtained by patterning the silicon nitride film (14) and insulating film (15) formed on the semiconductor substrate (11) as a mask, the semiconductor substrate (11) is separated by the sidewall (13). A step of forming a groove (12), a step of growing a silicon nitride film (16) on the entire surface of the substrate (11), a step of anisotropic etching to leave the nitride film (16) on the sidewalls (13) but forming the groove. etching the substrate (11) to expose the bottom surface of the substrate (11); and oxidizing the exposed surface of the substrate (11) to expose the substrate (11).
) Step of forming an insulating film (17) on the surface, side wall (13)
Step of removing the silicon nitride film (16) remaining on both sides of the single crystal silicon by selective epitaxial growth.
) is also grown in the lateral direction to fill the groove (13) with single crystal silicon.
(2)前記側壁(13)の幅をW、絶縁膜(17)の最
も厚い部分の厚さをTとしたとき、 W/2<T なる条件を満足する如くに該基板(11)を酸化するこ
とを特徴とする特許請求の範囲第1項記載の方法。
(2) Oxidize the substrate (11) to satisfy the following condition: W/2<T, where W is the width of the side wall (13) and T is the thickness of the thickest part of the insulating film (17). A method according to claim 1, characterized in that:
JP23240585A 1985-10-18 1985-10-18 Method for manufacturing semiconductor device Expired - Lifetime JPH0738408B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23240585A JPH0738408B2 (en) 1985-10-18 1985-10-18 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23240585A JPH0738408B2 (en) 1985-10-18 1985-10-18 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPS6292429A true JPS6292429A (en) 1987-04-27
JPH0738408B2 JPH0738408B2 (en) 1995-04-26

Family

ID=16938727

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23240585A Expired - Lifetime JPH0738408B2 (en) 1985-10-18 1985-10-18 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JPH0738408B2 (en)

Also Published As

Publication number Publication date
JPH0738408B2 (en) 1995-04-26

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