JPS6290956A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPS6290956A
JPS6290956A JP60229948A JP22994885A JPS6290956A JP S6290956 A JPS6290956 A JP S6290956A JP 60229948 A JP60229948 A JP 60229948A JP 22994885 A JP22994885 A JP 22994885A JP S6290956 A JPS6290956 A JP S6290956A
Authority
JP
Japan
Prior art keywords
pad
integrated circuit
input
ground potential
power supply
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60229948A
Other languages
Japanese (ja)
Inventor
Minoru Hori
堀　稔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to JP60229948A priority Critical patent/JPS6290956A/en
Publication of JPS6290956A publication Critical patent/JPS6290956A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Abstract

PURPOSE:To reduce the size of a package size by connecting a pad not connected to an external circuit for producing an input/output signal by the formation of an integrated circuit with a ground potential pad or a power potential pad. CONSTITUTION:An input/output signal producing pad C of the periphery of a chip is interposed between a power potential pad B and a ground potential pad A. A ground potential line LA is provided inside the pad row, and a power potential line LB is provided outside the pad row through an insulating layer on a substrate 1. The pad B is connected through a connecting wire 3 to the line LB, and the pad A is connected through a connecting wire 2 to the line LA. Accordingly, the unnecessary pad C is wired by wire bonding L with Al or Au wire with the pad B or A, and the pad C is not wired with the pin of a package. Thus, the package may have pins of the number corresponding to the pad C for producing the input/output signals.

Description

【発明の詳細な説明】 〈産業上の利用分野〉 本発明は半導体集積回路の改良に係わる。[Detailed description of the invention] <Industrial application field> The present invention relates to improvements in semiconductor integrated circuits.

〈従来の技術〉 シリコン集積回路において、同一チップ上に多用途回路
を形成し、用途に応じてそのうちの一部の回路のみを使
用したい場合がある。<Prior Art> In silicon integrated circuits, there are cases in which multipurpose circuits are formed on the same chip and it is desired to use only some of the circuits depending on the purpose.

このような場合、使用しない回路の入出力端子も、回路
を浮かしておくわけにいかないので、用途により不要な
入出力信号、ｅラドを、′ｅツケージのぎンにワイヤゼ
ンデイングし、ノぐツケージのピンを介して外部回路で
電源電位あるいはグランド電位にプルアップあるいはプ
ルダウンしている。In such a case, the input/output terminals of unused circuits cannot be left floating, so depending on the application, unnecessary input/output signals and e-rads may be wire-ended to the gate of the cage. It is pulled up or down to the power supply potential or ground potential by an external circuit via the pin of the device cage.

〈発明が解決しようとする問題点〉 従って、シリコン集積回路等の集積回路チップをノセツ
ケージするには、チップの全入出力信号パッド数に相当
する数のピンをもつノぞッケージに実装されるため、ノ
ぐツケージが大きくなりコストアップとなる欠点があっ
た。<Problems to be Solved by the Invention> Therefore, in order to install an integrated circuit chip such as a silicon integrated circuit, it is necessary to mount it on a chip cage that has a number of pins equivalent to the total number of input/output signal pads of the chip. However, there was a drawback that the cage became large and the cost increased.

またチップのパッドとパッケージのビンの間をゼンデイ
ングワイヤで全て接続せねばならず、さらにノぞツケー
ジのビンを外部回路で電源電位あるいはグランド電位に
接続せねばならず作業工程が嵩み不経済であった。In addition, all connections between the pads of the chip and the vias of the package must be made using winding wires, and the vias of the slot cage must be connected to the power supply potential or ground potential using an external circuit, which increases the work process and makes it uneconomical. Met.

本発明はかかる従来技術の欠点に鑑みてなされたもので
、所望の回路の形成に応じて、必要となる入出力信号ノ
ミラド数に対応して、相当のピンを有するパッケージを
用いることができ、小型化され、かつ経済的な半導体集
積回路を提供するととを目的としている。The present invention has been made in view of the drawbacks of the prior art, and it is possible to use a package having a considerable number of pins corresponding to the number of required input/output signals depending on the formation of a desired circuit. The purpose is to provide a compact and economical semiconductor integrated circuit.

く問題点を解決するための手段〉 かかる目的を達成した本発明による半導体集積回路の構
成は、集積回路が形成されたチップの周囲に配列された
上記集積回路の入出力信号取出し用パッドと、上記集積
回路の外周に上記集積回路を取り巻いて配置されたグラ
ンド電位ライン並びに電源電位ラインと、上記入出力信
号取出し用、９ツドをはさんで配置された、グランＦ電
位、Ｏツド並びに電源を位パッドとからなり、上記集積
回路の回路形成によシ外部回路に接続されない上記入出
力信号取出し用パッドは、上記グランド電位パッドある
いは電源電位パッドに接続しておくことを特徴とするも
のである。Means for Solving the Problems> The structure of a semiconductor integrated circuit according to the present invention that achieves the above object includes pads for taking out input/output signals of the integrated circuit arranged around a chip on which the integrated circuit is formed; A ground potential line and a power supply potential line are arranged around the integrated circuit on the outer periphery of the integrated circuit, and a ground F potential, an O terminal and a power supply are arranged across the nine terminals for taking out the input/output signals. The input/output signal extraction pad, which is not connected to an external circuit during circuit formation of the integrated circuit, is connected to the ground potential pad or power supply potential pad. .

く実　施　例〉 本発明による半導体集積回路の一実施例を図面を参照し
て説明する。Embodiment One embodiment of a semiconductor integrated circuit according to the present invention will be described with reference to the drawings.

図は本発明による半導体集積回路の一部分の平面図を示
す。本発明の半導体集積回路は、シリコン等の基板１の
上に形成された集積回路　には一般に基本回路方式を採
用されているため、目的の回路によって、所定の入出力
信号取出し用ノクツドのみが外部回路に接続され、その
他の不要人出力信号取出し用ノミラドは、電源電位かグ
ランド電位に接続される必要がある。本発明によるもの
では、チップ周辺の入出力信号取出し用パッドＣをはさ
んで電源電位パッドＢとグランド電位パッドＡが配置さ
れている。また、これらのｉｉミツドの内側にグランド
電位ラインＬＡ、パッド列の外側に電源電位ラインＬＢ
が基板１上に絶縁層を介して設けられている。電源電位
ノミラドＢは接続線３を介して電源電位ラインＬＢに、
グランド電位パッドＡは接続線２を介してグランド電位
ラインＬＡに接続されている。従って集積回路が所定の
回路に形成される際、不要の入出力信号取出し用パッド
Ｃはそれぞれ必要に応じて、電源電位パッドＢあるいは
グランド電位ノぐツドハにｈｔ　ｔたはＡｕのワイヤー
でワイヤボンディングによって結線される。このなめ、
不要の入出力信号取出し用パッドＣはノぐツケージのビ
ンとは結線されない。従ってノぐツケージは必要人出力
信号取出し用パッドＣに対応した数のビンを持つものを
使えばよく、従来の場合の如く、チップの全入出力信号
取出し用パッドに相当するピンをもつノぐツケージを使
用する必要がなくなシ、パッケージが構造的に小型化さ
れるとともに、ワイヤボンディング作業等も著しく簡素
化された。The figure shows a plan view of a portion of a semiconductor integrated circuit according to the invention. In the semiconductor integrated circuit of the present invention, since a basic circuit system is generally adopted for the integrated circuit formed on the substrate 1 of silicon or the like, only the designated input/output signal extraction nodes may be externally connected depending on the target circuit. The Nomurad connected to the circuit and used to extract other unnecessary output signals must be connected to the power supply potential or ground potential. In the device according to the present invention, a power supply potential pad B and a ground potential pad A are placed across a pad C for taking out input/output signals around the chip. In addition, a ground potential line LA is placed inside these ii middles, and a power supply potential line LB is placed outside the pad row.
is provided on the substrate 1 with an insulating layer interposed therebetween. The power supply potential Nomurad B is connected to the power supply potential line LB via the connection line 3,
Ground potential pad A is connected to ground potential line LA via connection line 2. Therefore, when an integrated circuit is formed into a predetermined circuit, unnecessary input/output signal extraction pads C are wire-bonded to the power supply potential pad B or the ground potential node using htt or Au wires, as necessary. Connected by. This lick,
The pad C for taking out unnecessary input/output signals is not connected to the bottle of the gauge cage. Therefore, it is sufficient to use a nozzle cage that has the number of pins corresponding to the pads C for extracting output signals of the required person. There is no need to use a package, the package is structurally more compact, and wire bonding work is also significantly simplified.

〈発明の効果〉 本発明による半導体集積回路によれば、集積回路チップ
の周囲に配列された入出力信号取出し用パッドをはさん
で電源電位パッド、グランド電位パッドが設けられ、さ
らにこれらパッドの例えば内側にグランド邂位ライン、
外側に電源電位ラインが配線され、電源電位パッドは電
源電位ラインに、又、グラン）′電位Ａツドはグランド
電位パラＦにそれぞれ結線されている◇従って、集積回
路の回路形成に当って、不要な入出力信号取出し用パッ
ドは電源電位パッドあるいはグランド電位ノミラドにワ
イヤボンディングしてゾルアップあるいはプルダウンで
きる。従来のものの如く不要の入出力信号取出し用パッ
ドまでパッケージのピンとワイヤボンディングして外部
回路でプルアップあるいはプルダウンの配線をするとい
った処理が全く不用になった。従ってパッケージも必要
人出力信号取出し用パッドに相当するビン数のパッケー
ジでよいためパッケージサイズが著しく小型化された。<Effects of the Invention> According to the semiconductor integrated circuit according to the present invention, a power supply potential pad and a ground potential pad are provided across the input/output signal extraction pads arranged around the integrated circuit chip, and further, for example, Grand Nii line on the inside,
A power supply potential line is wired on the outside, and the power supply potential pad is connected to the power supply potential line, and the ground potential A is connected to the ground potential Para F. ◇Therefore, when forming an integrated circuit circuit, unnecessary The pad for taking out input/output signals can be wire-bonded to the power supply potential pad or the ground potential Nomurad for sold-up or pull-down. The conventional process of wire bonding unnecessary input/output signal extraction pads to package pins and wiring for pull-up or pull-down using an external circuit is completely unnecessary. Therefore, the package size can be significantly reduced because the number of bins required for the package is equivalent to the number of pads for extracting output signals from the required person.

また不要人出力信号取出し用パッドとビンとのワイヤボ
ンディング及びこれに係わるゾルアップ。Also, wire bonding between the unwanted output signal extraction pad and the bottle, and related sol-up.

プルダウンの配線も不用とな、シ製造作業が著しく簡単
化され、従ってコストダウンが可能となった。There is no need for pull-down wiring, which greatly simplifies the manufacturing process, making it possible to reduce costs.

【図面の簡単な説明】[Brief explanation of drawings]

図は本発明による半導体集積回路の部分的平面図である
。 図　　面　　中、 】は基板、 ２．３は接続線、 Ａはグランド電位パッド、 Ｂは電源電位パラＦ１ Ｃは入出力信号取出し用パラＦ１ ＬＡはグランド電位ライン、 ＬＢは電源電位ラインである。The figure is a partial plan view of a semiconductor integrated circuit according to the present invention. In the figure, ] is the board, 2.3 is the connection line, A is the ground potential pad, B is the power supply potential para F1, C is the input/output signal extraction para F1, LA is the ground potential line, and LB is the power supply potential line.

Claims (1)

【特許請求の範囲】[Claims] 集積回路が形成されたチップの周囲に配列された上記集
積回路の入出力信号取出し用パッドと、上記集積回路の
外周に、上記集積回路を取り巻いて配置されたグランド
電位ライン並びに電源電位ラインと、上記入出力信号取
出し用パツドをはさんで配置された、グランド電位パツ
ド並びに電源電位パッドとからなり、上記集積回路の回
路形成によつて外部回路に接続されない上記入出力信号
取出し用パッドは、上記グランド電位パッドあるいは電
源電位パッドに接続されることを特徴とする半導体集積
回路。pads for taking out input/output signals of the integrated circuit arranged around a chip on which the integrated circuit is formed; a ground potential line and a power supply potential line arranged around the integrated circuit on the outer periphery of the integrated circuit; It consists of a ground potential pad and a power supply potential pad placed across the input/output signal extraction pad, and the input/output signal extraction pad that is not connected to an external circuit due to the circuit formation of the integrated circuit is A semiconductor integrated circuit characterized in that it is connected to a ground potential pad or a power supply potential pad.
JP60229948A 1985-10-17 1985-10-17 Semiconductor integrated circuit Pending JPS6290956A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60229948A JPS6290956A (en) 1985-10-17 1985-10-17 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60229948A JPS6290956A (en) 1985-10-17 1985-10-17 Semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS6290956A true JPS6290956A (en) 1987-04-25

Family

ID=16900226

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60229948A Pending JPS6290956A (en) 1985-10-17 1985-10-17 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS6290956A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6509628B2 (en) 2001-04-02 2003-01-21 Fujitsu Limited IC chip
EP1179848A3 (en) * 1989-02-14 2005-03-09 Koninklijke Philips Electronics N.V. Supply pin rearrangement for an I.C.

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1179848A3 (en) * 1989-02-14 2005-03-09 Koninklijke Philips Electronics N.V. Supply pin rearrangement for an I.C.
US6509628B2 (en) 2001-04-02 2003-01-21 Fujitsu Limited IC chip

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