JPS6290774A - Peak voltage holding circuit - Google Patents

Abstract

PURPOSE:To obtain a rapid response always constant regardless of the level of an input voltage by charging a capacitor with constant current by the output from a transistor differential switching circuit in case when the external input voltage is higher than the potential of the capacitor terminal. CONSTITUTION:When the input voltage goes to higher than the output voltage, the output from a comparator turns a transistor 4 ON, so that the capacitor 2 is charged with constant current by the output current from the transistor 4. And the output voltage rises linearly as time lapses. When the output voltage reaches a level equal to that of the input voltage, the output from a voltage comparator 1 turns the transistor 4 OFF terminating the charging of the capacitor 2. As a result, the response level is made at all time constant regardless of the level of the input voltage, and the constant current can be optionally set by means of a constant current element 5. Therefore, the response is speeded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to improving the response time of a peak voltage holding circuit.

[Background of the invention]

As a method of improving the response time of a peak voltage holding circuit, for example, as shown in Japanese Patent Publication No. 59-47399, there is a method of using an analog switch to control charging of a signal voltage holding capacitor and charging the capacitor with a constant voltage. However, since analog switches have switch resistance when they are turned on, they have the disadvantage that the response time changes significantly depending on the level of external input voltage.

[Purpose of the invention]

An object of the present invention is to provide a peak voltage holding circuit whose response time does not change depending on the level of input voltage and whose response is fast.

[Summary of the invention]

An example of a conventional peak voltage holding circuit is shown in FIG. This is because when a voltage higher than the output is input, the output of the voltage comparator 1 turns on the analog switch 3, and the capacitor 2 charges. As the capacitor 2 is charged, the output voltage increases, and as a result, when the output voltage reaches the same level as the input voltage, the voltage comparator output turns off the analog switch 3, and the charging of the capacitor 2 ends.

In the above capacitor charging process, the output voltage E. is the ON resistance (r) of the analog switch.

Since the capacitor (C) integrates the voltage VDD, E,=VI)I,(1-e '')
In the curve, the output voltage increases over time until the input voltage becomes equal to the input voltage, but if E is a sufficiently lower voltage than vD, then it increases linearly with respect to time t. On the other hand, Eo is vI. If the voltage is close to , the time it takes to finish charging the capacitor will be long and the response will be slow.As explained above, the example in Figure 3 has the disadvantage that the response time will vary greatly depending on the input voltage. .

The present invention aims to eliminate this drawback, and by charging the capacitor 2 with a constant current, a constant and high-speed response is always obtained regardless of the level of the input voltage.

[Embodiments of the invention] Embodiments of the present invention will be described below with reference to FIG.

In the figure, capacitor 2 is connected to the output of transistor 4 of the differential switching circuit, and transistor 3 is ON.
In this case, constant current charging is performed. Further, the gate of transistor 4 is driven by the output of voltage comparator l,
When the input voltage is lower than the output voltage, transistor 4 is turned off.
F, and when the input voltage becomes higher than the output voltage, the transistor 3 is configured to turn on.

In a circuit configured in this way, when the input voltage becomes higher than the output voltage, the comparator output turns on transistor 4, capacitor 2 is charged with a constant current by the output current of transistor 4, and the output voltage increases with time. . When the output voltage reaches the same level as the input voltage, the output of the voltage comparator 1 turns off the transistor 4, and charging of the capacitor 2 ends. In the process of charging the capacitor, the output voltage E0 increases while the capacitor 2 is being charged.
Charging is done by the output current of transistor 4. Good work.

Since it is charged with a constant current, it always increases linearly with time due to the relationship E l, = -T. This voltage increase is a straight line proportional to time, which is always true within the range in which the circuit shown in FIG. 1 operates normally under bias conditions, so the response is always constant regardless of the level of the input voltage. Also a constant current engineer. can be freely set using the constant current element 5, so a high-speed peak voltage holding circuit can be easily realized.

Regarding the holding time, if a MOS type transistor is used as the transistor 3 and an MO8 type transistor input voltage comparator is used, the holding time can be easily maintained for a long time.

If the voltage comparator must be of a bipolar transistor type due to speed or other reasons, a buffer made of an MO8 type transistor may be provided between the capacitor 2 and the voltage comparator 1, as in the embodiment shown in FIG.

Furthermore, in applications where a long holding time is not required, bipolar transistors can be used as transistors 4 and 5 in FIG.

〔Effect of the invention〕

As described above, according to the present invention, the response of the peak voltage holding circuit can always be made constant regardless of the level of the input voltage, and the speed can be increased.

[Brief explanation of drawings]

1 and 2 are peak voltage holding circuit diagrams according to the present invention,
FIG. 3 shows a conventional peak voltage holding circuit.

Claims (1)

[Claims] 1. It consists of a capacitor driven by one output of a transistor differential switching circuit, and a voltage comparator that compares the terminal voltage of the capacitor with an external input voltage, and when the external input voltage is higher than the capacitor terminal, the A peak voltage holding circuit characterized in that a capacitor is configured to be charged at a constant current by the output of the transistor differential switching circuit.