JPH018007Y2 - - Google Patents
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- Publication number
- JPH018007Y2 JPH018007Y2 JP1980097366U JP9736680U JPH018007Y2 JP H018007 Y2 JPH018007 Y2 JP H018007Y2 JP 1980097366 U JP1980097366 U JP 1980097366U JP 9736680 U JP9736680 U JP 9736680U JP H018007 Y2 JPH018007 Y2 JP H018007Y2
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- circuit
- feedback
- resistance value
- amplifier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 12
- 238000006243 chemical reaction Methods 0.000 claims description 7
- 238000010586 diagram Methods 0.000 description 6
- 239000002131 composite material Substances 0.000 description 3
- 230000002411 adverse Effects 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 235000014676 Phragmites communis Nutrition 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
Landscapes
- Amplifiers (AREA)
- Measurement Of Current Or Voltage (AREA)
- Control Of Amplification And Gain Control (AREA)
Description
【考案の詳細な説明】
本考案は電流を電圧に変換する回路において、
帰還抵抗器を切換える際に発生するスパイクノイ
ズを抑制した電流−電圧変換回路に関するもので
ある。[Detailed description of the invention] This invention is a circuit that converts current into voltage.
The present invention relates to a current-voltage conversion circuit that suppresses spike noise generated when switching a feedback resistor.
第1図は従来の抵抗器切換え回路を備えた電流
−電圧変換回路のブロツク図である。この回路は
周知の回路であり、入力端子1,2間に接続され
た試験素子3に流れる電流Iを、高利得増幅器4
の入出力端子間に接続された帰還抵抗器5等によ
り電圧を変換し、出力端子12より前記電流に比
例した電圧VAを導出するものである。ここで帰
還抵抗器は試験素子3に流れる電流の大きさに応
じて通常切換えられる。この切換えはスイツチ
(リードリレー)7をオン、オフすることにより
行なわれる。しかしながら例えばスイツチ7をオ
ンにした瞬間には、増幅器4の応答速度は有限の
ため、この抵抗変化に瞬時には応答できず、出力
電圧VAは一定で、増幅器4の入力端(入力端子
2、入力電圧VB)にスパイクノイズが発生する。
このスパイクノイズは通常数Vにもなり、試験素
子3として半導体素子を接続した場合には、その
測定条件を変える等の悪影響を及ぼす。 FIG. 1 is a block diagram of a current-to-voltage conversion circuit with a conventional resistor switching circuit. This circuit is a well-known circuit in which a current I flowing through a test element 3 connected between input terminals 1 and 2 is passed through a high gain amplifier 4.
The voltage is converted by a feedback resistor 5 etc. connected between the input and output terminals of the circuit, and a voltage V A proportional to the current is derived from the output terminal 12. Here, the feedback resistor is normally switched depending on the magnitude of the current flowing through the test element 3. This switching is performed by turning on and off a switch (reed relay) 7. However, at the moment when the switch 7 is turned on, for example, the response speed of the amplifier 4 is finite, so it cannot respond instantaneously to this resistance change, and the output voltage V A remains constant. , input voltage V B ).
This spike noise usually reaches several volts, and when a semiconductor element is connected as the test element 3, it has an adverse effect such as changing the measurement conditions.
したがつて本考案は上記欠点を除去するために
なされたもので、本考案は帰還抵抗器の切換え時
に発生するスパイクノイズを抑制できる電流−電
圧変換回路を提供することである。 Therefore, the present invention has been made to eliminate the above-mentioned drawbacks, and the object of the present invention is to provide a current-to-voltage conversion circuit that can suppress spike noise generated when switching a feedback resistor.
第2図は本考案の一実施例による抵抗器切換え
回路を備えた電流−電圧変換回路のブロツク図で
ある。第1図と同一部分には同一符号が付してあ
る。第1図と異なる部分のみ説明する。増幅器4
の入出力端子間にスイツチ7、帰還抵抗器9およ
び11より成る直列回路が接続される。そして抵
抗器9と11の結合点と基準電位点間に接合形
FET,MOSFET、バイポーラ・トランジスタ等
の半導体スイツチ19が接続される。15,17
はそれぞれスイツチ制御回路、鋸歯状波信号発生
器であり、端子13に印加される制御信号VPに
応答して信号VQ、VGをそれぞれ発生する。信号
VQはスイツチ7に、信号VGは半導体スイツチ1
9の制御端子にそれぞれ印加される。なおスイツ
チ7は抵抗器9,11を含む帰還回路を完全にオ
フするためのもので、必須要件ではない。 FIG. 2 is a block diagram of a current-to-voltage conversion circuit with a resistor switching circuit according to an embodiment of the present invention. The same parts as in FIG. 1 are given the same reference numerals. Only the parts that are different from FIG. 1 will be explained. amplifier 4
A series circuit consisting of switch 7 and feedback resistors 9 and 11 is connected between the input and output terminals of . And a junction type between the connection point of resistors 9 and 11 and the reference potential point.
A semiconductor switch 19 such as a FET, MOSFET, or bipolar transistor is connected. 15,17
are a switch control circuit and a sawtooth signal generator, respectively, which generate signals V Q and V G in response to a control signal V P applied to terminal 13, respectively. signal
V Q to switch 7, signal V G to semiconductor switch 1
9 control terminals, respectively. Note that the switch 7 is for completely turning off the feedback circuit including the resistors 9 and 11, and is not an essential requirement.
以下動作を説明する。第3図は帰還抵抗器(レ
ンジ抵抗器)の大きさに応じて作られる2個の構
成およびこれらの各種動作時における等価回路を
示したものである。第4図は各部動作波形図であ
る。以下半導体スイツチ19をNチヤンネル
FETとして場合を別けて説明する。 The operation will be explained below. FIG. 3 shows two configurations made depending on the size of the feedback resistor (range resistor) and their equivalent circuits during various operations. FIG. 4 is a waveform chart showing the operation of each part. Below is the semiconductor switch 19 as N channel.
The case will be explained separately as a FET.
第3図のaの場合
この構成は第2図の構成と同一であるが、原理
的に不必要な部分は省略してある。RR1とは抵抗
器9と11との直列合成抵抗器を示し、オンとは
この合成抵抗器が抵抗器5に並列接続され、帰還
抵抗値がこの直列合成抵抗器の抵抗値でほぼ定ま
る場合をいい、オフとは等価的に並列接続されな
い場合をいう。この構成はR5=100MΩ,R9=
990KΩ,R11=10KΩのような高抵抗切換え時に
用いられる。まず帰還抵抗値がほぼR9+R11=
1MΩとなるように帰還抵抗器を切換える場合
(並列接続)について説明する。この場合の等価
回路は第3図のbに示してある。第4図を参照す
る。信号VPがON信号からOFF信号になり、信号
VGは最大から最大に向つて一定のスルー・
レート(slew rate、傾斜、電圧/時間)で変化
する。VGがある値まで下がるとFET19はオン
からオフに向つて緩慢に変化する。即ちFET1
9のドレイン・ソース間の抵抗値(RF)は緩慢
に変化する。VGがさらに下つたある時点でFET
19は完全にオフになる。VQはVQ1のように変化
する。ここでFET19の一方の端子と抵抗器1
1の結合点sの電圧は、出力電圧VAをR11と
RFOFFの分電圧でVS≒VAである。R5≫(R9+R11)
であるから入力電流Iは抵抗器9,11を通つて
流れ、帰還抵抗値はほぼR9+R11で定まり帰還抵
抗器が切換えられたことになる。上記説明したこ
とにより明らかなようにFET19の抵抗値は緩
慢に切換えられ、よつてその速度に増幅器4は追
従できるので、即ちVGのスルー・レートより増
幅器4のスルー・レートが大なので、VBにスパ
イクノイズは発生しない。 Case a in Figure 3 This configuration is the same as the configuration in Figure 2, but parts that are unnecessary in principle have been omitted. R R1 indicates a series composite resistor of resistors 9 and 11, and ON means that this composite resistor is connected in parallel to resistor 5, and the feedback resistance value is approximately determined by the resistance value of this series composite resistor. , and off means that they are not equivalently connected in parallel. This configuration has R 5 = 100MΩ, R 9 =
Used when switching high resistances such as 990KΩ and R 11 = 10KΩ. First, the feedback resistance value is approximately R 9 + R 11 =
We will explain the case of switching the feedback resistor to 1MΩ (parallel connection). The equivalent circuit in this case is shown in FIG. 3b. Please refer to FIG. The signal V P changes from an ON signal to an OFF signal, and the signal
V G is a constant slew from maximum to maximum.
Changes in rate (slew rate, slope, voltage/time). When V G falls to a certain value, the FET 19 slowly changes from on to off. That is, FET1
The resistance value (R F ) between the drain and source of No. 9 changes slowly. At some point when V G has fallen further, FET
19 is completely turned off. V Q changes like V Q1 . Here, one terminal of FET19 and resistor 1
The voltage at the node s of 1 is the output voltage V A with R 11
The voltage divided by R FOFF is V S ≒ V A. R 5 ≫ (R 9 + R 11 )
Therefore, the input current I flows through the resistors 9 and 11, and the feedback resistance value is approximately determined by R 9 +R 11 , which means that the feedback resistor has been switched. As is clear from the above explanation, the resistance value of the FET 19 is switched slowly, and the amplifier 4 can follow that speed. In other words, since the slew rate of the amplifier 4 is greater than the slew rate of V G , the resistance value of the FET 19 is switched slowly. No spike noise occurs in B.
次に帰還抵抗値がR5のみで定まるように帰還
抵抗器を切換える場合ついて説明する。この場合
の等価回路は第3図のCに示してある。VPがオ
ンからオフになると、それと同時にまたは少し遅
れて、信号VGを最大から最大に向つて一定
のスルー・レートで変化させる。即ちFET19
をオンからオフに向つて変化させる。VGがある
値に達するとFET19はオンになり始め、その
抵抗値は緩慢に変化される。そしてFET19は
その後完全にオンになる。この場合VS≒0Vとな
り入力電流Iは帰還抵抗器5を通つて流れ、帰還
抵抗器は抵抗器5のみによつて定まる。この場合
もFET19のソース・ドレイン間抵抗値は緩慢
に変化するためVBにスパイクノイズは発生しな
い。なお、FET19はリレー7がオンの期間中
にオン/オフされねばらないので、FET19が
オンになつた後にVQ1はオフにされる。即ち、制
御回路15には遅延回路があり、VPがオンにな
つた後、遅延時間を経てVQ1はオフになる。 Next, a case will be described in which the feedback resistor is switched so that the feedback resistance value is determined only by R5 . The equivalent circuit in this case is shown in FIG. 3C. When V P turns from on to off, simultaneously or with a slight delay, the signal V G changes from maximum to maximum at a constant slew rate. That is, FET19
change from on to off. When V G reaches a certain value, FET 19 begins to turn on and its resistance value is slowly changed. FET 19 then turns completely on. In this case, V S ≈0V, and the input current I flows through the feedback resistor 5, which is determined only by the resistor 5. In this case as well, since the source-drain resistance value of FET 19 changes slowly, no spike noise is generated at VB . Note that since FET 19 must be turned on and off while relay 7 is on, V Q1 is turned off after FET 19 is turned on. That is, the control circuit 15 includes a delay circuit, and after V P is turned on, V Q1 is turned off after a delay time.
第3図のdの場合
この構成は第3図のaの場合と異なり、抵抗器
9と直列にFET20が接続され、そして抵抗器
9とFET20の結合点sと基準電位点間に抵抗
器13が接続される。この構成はR5=10KΩ,
R9=75Ω,R13=10KΩのような低抵抗切換え時
に用いられる。まず帰還抵抗値がほぼR9+RFON
=100Ωとなるように帰還抵抗器を切換える場合
(並列接続)について説明する。この場合の等価
回路は第3図のeに示してある。FET20をオ
フからオンに向つて変化させる。VGがある値に
なるとFET20はオンになり始めその抵抗値は
緩慢に変化される。FET20が完全にオンにな
つたときVS≒VAであり、帰還抵抗値はほぼR9+
RFONで定まる。VQはVQ2のように変化する。 Case d in Figure 3 This configuration differs from the case in Figure 3 a, in that the FET 20 is connected in series with the resistor 9, and the resistor 13 is connected between the connection point s of the resistor 9 and FET 20 and the reference potential point. is connected. This configuration has R 5 = 10KΩ,
Used for low resistance switching such as R 9 = 75Ω and R 13 = 10KΩ. First, the feedback resistance value is approximately R 9 + R FON
We will explain the case of switching the feedback resistor so that = 100Ω (parallel connection). The equivalent circuit in this case is shown in FIG. 3e. Change FET20 from off to on. When V G reaches a certain value, FET 20 begins to turn on and its resistance value changes slowly. When FET20 is completely turned on, V S ≒ V A , and the feedback resistance value is approximately R 9 +
Determined by R FON . V Q changes like V Q2 .
第3図のfの場合はFET20がオフになるよ
うに制御され、帰還抵抗値はほぼR5で定まる。
なおレンジ抵抗値の大小によつて第3図のaとd
に構成を区別したのは、例えば第3図のfの場合
をcと同一構成にすると、RFONがかなりの値をも
つことからVS≒0Vになし得ないからである。 In the case of f in FIG. 3, the FET 20 is controlled to be turned off, and the feedback resistance value is approximately determined by R5 .
Depending on the range resistance value, a and d in Figure 3.
The reason for distinguishing the configurations is that if, for example, f in FIG. 3 were to have the same configuration as c, it would not be possible to make V S ≈0V since R FON would have a considerable value.
以上の説明より明らかなように本考案によれば
帰還抵抗器の切換え時に発生するスパイクノイズ
は抑制され、試験素子3として半導体素子を接続
してもその特性測定に悪影響を与えることはな
い。本考案は半導体素子に流れる電流を電圧に変
換し、該電流を検出する装置に使用して効果が極
めて大である。 As is clear from the above explanation, according to the present invention, the spike noise generated when switching the feedback resistor is suppressed, and even if a semiconductor element is connected as the test element 3, the characteristics measurement thereof will not be adversely affected. The present invention is extremely effective when used in a device that converts a current flowing through a semiconductor element into a voltage and detects the current.
第1図は従来の抵抗器切換え回路を備えた電流
−電圧変換回路のブロツク図、第2図は本考案の
一実施例による抵抗器切換え回路を備えた電流−
電圧変換回路のブロツク図、第3図は本考案の他
実施例を含む本考案の動作説明図、第4図は本考
案の各部波形図である。
3:試験素子、7:スイツチ、15:スイツチ
制御回路、17:鋸歯状波信号発生器、19:半
導体スイツチ。
FIG. 1 is a block diagram of a current-to-voltage conversion circuit equipped with a conventional resistor switching circuit, and FIG. 2 is a block diagram of a current-to-voltage conversion circuit equipped with a resistor switching circuit according to an embodiment of the present invention.
FIG. 3 is an explanatory diagram of the operation of the present invention including other embodiments of the present invention, and FIG. 4 is a waveform diagram of each part of the present invention. 3: Test element, 7: Switch, 15: Switch control circuit, 17: Sawtooth signal generator, 19: Semiconductor switch.
Claims (1)
該増幅器への入力電流を電圧に変換する回路にお
いて、抵抗器と抵抗器(または半導体スイツチ)
との直列回路と、前記抵抗器と抵抗器(または半
導体スイツチ)との結合点と基準電位点との間に
接続された半導体スイツチ(または抵抗器)と、
前記半導体スイツチの制御端子に接続された鋸歯
状波信号発生器とより成る抵抗器切換え回路を前
記直列回路が前記帰還抵抗器に並列接続されるよ
うに前記増幅器の入出力端子間に接続し、前記半
導体スイツチのオン/オフ動作に応答して、前記
増幅器の入出力端子間の帰還抵抗値を前記帰還抵
抗器または前記直列回路による抵抗値に実質的に
切換えるようにした抵抗器切換え回路を備えた電
流−電圧変換回路。 Connect a feedback resistor between the input and output terminals of the amplifier,
In the circuit that converts the input current to the amplifier into voltage, resistors and resistors (or semiconductor switches)
and a semiconductor switch (or resistor) connected between the connection point of the resistor and the resistor (or semiconductor switch) and a reference potential point;
a resistor switching circuit comprising a sawtooth signal generator connected to a control terminal of the semiconductor switch, connected between input and output terminals of the amplifier such that the series circuit is connected in parallel to the feedback resistor; A resistor switching circuit configured to substantially switch the feedback resistance value between the input and output terminals of the amplifier to the resistance value of the feedback resistor or the series circuit in response to the on/off operation of the semiconductor switch. Current-voltage conversion circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1980097366U JPH018007Y2 (en) | 1980-07-10 | 1980-07-10 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1980097366U JPH018007Y2 (en) | 1980-07-10 | 1980-07-10 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5723614U JPS5723614U (en) | 1982-02-06 |
JPH018007Y2 true JPH018007Y2 (en) | 1989-03-02 |
Family
ID=29459154
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1980097366U Expired JPH018007Y2 (en) | 1980-07-10 | 1980-07-10 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH018007Y2 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2568851Y2 (en) * | 1991-04-23 | 1998-04-15 | 松下電工株式会社 | Keraba structure for roof panel |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4821542B1 (en) * | 1967-06-26 | 1973-06-29 | ||
JPS5320344A (en) * | 1976-08-10 | 1978-02-24 | Mitsubishi Electric Corp | Photo-fiber connector |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4821542U (en) * | 1971-07-23 | 1973-03-12 |
-
1980
- 1980-07-10 JP JP1980097366U patent/JPH018007Y2/ja not_active Expired
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4821542B1 (en) * | 1967-06-26 | 1973-06-29 | ||
JPS5320344A (en) * | 1976-08-10 | 1978-02-24 | Mitsubishi Electric Corp | Photo-fiber connector |
Also Published As
Publication number | Publication date |
---|---|
JPS5723614U (en) | 1982-02-06 |
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