JP2973654B2 - Static auxiliary relay circuit - Google Patents
Static auxiliary relay circuitInfo
- Publication number
- JP2973654B2 JP2973654B2 JP3305792A JP30579291A JP2973654B2 JP 2973654 B2 JP2973654 B2 JP 2973654B2 JP 3305792 A JP3305792 A JP 3305792A JP 30579291 A JP30579291 A JP 30579291A JP 2973654 B2 JP2973654 B2 JP 2973654B2
- Authority
- JP
- Japan
- Prior art keywords
- photocoupler
- transistor
- time
- semiconductor element
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Emergency Protection Circuit Devices (AREA)
- Electronic Switches (AREA)
Description
【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION
【0001】[0001]
【産業上の利用分野】本発明は、入出力間を光素子で電
気絶縁し、出力段半導体素子にオン・オフ出力を得る静
止形補助リレー回路に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a static auxiliary relay circuit in which an input and output are electrically insulated by an optical element and an on / off output is obtained at an output semiconductor element.
【0002】[0002]
【従来の技術】図2は従来の回路図を示す。オン・オフ
入力信号は限流抵抗1を通してフオトカプラ2の入力素
子に印加される。フオトカプラ2の出力素子電圧V
inは、抵抗3を通して出力素子になるFET4のゲート
に印加される。FET4のゲート・ソース間には時定数
回路としての抵抗5とコンデンサ6の並列回路が設けら
れる。2. Description of the Related Art FIG. 2 shows a conventional circuit diagram. The on / off input signal is applied to the input element of the photocoupler 2 through the current limiting resistor 1. Output element voltage V of photocoupler 2
in is applied to the gate of the FET 4 that becomes an output element through the resistor 3. A parallel circuit of a resistor 5 and a capacitor 6 as a time constant circuit is provided between the gate and the source of the FET 4.
【0003】上述の構成において、入力信号のオン・オ
フに対するFET4のオン・オフ出力になる動作時間T
OP及び復帰時間TREは以下のようになる。In the above-described configuration, the operation time T when the FET 4 is turned on / off with respect to the on / off of the input signal.
OP and return time T RE are as follows.
【0004】 TOP=−(C6+CSS)×(R3//R5)ln(1−V2/V1) 但し、V1=Vsn(R3/(R2+R3)) C6 :コンデンサ6の容量 CSS:FETの入力容量 R3 :抵抗3の抵抗値 R5 :抵抗5の抵抗値 V2 :FETの動作電圧(スレッショールド) TRE=−(C6+CSS)×R5×ln(V3/V1) 但し、V3:FETの復帰電圧[0004] T OP =-(C 6 + C SS ) × (R 3 // R 5 ) ln (1-V 2 / V 1 ) where V 1 = V sn (R 3 / (R 2 + R 3 )) C 6 : Capacitance of capacitor 6 C SS : Input capacitance of FET R 3 : Resistance value of resistor 3 R 5 : Resistance value of resistor 5 V 2 : Operating voltage (threshold) of FET T RE = − (C 6 + C SS ) × R 5 × ln (V 3 / V 1 ), where V 3 : FET return voltage
【0005】[0005]
【発明が解決しようとする課題】従来の補助リレー回路
において、フオトカプラ2はその出力容量が小さいた
め、抵抗3と5の抵抗値R3,R5は R3<<R5 とする必要がある。このため、動作時間TOPと復帰時間
TREには TOP<TRE となるのが一般的であり、TOP>TREとすることができ
ない問題があった。In the conventional auxiliary relay circuit, since the output capacity of the photocoupler 2 is small, the resistance values R 3 and R 5 of the resistors 3 and 5 must be R 3 << R 5. . For this reason, it is general that the operating time TOP and the return time TRE generally satisfy TOP < TRE, and there is a problem that TOP > TRE cannot be satisfied.
【0006】また、動作時間TOPに短い時間を得るには
コンデンサ6の容量C6を小さくすることになるが、こ
の容量が小さくなるとFET4の入力容量CSSのバラツ
キによって所期の特性を得る設計が難しくなる。逆に、
抵抗3の抵抗値R3を小さくして容量C6をCSSより十分
に大きくすると、復帰時間TREを大きくしてしまい、T
OP<<TREとなって復帰時間との間に所期のものが得ら
れなくなる。In order to obtain a short operation time TOP , the capacitance C 6 of the capacitor 6 must be reduced. However, if this capacitance is reduced, desired characteristics are obtained due to variations in the input capacitance C SS of the FET 4. Design becomes difficult. vice versa,
If the resistance value R 3 of the resistor 3 is reduced and the capacitance C 6 is made sufficiently larger than C SS , the return time T RE becomes longer, and T
OP << T RE and the expected value cannot be obtained between the return time.
【0007】本発明の目的は、動作時間と復帰時間の大
小関係及び値設定を任意する静止形補助リレー回路を提
供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a static auxiliary relay circuit for arbitrarily setting a magnitude relationship between an operation time and a recovery time and setting a value.
【0008】[0008]
【課題を解決するための手段】本発明は、前記課題を解
決するため、オン・オフ入力信号を電気絶縁して取込む
フオトカプラと、前記フオトカプラの出力素子に並列に
設けられるコンデンサと第1の抵抗との並列回路及び該
並列回路に直列接続される第2の抵抗と、前記フオトカ
プラの出力素子と出力用半導体素子のゲート間に設けら
れ前記第1の抵抗と第2の抵抗との接続点電圧によって
オンして半導体素子をオフさせるトランジスタと、前記
トランジスタのコレクタとエミッタ間に設けられ前記半
導体素子をオンさせる電流路を形成するダイオードと備
えたことを特徴とする。SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a photocoupler for receiving an ON / OFF input signal in a state of being electrically isolated, a capacitor provided in parallel with an output element of the photocoupler, and a first circuit. A parallel circuit with a resistor, a second resistor connected in series with the parallel circuit, and a connection point between the first resistor and the second resistor provided between the output element of the photocoupler and the gate of the output semiconductor element. The semiconductor device includes a transistor that is turned on by a voltage to turn off the semiconductor element, and a diode that is provided between a collector and an emitter of the transistor and forms a current path that turns on the semiconductor element.
【0009】[0009]
【作用】本発明によれば、フオトカプラの出力素子と出
力用半導体素子間にトランジスタを設けることにより、
半導体素子をオフさせる動作時間を該トランジスタのオ
ンまでの時間、即ちコンデンサと第1、第2の抵抗によ
る時定数に依存させる。According to the present invention, by providing a transistor between the output element of the photocoupler and the output semiconductor element,
The operation time for turning off the semiconductor element depends on the time until the transistor turns on, that is, the time constant of the capacitor and the first and second resistors.
【0010】また、トランジスタのコレクタとエミッタ
間にダイオードを設けることにより、半導体素子をオン
させる復帰時間を半導体素子の入力容量又は外付けコン
デンサ容量と第1、第2の抵抗による時定数に依存させ
る。Further, by providing a diode between the collector and the emitter of the transistor, the recovery time for turning on the semiconductor element depends on the input capacitance of the semiconductor element or the external capacitor capacitance and the time constant of the first and second resistors. .
【0011】[0011]
【実施例】図1は本発明の一実施例を示す回路図であ
り、図2と同じものは同一符号で示す。フオトカプラ2
の出力素子には並列に、コンデンサ7と抵抗8の並列回
路とこれに直列の抵抗9が設けられる。また、フオトカ
プラ2の出力素子とFET4のゲート間にはスイッチ手
段になるPNP型トランジスタ10のエミッタ・コレク
タ間が接続され、該トランジスタ10のベースが抵抗8
と抵抗9の接続点に接続される。さらに、トランジスタ
10のコレクタからエミッタに向けて順方向にダイオー
ド11が設けられてFETをオンさせる電流路が形成さ
れる。FIG. 1 is a circuit diagram showing one embodiment of the present invention, and the same components as those in FIG. 2 are denoted by the same reference numerals. Photocoupler 2
Are provided in parallel with a parallel circuit of a capacitor 7 and a resistor 8 and a resistor 9 in series therewith. An emitter-collector of a PNP transistor 10 serving as a switch is connected between the output element of the photocoupler 2 and the gate of the FET 4, and the base of the transistor 10 is connected to a resistor 8
And the resistor 9 are connected. Further, a diode 11 is provided in a forward direction from the collector to the emitter of the transistor 10 to form a current path for turning on the FET.
【0012】本実施例において、動作時間TOPはトラン
ジスタ10がオンするまでの時間、即ち抵抗8,9の抵
抗値R8,R9とコンデンサ7の容量C7によって決ま
り、FET4の入力容量CSSには依存しない。この動作
時間TOPは、FET4の入力インピーダンスR4がR4>
>R8+R9とすると、次式になる。In this embodiment, the operation time T OP is determined by the time until the transistor 10 is turned on, that is, the resistance values R 8 and R 9 of the resistors 8 and 9 and the capacitance C 7 of the capacitor 7. Not dependent on SS . The operation time T OP is input impedance R 4 is R 4 of FET 4>
If> R 8 + R 9 , the following equation is obtained.
【0013】 TOP=−C7×(R8//R9)×ln(1−VBE/V1) 但し、V1=Vin(R8/(R8+R9)) VBE:トランジスタ10のベース・エミッタ間電圧 一方、復帰時間TREはダイオード11が導通して入力容
量CSSの電荷を放電するまでの時間、即ち抵抗8,9の
抵抗値R8,R9と入力容量CSSによって決まり、コンデ
ンサ7の容量C7には依存しない。この復帰時間T
REは、 TRE=−CSS×(R8+R9)×ln(V3/V1) となる。T OP = −C 7 × (R 8 // R 9 ) × ln (1-V BE / V 1 ) where V 1 = V in (R 8 / (R 8 + R 9 )) V BE : On the other hand, the recovery time T RE is the time required for the diode 11 to conduct and discharge the charge of the input capacitance C SS , that is, the resistance values R 8 and R 9 of the resistors 8 and 9 and the input capacitance. It is determined by C SS and does not depend on the capacitance C 7 of the capacitor 7. This return time T
RE is given by T RE = −C SS × (R 8 + R 9 ) × ln (V 3 / V 1 ).
【0014】従って、本実施例によれば、動作時間TOP
と復帰時間TREを夫々異なる容量C7,CSSによって決
定でき、TOP>=TREになる回路構成及びTOP<TREの
構成にも任意に設定できる。Therefore, according to this embodiment, the operation time T OP
And the recovery time T RE can be determined by different capacities C 7 and C SS , respectively, and can be arbitrarily set to a circuit configuration where T OP > = T RE and a configuration of T OP <T RE .
【0015】また、動作時間TOPはコンデンサ7の容量
に依存するため、FET4の入力容量CSSのバラツキに
影響されることなく確実にしかも短時間から長時間まで
広範囲に設定できる。Further, operation time T OP is dependent on the capacity of the capacitor 7 can be reliably and set in a wide range from short to long, without being affected by variations in the input capacitance C SS of FET 4.
【0016】なお、復帰時間TREはFET4の入力容量
CSSに依存するため、そのバラツキが設計値とずれるこ
とがあるが、FET4のゲート・ソース間に外付けコン
デンサを付加する構成にして入力容量CSSのバラツキに
よる影響を抑制することができる。Since the recovery time T RE depends on the input capacitance C SS of the FET 4, its dispersion may deviate from the designed value. However, the input time is determined by adding an external capacitor between the gate and source of the FET 4. The effect of the variation in the capacitance C SS can be suppressed.
【0017】以上までの本実施例において、出力素子と
してFETを使用する場合を示すが、これはトランジス
タやサイリスタなどの他の半導体素子に置換して同等の
作用効果を得ることができる。In the above-described embodiment, the case where an FET is used as an output element is shown. However, this can be replaced with another semiconductor element such as a transistor or a thyristor to obtain the same operation and effect.
【0018】[0018]
【発明の効果】以上のとおり、本発明によれば、フオト
カプラの出力素子と出力用半導体素子のゲート間にオフ
用トランジスタとオン用ダイオードを設け、出力素子側
と半導体素子側との両コンデンサの容量によって動作時
間と復帰時間が個別に設定できるようにしたため、動作
時間と復帰時間をリレー回路に要求される任意の時間設
定ができる効果がある。As described above, according to the present invention, an off transistor and an on diode are provided between the output element of the photocoupler and the gate of the output semiconductor element, and the capacitors of both the output element side and the semiconductor element side are provided. Since the operation time and the recovery time can be individually set according to the capacity, there is an effect that the operation time and the recovery time can be set to any time required for the relay circuit.
【図1】実施例の回路図。FIG. 1 is a circuit diagram of an embodiment.
【図2】従来の回路図。FIG. 2 is a conventional circuit diagram.
2…フオトカプラ、4…FET、7…コンデンサ、8,
9…抵抗、10…トランジスタ、11…ダイオード。2 ... Photocoupler, 4 ... FET, 7 ... Capacitor, 8,
9: resistance, 10: transistor, 11: diode.
Claims (1)
むフオトカプラと、 前記フオトカプラの出力素子に並列に設けられるコンデ
ンサと第1の抵抗との並列回路及び該並列回路に直列接
続される第2の抵抗と、 前記フオトカプラの出力素子と出力用半導体素子のゲー
ト間に設けられ前記第1の抵抗と第2の抵抗との接続点
電圧によってオンして半導体素子をオフさせるトランジ
スタと、 前記トランジスタのコレクタとエミッタ間に設けられ前
記半導体素子をオンさせる電流路を形成するダイオード
と、 を備えたことを特徴とする静止形補助リレー回路。1. A photocoupler for electrically isolating and receiving an on / off input signal, a parallel circuit of a capacitor and a first resistor provided in parallel with an output element of the photocoupler, and a second circuit connected in series to the parallel circuit. A transistor provided between the output element of the photocoupler and the gate of the output semiconductor element and turned on by a connection point voltage between the first and second resistors to turn off the semiconductor element; and the transistor And a diode provided between the collector and the emitter of the above to form a current path for turning on the semiconductor element.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3305792A JP2973654B2 (en) | 1991-11-21 | 1991-11-21 | Static auxiliary relay circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3305792A JP2973654B2 (en) | 1991-11-21 | 1991-11-21 | Static auxiliary relay circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH05145392A JPH05145392A (en) | 1993-06-11 |
JP2973654B2 true JP2973654B2 (en) | 1999-11-08 |
Family
ID=17949416
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3305792A Expired - Fee Related JP2973654B2 (en) | 1991-11-21 | 1991-11-21 | Static auxiliary relay circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2973654B2 (en) |
-
1991
- 1991-11-21 JP JP3305792A patent/JP2973654B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JPH05145392A (en) | 1993-06-11 |
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