JPH05145392A - Stationary auxiliary relay circuit - Google Patents

Stationary auxiliary relay circuit

Info

Publication number
JPH05145392A
JPH05145392A JP3305792A JP30579291A JPH05145392A JP H05145392 A JPH05145392 A JP H05145392A JP 3305792 A JP3305792 A JP 3305792A JP 30579291 A JP30579291 A JP 30579291A JP H05145392 A JPH05145392 A JP H05145392A
Authority
JP
Japan
Prior art keywords
time
capacitance
resistor
transistor
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3305792A
Other languages
Japanese (ja)
Other versions
JP2973654B2 (en
Inventor
Masaharu Emoto
政春 江本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Meidensha Corp
Meidensha Electric Manufacturing Co Ltd
Original Assignee
Meidensha Corp
Meidensha Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Meidensha Corp, Meidensha Electric Manufacturing Co Ltd filed Critical Meidensha Corp
Priority to JP3305792A priority Critical patent/JP2973654B2/en
Publication of JPH05145392A publication Critical patent/JPH05145392A/en
Application granted granted Critical
Publication of JP2973654B2 publication Critical patent/JP2973654B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

PURPOSE:To set the operating time and the restoration time and their quantity relation optionally by providing a transistor(TR) and a diode between an output element of a photocoupler and an output semiconductor element. CONSTITUTION:An operating time TOP depends on resistance values R8, R9 of resistors 8, 9 and a capacitance C7 of a capacitor 7 and is not depending on an input capacitance CSS of a FET4. On the other hand, a returning time TRE depends on the resistance values R8, R9 and the capacitance CSS and is not depending on the C7. Thus, the times TOP, TRE depend respectively different capacitance values C7, CSS and the circuit configuration for TOP >=TRE and the circuit configuration for TOP<TRE are set optionally. Thus, the operating time and the return time are set to optional times requested by a relay circuit.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、入出力間を光素子で電
気絶縁し、出力段半導体素子にオン・オフ出力を得る静
止形補助リレー回路に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a static auxiliary relay circuit that electrically insulates an input and an output from each other with an optical element and obtains an on / off output to an output stage semiconductor element.

【0002】[0002]

【従来の技術】図2は従来の回路図を示す。オン・オフ
入力信号は限流抵抗1を通してフオトカプラ2の入力素
子に印加される。フオトカプラ2の出力素子電圧V
inは、抵抗3を通して出力素子になるFET4のゲート
に印加される。FET4のゲート・ソース間には時定数
回路としての抵抗5とコンデンサ6の並列回路が設けら
れる。
2. Description of the Related Art FIG. 2 shows a conventional circuit diagram. The on / off input signal is applied to the input element of the photocoupler 2 through the current limiting resistor 1. Output element voltage V of photo coupler 2
in is applied to the gate of the FET 4 which becomes an output element through the resistor 3. A parallel circuit of a resistor 5 and a capacitor 6 as a time constant circuit is provided between the gate and source of the FET 4.

【0003】上述の構成において、入力信号のオン・オ
フに対するFET4のオン・オフ出力になる動作時間T
OP及び復帰時間TREは以下のようになる。
In the above structure, the operating time T at which the FET 4 turns on and off with respect to the turning on and off of the input signal.
OP and recovery time T RE are as follows.

【0004】 TOP=−(C6+CSS)×(R3//R5)ln(1−V2/V1) 但し、V1=Vsn(R3/(R2+R3)) C6 :コンデンサ6の容量 CSS:FETの入力容量 R3 :抵抗3の抵抗値 R5 :抵抗5の抵抗値 V2 :FETの動作電圧(スレッショールド) TRE=−(C6+CSS)×R5×ln(V3/V1) 但し、V3:FETの復帰電圧T OP = − (C 6 + C SS ) × (R 3 // R 5 ) ln (1-V 2 / V 1 ) where V 1 = V sn (R 3 / (R 2 + R 3 )) C 6: capacitance of the capacitor 6 C SS: input capacitance R 3 and FET: resistance 3 of the resistance value R 5: resistor 5 of resistance V 2: operating voltage (threshold) of FET T RE = - (C 6 + C SS ) × R 5 × ln (V 3 / V 1 ) where V 3 is the recovery voltage of the FET

【0005】[0005]

【発明が解決しようとする課題】従来の補助リレー回路
において、フオトカプラ2はその出力容量が小さいた
め、抵抗3と5の抵抗値R3,R5は R3<<R5 とする必要がある。このため、動作時間TOPと復帰時間
REには TOP<TRE となるのが一般的であり、TOP>TREとすることができ
ない問題があった。
In the conventional auxiliary relay circuit, since the photocoupler 2 has a small output capacity, it is necessary to set the resistance values R 3 and R 5 of the resistors 3 and 5 to R 3 << R 5. .. Therefore, the operation time T OP and the recovery time T RE are generally T OP <T RE, and there is a problem that T OP > T RE cannot be satisfied.

【0006】また、動作時間TOPに短い時間を得るには
コンデンサ6の容量C6を小さくすることになるが、こ
の容量が小さくなるとFET4の入力容量CSSのバラツ
キによって所期の特性を得る設計が難しくなる。逆に、
抵抗3の抵抗値R3を小さくして容量C6をCSSより十分
に大きくすると、復帰時間TREを大きくしてしまい、T
OP<<TREとなって復帰時間との間に所期のものが得ら
れなくなる。
Further, in order to obtain a short operation time T OP , the capacitance C 6 of the capacitor 6 is made small. However, when this capacitance becomes small, the desired characteristic is obtained due to the variation of the input capacitance C SS of the FET 4. Design becomes difficult. vice versa,
If the resistance value R 3 of the resistor 3 is made small and the capacitance C 6 is made sufficiently larger than C SS , the recovery time T RE becomes large and T
It becomes OP << T RE, and it becomes impossible to obtain the desired product during the recovery time.

【0007】本発明の目的は、動作時間と復帰時間の大
小関係及び値設定を任意する静止形補助リレー回路を提
供することにある。
An object of the present invention is to provide a static auxiliary relay circuit in which the magnitude relation between the operating time and the recovery time and the value setting are arbitrary.

【0008】[0008]

【課題を解決するための手段】本発明は、前記課題を解
決するため、オン・オフ入力信号を電気絶縁して取込む
フオトカプラと、前記フオトカプラの出力素子に並列に
設けられるコンデンサと第1の抵抗との並列回路及び該
並列回路に直列接続される第2の抵抗と、前記フオトカ
プラの出力素子と出力用半導体素子のゲート間に設けら
れ前記第1の抵抗と第2の抵抗との接続点電圧によって
オンして半導体素子をオフさせるトランジスタと、前記
トランジスタのコレクタとエミッタ間に設けられ前記半
導体素子をオンさせる電流路を形成するダイオードと備
えたことを特徴とする。
In order to solve the above-mentioned problems, the present invention provides a photocoupler for electrically isolating an ON / OFF input signal, a capacitor provided in parallel with an output element of the photocoupler, and a first capacitor. A parallel circuit with a resistor and a second resistor connected in series with the parallel circuit, and a connection point between the first resistor and the second resistor provided between the output element of the photocoupler and the gate of the output semiconductor element. It is characterized by comprising a transistor which is turned on by a voltage to turn off the semiconductor element, and a diode which is provided between a collector and an emitter of the transistor and which forms a current path for turning on the semiconductor element.

【0009】[0009]

【作用】本発明によれば、フオトカプラの出力素子と出
力用半導体素子間にトランジスタを設けることにより、
半導体素子をオフさせる動作時間を該トランジスタのオ
ンまでの時間、即ちコンデンサと第1、第2の抵抗によ
る時定数に依存させる。
According to the present invention, by providing a transistor between the output element of the photocoupler and the output semiconductor element,
The operation time for turning off the semiconductor element depends on the time until the transistor turns on, that is, the time constant due to the capacitor and the first and second resistors.

【0010】また、トランジスタのコレクタとエミッタ
間にダイオードを設けることにより、半導体素子をオン
させる復帰時間を半導体素子の入力容量又は外付けコン
デンサ容量と第1、第2の抵抗による時定数に依存させ
る。
Further, by providing a diode between the collector and the emitter of the transistor, the recovery time for turning on the semiconductor element depends on the input capacitance of the semiconductor element or the capacitance of the external capacitor and the time constant of the first and second resistors. ..

【0011】[0011]

【実施例】図1は本発明の一実施例を示す回路図であ
り、図2と同じものは同一符号で示す。フオトカプラ2
の出力素子には並列に、コンデンサ7と抵抗8の並列回
路とこれに直列の抵抗9が設けられる。また、フオトカ
プラ2の出力素子とFET4のゲート間にはスイッチ手
段になるPNP型トランジスタ10のエミッタ・コレク
タ間が接続され、該トランジスタ10のベースが抵抗8
と抵抗9の接続点に接続される。さらに、トランジスタ
10のコレクタからエミッタに向けて順方向にダイオー
ド11が設けられてFETをオンさせる電流路が形成さ
れる。
1 is a circuit diagram showing an embodiment of the present invention, and the same elements as those in FIG. 2 are designated by the same reference numerals. Photo coupler 2
In parallel with the output element of, the parallel circuit of the capacitor 7 and the resistor 8 and the resistor 9 in series therewith are provided. Further, between the output element of the photocoupler 2 and the gate of the FET 4, the emitter and collector of a PNP transistor 10 serving as a switching means are connected, and the base of the transistor 10 is a resistor 8.
Is connected to the connection point of the resistor 9 and the resistor 9. Further, the diode 11 is provided in the forward direction from the collector to the emitter of the transistor 10 to form a current path for turning on the FET.

【0012】本実施例において、動作時間TOPはトラン
ジスタ10がオンするまでの時間、即ち抵抗8,9の抵
抗値R8,R9とコンデンサ7の容量C7によって決ま
り、FET4の入力容量CSSには依存しない。この動作
時間TOPは、FET4の入力インピーダンスR4がR4
>R8+R9とすると、次式になる。
In this embodiment, the operating time T OP is determined by the time until the transistor 10 is turned on, that is, the resistance values R 8 and R 9 of the resistors 8 and 9 and the capacitance C 7 of the capacitor 7, and the input capacitance C of the FET 4 is determined. Does not depend on SS . In this operation time T OP , the input impedance R 4 of the FET 4 is R 4 >
When> R 8 + R 9 , the following equation is obtained.

【0013】 TOP=−C7×(R8//R9)×ln(1−VBE/V1) 但し、V1=Vin(R8/(R8+R9)) VBE:トランジスタ10のベース・エミッタ間電圧 一方、復帰時間TREはダイオード11が導通して入力容
量CSSの電荷を放電するまでの時間、即ち抵抗8,9の
抵抗値R8,R9と入力容量CSSによって決まり、コンデ
ンサ7の容量C7には依存しない。この復帰時間T
REは、 TRE=−CSS×(R8+R9)×ln(V3/V1) となる。
T OP = −C 7 × (R 8 // R 9 ) × ln (1-V BE / V 1 ), where V 1 = V in (R 8 / (R 8 + R 9 )) V BE : Base-emitter voltage of the transistor 10 On the other hand, the recovery time T RE is the time until the diode 11 becomes conductive and the charge of the input capacitance C SS is discharged, that is, the resistance values R 8 and R 9 of the resistors 8 and 9 and the input capacitance. It depends on C SS and does not depend on the capacitance C 7 of the capacitor 7. This return time T
RE becomes T RE = −C SS × (R 8 + R 9 ) × ln (V 3 / V 1 ).

【0014】従って、本実施例によれば、動作時間TOP
と復帰時間TREを夫々異なる容量C7,CSSによって決
定でき、TOP>=TREになる回路構成及びTOP<TRE
構成にも任意に設定できる。
Therefore, according to this embodiment, the operating time T OP
And the recovery time T RE can be determined by different capacitances C 7 and C SS , respectively, and can be arbitrarily set in the circuit configuration in which T OP > = T RE and the configuration in T OP <T RE .

【0015】また、動作時間TOPはコンデンサ7の容量
に依存するため、FET4の入力容量CSSのバラツキに
影響されることなく確実にしかも短時間から長時間まで
広範囲に設定できる。
Further, since the operating time T OP depends on the capacity of the capacitor 7, it can be set reliably and in a wide range from short time to long time without being affected by the variation of the input capacity C SS of the FET 4.

【0016】なお、復帰時間TREはFET4の入力容量
SSに依存するため、そのバラツキが設計値とずれるこ
とがあるが、FET4のゲート・ソース間に外付けコン
デンサを付加する構成にして入力容量CSSのバラツキに
よる影響を抑制することができる。
Since the recovery time T RE depends on the input capacitance C SS of the FET 4, its variation may deviate from the design value. However, an external capacitor is added between the gate and source of the FET 4 to input it. It is possible to suppress the influence of variations in the capacitance C SS .

【0017】以上までの本実施例において、出力素子と
してFETを使用する場合を示すが、これはトランジス
タやサイリスタなどの他の半導体素子に置換して同等の
作用効果を得ることができる。
In the above-mentioned embodiment, the case where the FET is used as the output element is shown. However, this can be replaced with another semiconductor element such as a transistor or a thyristor to obtain the same effect.

【0018】[0018]

【発明の効果】以上のとおり、本発明によれば、フオト
カプラの出力素子と出力用半導体素子のゲート間にオフ
用トランジスタとオン用ダイオードを設け、出力素子側
と半導体素子側との両コンデンサの容量によって動作時
間と復帰時間が個別に設定できるようにしたため、動作
時間と復帰時間をリレー回路に要求される任意の時間設
定ができる効果がある。
As described above, according to the present invention, the off transistor and the on diode are provided between the output element of the photocoupler and the gate of the output semiconductor element, and the capacitors for both the output element side and the semiconductor element side are provided. Since the operating time and the recovery time can be set individually depending on the capacity, there is an effect that the operating time and the recovery time can be set to arbitrary times required for the relay circuit.

【図面の簡単な説明】[Brief description of drawings]

【図1】実施例の回路図。FIG. 1 is a circuit diagram of an embodiment.

【図2】従来の回路図。FIG. 2 is a conventional circuit diagram.

【符号の説明】[Explanation of symbols]

2…フオトカプラ、4…FET、7…コンデンサ、8,
9…抵抗、10…トランジスタ、11…ダイオード。
2 ... Photo coupler, 4 ... FET, 7 ... Capacitor, 8,
9 ... Resistor, 10 ... Transistor, 11 ... Diode.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 オン・オフ入力信号を電気絶縁して取込
むフオトカプラと、 前記フオトカプラの出力素子に並列に設けられるコンデ
ンサと第1の抵抗との並列回路及び該並列回路に直列接
続される第2の抵抗と、 前記フオトカプラの出力素子と出力用半導体素子のゲー
ト間に設けられ前記第1の抵抗と第2の抵抗との接続点
電圧によってオンして半導体素子をオフさせるトランジ
スタと、 前記トランジスタのコレクタとエミッタ間に設けられ前
記半導体素子をオンさせる電流路を形成するダイオード
と、 を備えたことを特徴とする静止形補助リレー回路。
1. A photocoupler that electrically insulates an ON / OFF input signal, a parallel circuit of a capacitor and a first resistor provided in parallel with an output element of the photocoupler, and a first circuit connected in series to the parallel circuit. And a transistor provided between the output element of the photocoupler and the gate of the output semiconductor element to turn on the semiconductor element by a connection point voltage between the first resistor and the second resistor, and the transistor. A diode provided between the collector and the emitter of the diode to form a current path for turning on the semiconductor element, and a static auxiliary relay circuit.
JP3305792A 1991-11-21 1991-11-21 Static auxiliary relay circuit Expired - Fee Related JP2973654B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3305792A JP2973654B2 (en) 1991-11-21 1991-11-21 Static auxiliary relay circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3305792A JP2973654B2 (en) 1991-11-21 1991-11-21 Static auxiliary relay circuit

Publications (2)

Publication Number Publication Date
JPH05145392A true JPH05145392A (en) 1993-06-11
JP2973654B2 JP2973654B2 (en) 1999-11-08

Family

ID=17949416

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3305792A Expired - Fee Related JP2973654B2 (en) 1991-11-21 1991-11-21 Static auxiliary relay circuit

Country Status (1)

Country Link
JP (1) JP2973654B2 (en)

Also Published As

Publication number Publication date
JP2973654B2 (en) 1999-11-08

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