JPS6290500U - - Google Patents
Info
- Publication number
- JPS6290500U JPS6290500U JP18232185U JP18232185U JPS6290500U JP S6290500 U JPS6290500 U JP S6290500U JP 18232185 U JP18232185 U JP 18232185U JP 18232185 U JP18232185 U JP 18232185U JP S6290500 U JPS6290500 U JP S6290500U
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- base
- collector
- current
- hold capacitor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000003990 capacitor Substances 0.000 claims description 3
- 230000003139 buffering effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 5
Landscapes
- Electronic Switches (AREA)
- Analogue/Digital Conversion (AREA)
- Measurement Of Current Or Voltage (AREA)
- Processing Of Color Television Signals (AREA)
Description
第１図はこの考案の一実施例を示す接続図、第
２図はこの考案の他の実施例を示す接続図、第３
図は従来のサンプルホールド回路の例を示す接続
図、第４図は従来のサンプルホールド回路の各部
波形図である。
図面における主要な符号の説明、１：第１のト
ランジスタ、２：第２のトランジスタ、３：電源
端子、８：ホールドコンデンサ、１１：第３のト
ランジスタ、１３：第４のトランジスタ。
Figure 1 is a connection diagram showing one embodiment of this invention, Figure 2 is a connection diagram showing another embodiment of this invention, and Figure 3 is a connection diagram showing another embodiment of this invention.
The figure is a connection diagram showing an example of a conventional sample-and-hold circuit, and FIG. 4 is a waveform diagram of each part of the conventional sample-and-hold circuit. Explanation of main symbols in the drawings: 1: first transistor, 2: second transistor, 3: power supply terminal, 8: hold capacitor, 11: third transistor, 13: fourth transistor.
Claims (1)
差動接続され、上記第１のトランジスタのベース
に入力信号が印加され、上記第１のトランジスタ
のコレクタ及び上記第２のトランジスタのコレク
タの夫々と電源の一端間にカレントミラー回路が
接続され、上記第２のトランジスタのコレクタと
上記第２のトランジスタのベースとが接続されて
、この接続点がホールドコンデンサを介して上記
電源の他端に接続され、上記ホールドコンデンサ
の端子電圧がバツフア用の第３のトランジスタを
介して導出され、上記第１のトランジスタ及び上
記第２のトランジスタがサンプル期間にオンせし
められ、上記第１のトランジスタのコレクタが第
４のトランジスタのベースに接続され、上記第３
のトランジスタのベース電流と上記第４のトラン
ジスタのベース電流が略等しくなされたことを特
徴とするサンプルホールド回路。 A first transistor and a second transistor are differentially connected, an input signal is applied to the base of the first transistor, and a power source is connected to the collector of the first transistor and the collector of the second transistor, respectively. A current mirror circuit is connected between one end, the collector of the second transistor is connected to the base of the second transistor, this connection point is connected to the other end of the power supply via a hold capacitor, and the collector of the second transistor is connected to the base of the second transistor. The terminal voltage of the hold capacitor is derived through a third transistor for buffering, the first transistor and the second transistor are turned on during the sample period, and the collector of the first transistor is connected to the fourth transistor. connected to the base of the third
A sample hold circuit characterized in that the base current of the transistor and the base current of the fourth transistor are approximately equal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985182321U JPH0445199Y2 (en) | 1985-11-26 | 1985-11-26 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985182321U JPH0445199Y2 (en) | 1985-11-26 | 1985-11-26 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6290500U true JPS6290500U (en) | 1987-06-10 |
| JPH0445199Y2 JPH0445199Y2 (en) | 1992-10-23 |
Family
ID=31128011
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1985182321U Expired JPH0445199Y2 (en) | 1985-11-26 | 1985-11-26 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0445199Y2 (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60160099A (en) * | 1984-01-30 | 1985-08-21 | Toshiba Corp | Compensating circuit of holding voltage |
-
1985
- 1985-11-26 JP JP1985182321U patent/JPH0445199Y2/ja not_active Expired
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60160099A (en) * | 1984-01-30 | 1985-08-21 | Toshiba Corp | Compensating circuit of holding voltage |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0445199Y2 (en) | 1992-10-23 |
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