JPS6286737A - Substrate for face down bonding - Google Patents

Substrate for face down bonding

Info

Publication number
JPS6286737A
JPS6286737A JP60227377A JP22737785A JPS6286737A JP S6286737 A JPS6286737 A JP S6286737A JP 60227377 A JP60227377 A JP 60227377A JP 22737785 A JP22737785 A JP 22737785A JP S6286737 A JPS6286737 A JP S6286737A
Authority
JP
Japan
Prior art keywords
substrate
down bonding
face down
mold filling
filling holes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60227377A
Other languages
Japanese (ja)
Inventor
Kiyoyuki Shibata
柴田　清幸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP60227377A priority Critical patent/JPS6286737A/en
Publication of JPS6286737A publication Critical patent/JPS6286737A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To enable the freedom of pattern arrangement to augment on a substrate for face down bonding by perforating a plurality of mold filling holes in the substrate. CONSTITUTION:Mold filling holes 3 are perforated at plurality of places, for example, at two places, in a substrate 1. Hereby, patterns 2 can be arranged on the central part of the substrate. By perforating a plurality of mold filling holes in such a way, the freedom of pattern arrangement can be augmented on the substrate.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はフェイスダウンボンディング用基板の形状に関
する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the shape of a substrate for face-down bonding.

〔発明の概要〕[Summary of the invention]

本発明はフェイスダウンボンディング用基板において、
モールド元慎用の穴を複数あけることにより、基板のパ
ターン配置の自由１３１１したものである。The present invention provides a face-down bonding substrate that includes:
By making a plurality of holes for mold holes, the pattern arrangement of the substrate can be freely arranged.

〔従来技術〕[Prior art]

従来のフェイスダウンボッディング用基板は、第５図の
様にモールド充填用の穴が一ケ所であった。A conventional face-down bodding board has only one hole for mold filling, as shown in FIG.

〔発明が解決しようとする問題点及び目的〕しかし、前
述の従来技術ではモールド充填用の穴をＩＣ中央部に設
けなければならない為、基板のパターン配置が限られて
しまうという問題点を有する。[Problems and Objects to be Solved by the Invention] However, the above-mentioned prior art has the problem that the pattern arrangement on the substrate is limited because a hole for filling the mold must be provided in the center of the IC.

そこで本発明はこのような問題点を解決するもので、そ
の目的とするところは基板のパターン配置の自由変を増
すことにある。The present invention is intended to solve these problems, and its purpose is to increase the freedom of variation in pattern arrangement on a substrate.

〔問題点を解決するための手段〕[Means for solving problems]

本発明のフェイスダウンボンディング用基板は、モール
ド充填用の穴を複数あけたことを特徴とする。The face-down bonding substrate of the present invention is characterized by having a plurality of holes for mold filling.

〔実施例〕〔Example〕

第１図は本発明の実施例における平面図であって、モー
ルド充填用の穴を２ケ所あけることによシ、中央部分に
パターンを配置することが可能となる。FIG. 1 is a plan view of an embodiment of the present invention, and by making two holes for filling the mold, it is possible to arrange a pattern in the center.

〔発明の効果〕〔Effect of the invention〕

以上述べたように発明によればモールド充填用の穴を複
数あけることにより、基板のパターン配置の自由１１Ｅ
壇すという効果を有する。As described above, according to the invention, by making a plurality of holes for filling the mold, there is freedom in the pattern arrangement of the substrate.
It has the effect of giving a platform.

【図面の簡単な説明】[Brief explanation of drawings]

訊１図は２Ｉ−発明の一実施例を示す平面図。 第２図は本発明の一実施例を示すＶｆｒ面図。 第５図は従来のフェイスダウンボンディング用基板の平
面図。 第４図は従来のフェイスダウンボンディング用基板の断
面図。 １・・・基板 ２・・・パターン ５・・・モールド充填穴 ４　・・・　Ｉ　Ｃ 以　　　上Figure 1 is a plan view showing an embodiment of the invention. FIG. 2 is a Vfr side view showing an embodiment of the present invention. FIG. 5 is a plan view of a conventional face-down bonding substrate. FIG. 4 is a cross-sectional view of a conventional face-down bonding substrate. 1...Substrate 2...Pattern 5...Mold filling hole 4...IC or more

Claims (1)

【特許請求の範囲】[Claims] モールド剤充填用の穴が複数あいていることを特徴とす
るフェイスダウンボンディング用基板。A face-down bonding substrate characterized by having multiple holes for filling molding agent.
JP60227377A 1985-10-11 1985-10-11 Substrate for face down bonding Pending JPS6286737A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60227377A JPS6286737A (en) 1985-10-11 1985-10-11 Substrate for face down bonding

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60227377A JPS6286737A (en) 1985-10-11 1985-10-11 Substrate for face down bonding

Publications (1)

Publication Number Publication Date
JPS6286737A true JPS6286737A (en) 1987-04-21

Family

ID=16859854

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60227377A Pending JPS6286737A (en) 1985-10-11 1985-10-11 Substrate for face down bonding

Country Status (1)

Country Link
JP (1) JPS6286737A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0645806A1 (en) * 1993-04-08 1995-03-29 Seiko Epson Corporation Semiconductor device
WO1998018162A1 (en) * 1996-10-17 1998-04-30 Seiko Epson Corporation Film carrier tape and semiconductor device, method for manufacturing them, and circuit board

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0645806A1 (en) * 1993-04-08 1995-03-29 Seiko Epson Corporation Semiconductor device
EP0645806A4 (en) * 1993-04-08 1995-10-11 Seiko Epson Corp Semiconductor device.
US5563445A (en) * 1993-04-08 1996-10-08 Seiko Epson Corporation Semiconductor device
WO1998018162A1 (en) * 1996-10-17 1998-04-30 Seiko Epson Corporation Film carrier tape and semiconductor device, method for manufacturing them, and circuit board
US6262473B1 (en) 1996-10-17 2001-07-17 Seiko Epson Corporation Film carrier tape and semiconductor device, method of making the same and circuit board

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