JPS6284839U - - Google Patents
Info
- Publication number
- JPS6284839U JPS6284839U JP17718285U JP17718285U JPS6284839U JP S6284839 U JPS6284839 U JP S6284839U JP 17718285 U JP17718285 U JP 17718285U JP 17718285 U JP17718285 U JP 17718285U JP S6284839 U JPS6284839 U JP S6284839U
- Authority
- JP
- Japan
- Prior art keywords
- processing device
- instruction
- under test
- computer
- console
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012360 testing method Methods 0.000 claims description 8
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Test And Diagnosis Of Digital Computers (AREA)
Description
図はこの考案の一実施例を示す構成図であり、
１は被試験計算機システム、２は本考案の計算
機試験装置、３は処理装置、４は乱数発生機構、
５は命令実行シミユレータ機構、６は被試験命令
テーブル、７はコンソルを示し、８，９，１０，
１１は被試験計算機の内部構成要素で、それぞれ
コンソル、中央処理装置（ＣＰＵ）、メモリ、入
出力（Ｉ／Ｏ）を示す。
The figure is a configuration diagram showing an embodiment of this invention, in which 1 is a computer system under test, 2 is a computer testing device of this invention, 3 is a processing device, 4 is a random number generation mechanism,
5 is an instruction execution simulator mechanism, 6 is an instruction table under test, 7 is a console, 8, 9, 10,
Reference numerals 11 denote internal components of the computer under test, which are a console, a central processing unit (CPU), a memory, and an input/output (I/O), respectively.
Claims (1)
ためのコンソルと、前記処理装置に乱数を供給す
るための乱数発生機構と、被試験計算機の全命令
（インストラクシヨンセツト）をリストアツプし
た被試験命令テーブルと、被試験命令の動作をシ
ミユレートし、実行結果を前記処理装置に出力す
る命令実行シミユレータ機構とを備えたことを特
徴とする計算機試験装置。 A processing device, a console for giving operation commands to the processing device, a random number generation mechanism for supplying random numbers to the processing device, and a test object in which all instructions (instruction set) of the computer under test are restored. A computer testing device comprising: an instruction table; and an instruction execution simulator mechanism that simulates the operation of an instruction under test and outputs an execution result to the processing device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17718285U JPS6284839U (en) | 1985-11-18 | 1985-11-18 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17718285U JPS6284839U (en) | 1985-11-18 | 1985-11-18 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6284839U true JPS6284839U (en) | 1987-05-30 |
Family
ID=31118144
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17718285U Pending JPS6284839U (en) | 1985-11-18 | 1985-11-18 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6284839U (en) |
-
1985
- 1985-11-18 JP JP17718285U patent/JPS6284839U/ja active Pending
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