JPS6284544A - Manufacture of capacitance - Google Patents
Manufacture of capacitanceInfo
- Publication number
- JPS6284544A JPS6284544A JP22526085A JP22526085A JPS6284544A JP S6284544 A JPS6284544 A JP S6284544A JP 22526085 A JP22526085 A JP 22526085A JP 22526085 A JP22526085 A JP 22526085A JP S6284544 A JPS6284544 A JP S6284544A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- silicon
- silicon nitride
- nitride layer
- onto
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 19
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 19
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 9
- 238000010438 heat treatment Methods 0.000 claims abstract description 8
- 239000003990 capacitor Substances 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 7
- 229910044991 metal oxide Inorganic materials 0.000 claims description 4
- 150000004706 metal oxides Chemical class 0.000 claims description 4
- 230000001590 oxidative effect Effects 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 abstract description 8
- 239000010703 silicon Substances 0.000 abstract description 8
- 239000000758 substrate Substances 0.000 abstract description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 7
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 7
- 229910052760 oxygen Inorganic materials 0.000 abstract description 7
- 239000001301 oxygen Substances 0.000 abstract description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 7
- 230000002950 deficient Effects 0.000 abstract description 4
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 abstract 2
- 239000010410 layer Substances 0.000 description 46
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 4
- 230000015654 memory Effects 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000010292 electrical insulation Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- -1 'ri Substances 0.000 description 1
- 238000002048 anodisation reaction Methods 0.000 description 1
- YXTPWUNVHCYOSP-UHFFFAOYSA-N bis($l^{2}-silanylidene)molybdenum Chemical compound [Si]=[Mo]=[Si] YXTPWUNVHCYOSP-UHFFFAOYSA-N 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910021344 molybdenum silicide Inorganic materials 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 229910052762 osmium Inorganic materials 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/92—Capacitors having potential barriers
- H01L29/94—Metal-insulator-semiconductors, e.g. MOS
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は容量の製造方法に関し、特にＴ Ｈｚ０６ ｒ
ＮｂｚＯ５，ＴｉＯ２，ＢａＴｉ０． などの金属酸
化物誘電体層を有する容量の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method for manufacturing a capacitor, and in particular to a method for manufacturing a capacitor.
NbzO5, TiO2, BaTi0. The present invention relates to a method of manufacturing a capacitor having a metal oxide dielectric layer, such as a metal oxide dielectric layer.
ダイナミックランダム・アクセス・メモリのような、構
成要素として容量を備えた半導体装置の集積度は年々高
くなりている。従来、高集積化は配線や回路素子のパタ
ーンを微細化することで行われてきｆ、Ｌかし、このよ
うな微細化は信号に対応した蓄積電荷量を少なくするこ
とになり、α線などの放射線によるメモリの誤動作（ン
フトエラー）を防止する上で好しくない。The degree of integration of semiconductor devices such as dynamic random access memories that have capacitance as a component is increasing year by year. Conventionally, high integration has been achieved by miniaturizing the patterns of wiring and circuit elements, but such miniaturization reduces the amount of accumulated charge corresponding to signals, which increases the This is undesirable in terms of preventing memory malfunctions (ft errors) caused by radiation.
従来、容量の誘電体層を薄くシ、メモリセルの容量値を
大きくすることによりこの問題を解決してきた。しかし
、誘電体層の薄膜化が進むと、例えば６０人の５ｉＯ１
層に５■の電圧を印加するとトンネル電流が流れるため
原理的に絶縁膜として使用できないという問題が−ある
。Conventionally, this problem has been solved by making the dielectric layer of the capacitor thinner and increasing the capacitance value of the memory cell. However, as dielectric layers become thinner, for example, 60 people's 5iO1
There is a problem in that when a voltage of 5 .mu. is applied to the layer, a tunnel current flows, so in principle it cannot be used as an insulating film.
そこで、従来、容量の占める面積が小さくかつ大きい容
量値を得るために、誘電体材料として比誘電率の高いＴ
ａ２０５＋Ｎｂ２０ｒ＋ ＢａＴｌＯ３＋ ’ｒ、ｏ、
などの誘電体層を用いることが試みられている。Therefore, conventionally, in order to obtain a large capacitance value with a small area occupied by the capacitor, T
a205+Nb20r+ BaTlO3+ 'r, o,
Attempts have been made to use dielectric layers such as .
これらの誘電体層を形成する手段には、例えばＴａｔ
’ｒｉ、 Ｎｂ＊ Ｂａ などの金属材料を真空中で
蒸着し次後、酸素雰囲気中で熱処理する、あるいは陽極
酸化するなどの手段で酸化することにより。Means for forming these dielectric layers include, for example, Tat
By depositing a metal material such as 'ri, Nb*Ba, etc. in a vacuum and then oxidizing it by heat treatment in an oxygen atmosphere or anodization.
もしくはＴａｚＯａｓ ’ｒｔσＺ＊ Ｎｂ雪ＯＳｓ
１３ａ’Ｉ’ｉｏｓなど積するなどの方法がある。Or TazOas 'rtσZ* Nb snow OSs
There are methods such as multiplying 13a'I'ios.
上述し光従来の容量の製造方法は、熱処理中に誘電体層
内部で多結晶粒が成長したり、あるいは誘電体層と容量
の電極との間に反応が生じて膜質が劣化し、ピンホール
や電気的絶縁性の悪い部分が局所的に生じるので、漏れ
電流の大きな容量が得られるという欠点がある。As mentioned above, in the conventional optical capacitor manufacturing method, polycrystalline grains grow inside the dielectric layer during heat treatment, or a reaction occurs between the dielectric layer and the electrode of the capacitor, deteriorating the film quality and causing pinholes. This has the disadvantage that a large leakage current capacity is obtained because there are localized areas with poor electrical insulation.
本発明の目的は、漏れ電流が小さく容量値の大きな容量
が得られる容量の製造方法を提供することにある。An object of the present invention is to provide a method for manufacturing a capacitor that can obtain a capacitor with a small leakage current and a large capacitance value.
本発明の容量の製造方法は、金属酸化物を含む誘電体層
上に窒化シリコン層を設けｔのち、酸化性雰囲気中で熱
処理を行ない前記窒化シリコン層の表面に酸化シリコン
層を形成する工程を含んでいる。The capacitor manufacturing method of the present invention includes the steps of providing a silicon nitride layer on a dielectric layer containing a metal oxide, and then performing heat treatment in an oxidizing atmosphere to form a silicon oxide layer on the surface of the silicon nitride layer. Contains.
次に本発明の実施例について図面を参照して説明する。 Next, embodiments of the present invention will be described with reference to the drawings.
第１図（ａ）〜（ｄ）は本発明の一実施例を説明するた
めの製造工程順に配列し友容量の断面図÷ある。FIGS. 1(a) to 1(d) are cross-sectional views of companion capacitors arranged in the order of manufacturing steps to explain one embodiment of the present invention.
まず、第１＠（場に示すように、シリコン基板１０表面
にＴ３を真空蒸着などの気相成長法を用いて被着させに
後、４００〜６００℃ の熱酸化処理を行うか、もしく
はＣＶＤ法、スパッタ法などの手段により厚さ１００〜
８００人のＴａ、Ｏｓ層２を形成する。First, as shown in the first step, T3 is deposited on the surface of the silicon substrate 10 using a vapor phase growth method such as vacuum evaporation, and then thermal oxidation treatment at 400 to 600 degrees Celsius or CVD Thickness: 100~ by means of method, sputtering method, etc.
A Ta, Os layer 2 of 800 layers is formed.
次に、第１図などの手段により厚さ１００〜８００人の
Ｔａ２０ｔＪ１２１ｊｔ形成スル。Next, Ta20tJ121jt is formed to a thickness of 100 to 800 people by the means shown in FIG.
次に、第１図（ロ）に示すように４ Ｔ１２０１１層２
０表面にＣＶＤ法などの手段で、厚さ１００〜２００人
の窒化シリコン層３ｔ−形成する。この窒化シリコン層
３は、Ｔａｘｏｓ層２と後述の多結晶シリコン電極５と
の反応を防止すると共に、後に行われる酸化工程で余分
の酸素の拡散を防止するために設けるものである。続い
て、酸素又は水分を含む雰囲気（スチーム）中において
８００〜１０００℃ の温度で熱処理を行うと、第１図
（Ｃ）に示すように、窒化シリコン層３の表面に薄い酸
化シリコン層４が形成される。窒化シリコン層３中の酸
素の拡散係数が小さいため表面にわずかの酸化膜が形成
されるのみであるが、同一に、窒化シリコン層３およヒ
Ｔａｔｏｓ層２にピンホールや電気的絶縁性が悪い部分
が存在する場合、これらの欠陥部分が熱処理によって修
復されるほか、これらの欠陥部分を通って酸素がシリコ
ン基板１表面に選択的に拡散し酸化膜が形成される。。Next, as shown in Figure 1 (b), 4 T12011 layers 2
A silicon nitride layer 3t- having a thickness of 100 to 200 layers is formed on the surface of the silicon nitride layer 3t by CVD or the like. This silicon nitride layer 3 is provided to prevent a reaction between the Taxos layer 2 and a polycrystalline silicon electrode 5, which will be described later, and to prevent excess oxygen from diffusing in the oxidation step to be performed later. Subsequently, when heat treatment is performed at a temperature of 800 to 1000°C in an atmosphere containing oxygen or moisture (steam), a thin silicon oxide layer 4 is formed on the surface of the silicon nitride layer 3, as shown in FIG. 1(C). It is formed. Since the diffusion coefficient of oxygen in the silicon nitride layer 3 is small, only a slight oxide film is formed on the surface, but there are also pinholes and electrical insulation in the silicon nitride layer 3 and the Tatos layer 2. If defective portions exist, these defective portions are repaired by heat treatment, and oxygen is selectively diffused to the surface of the silicon substrate 1 through these defective portions to form an oxide film. .
更に、第１図（ｄ）に示すように、酸化シリコン層４０
表面に多結晶シリコン層５を選択的に形成すると、シリ
コン基板１と多結晶シリコン層とを電極とする容量がで
きる。Furthermore, as shown in FIG. 1(d), a silicon oxide layer 40 is formed.
When the polycrystalline silicon layer 5 is selectively formed on the surface, a capacitor is created using the silicon substrate 1 and the polycrystalline silicon layer as electrodes.
以上、１ｔ−シリコン基板、２ Ｋｌ” Ｔａｌｏｌ層
、３を窒化シリコン層、４を酸化シリコン層、５を多結
晶シリコン層として説明したが、１を多結晶シリコンや
高融点金属などの電極もしくは他の半導体基板％ ２を
ＮｂｚＯｓ、 Ｂａ’ｒｉｏ３などの比誘電率の高い誘
電体層、５を高融点金属などの電極もしくはモリブデン
シリサイドやタンタルシリサイドなどのシリサイド電極
を用いてもよい。In the above explanation, 1t-silicon substrate, 2 Kl" Talol layer, 3 a silicon nitride layer, 4 a silicon oxide layer, and 5 a polycrystalline silicon layer are used. 2 may be a dielectric layer having a high relative dielectric constant such as NbzOs or Ba'rio3, and 5 may be an electrode made of a high melting point metal or a silicide electrode such as molybdenum silicide or tantalum silicide.
また、上記説明では、誘電体層２ｔｆｆａｚＯｓ単層と
したが＊ ’Ｉ’ａｚｏｓ／’ｓｔｏｗ もしくはＴ
１２０ｓ／８ｉｘＮ４のように２層としてもよく、この
場合、薄い８ｉ０゜〔発明の効果〕
以上説明したように本発明はｓ Ｔａ２０５ ＊ Ｎｂ
意Ｏｉ ＩＢＪＩＴｉＯ，又はＴｉＯ２などの比誘電率
の高い誘電体層に窒化シリコン層を積層し几のち酸化し
て、窒化シリコン層上に薄い酸化シリコン層を設けるも
のであるから、誘電体層のピンホールなどの欠陥部が修
復され漏れ電流が小さくなり、窒化シリコン層の酸化は
ごくわずかしか行なわれないので容量値の低下は殆んど
生じることはなく、従って、漏れ電流が小さく容量値の
大きな容量が得られるという効果がある。In addition, in the above explanation, the dielectric layer 2 is a single layer of tffazOs, but * 'I'azos/'stow or T
It may be two layers like 120s/8ixN4, and in this case, it is thin 8i0゜ [Effects of the Invention] As explained above, the present invention provides sTa205*Nb
A silicon nitride layer is laminated on a dielectric layer with a high dielectric constant such as IBJITiO or TiO2, and then oxidized to form a thin silicon oxide layer on the silicon nitride layer, so the pins of the dielectric layer are Defects such as holes are repaired and the leakage current is reduced, and the silicon nitride layer is only slightly oxidized, so there is almost no decrease in capacitance. Therefore, the leakage current is small and the capacitance is large. This has the effect of increasing capacity.
【図面の簡単な説明】
第１図（ａ）〜（イ）は本発明の一実施例を説明するた
めの製造工程順に配列し友容量の断面図である。
１・・・・工シリコン基板、２・・・・・・’Ｆａｇｏ
ＩＩ層、３・・・・・・窒化シリコン層、４・・・・・
・酸化シリコン層％ ５・・・・・・多結晶シリコン層
。
第１図
（ｌｌ）
（ｃ）
（ｄ）BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1(a) to 1(a) are cross-sectional views of companion capacitors arranged in the order of manufacturing steps to explain one embodiment of the present invention. 1... Engineering silicon substrate, 2...'Fago
II layer, 3...Silicon nitride layer, 4...
-Silicon oxide layer% 5...Polycrystalline silicon layer. Figure 1 (ll) (c) (d)
Claims (1)
のち、酸化性雰囲気中で熱処理を行ない前記窒化シリコ
ン層の表面に酸化シリコン層を形成する工程を含むこと
を特徴とする容量の製造方法。Manufacturing a capacitor comprising the steps of providing a silicon nitride layer on a dielectric layer containing a metal oxide and then performing heat treatment in an oxidizing atmosphere to form a silicon oxide layer on the surface of the silicon nitride layer. Method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22526085A JPS6284544A (en) | 1985-10-08 | 1985-10-08 | Manufacture of capacitance |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22526085A JPS6284544A (en) | 1985-10-08 | 1985-10-08 | Manufacture of capacitance |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6284544A true JPS6284544A (en) | 1987-04-18 |
| JPH0584672B2 JPH0584672B2 (en) | 1993-12-02 |
Family
ID=16826524
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22526085A Granted JPS6284544A (en) | 1985-10-08 | 1985-10-08 | Manufacture of capacitance |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6284544A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58112360A (en) * | 1981-12-25 | 1983-07-04 | Nec Corp | Capacitor for semiconductor device and manufacture thereof |
| JPS58180014A (en) * | 1982-04-16 | 1983-10-21 | 富士通株式会社 | Thin film forming method |
-
1985
- 1985-10-08 JP JP22526085A patent/JPS6284544A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58112360A (en) * | 1981-12-25 | 1983-07-04 | Nec Corp | Capacitor for semiconductor device and manufacture thereof |
| JPS58180014A (en) * | 1982-04-16 | 1983-10-21 | 富士通株式会社 | Thin film forming method |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0584672B2 (en) | 1993-12-02 |
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