JPS5814537A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5814537A
JPS5814537A JP56111951A JP11195181A JPS5814537A JP S5814537 A JPS5814537 A JP S5814537A JP 56111951 A JP56111951 A JP 56111951A JP 11195181 A JP11195181 A JP 11195181A JP S5814537 A JPS5814537 A JP S5814537A
Authority
JP
Japan
Prior art keywords
film
nitride film
oxide film
pinhole
capacitor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56111951A
Other languages
Japanese (ja)
Other versions
JPS6351375B2 (en
Inventor
Yutaka Tomita
豊 冨田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56111951A priority Critical patent/JPS5814537A/en
Publication of JPS5814537A publication Critical patent/JPS5814537A/en
Publication of JPS6351375B2 publication Critical patent/JPS6351375B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment

Abstract

PURPOSE:To obtain a device having an internal capacitor which has a small area, a large capacity and high voltage resistance, by forming an Si3N4 film on an Si substrate and then oxidizing the film by water vapor at a temperature not higher than 1,000 deg.C. CONSTITUTION:Prior to the formation of an Al electrode 5, an Si substrate 1 to which an oxide film 2 and a nitride film 3 are connected is subjected to oxidation treatment for about six minutes in water vapor of 1,000 deg.C to grow an oxide film 6 of about 1,000Angstrom at the part of a pinhole 4. Thereafer the Al electrode 5 is provided on the nitride film 3. A capacitor the two electrodes of which are Al and Si substrates constituted in this way is made free from imperfections, since the pinhole is filled up with the oxide film, and has a large capacity with a small area, being sufficiently resistant to a voltage of about 100V.

Description

【発明の詳細な説明】 本発明は、半導体装置の製造方法にかかり、とくにシリ
コン基板上の誘電体層としての窒化膜を形成する工程を
含む半導体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a semiconductor device including a step of forming a nitride film as a dielectric layer on a silicon substrate.

半導体装置、特にアナログ型集積回路においては、内蔵
コンデンサを有することが多く、これらのコンデンサに
は集積回路装置としては比較的高電圧（３０■以上）が
加わることが多い。従来、特にシリコンの半導体集積回
路のコンデンサで、容量が数ｐＦ〜数＋ｐＦ程度のもの
は、シリコン基板上に形成された酸化膜または窒化膜を
誘電体層として、前記各誘電体層の底部に位置する拡散
層と誘電体層上の金属電極とによって形成されていた。Semiconductor devices, particularly analog integrated circuits, often have built-in capacitors, and relatively high voltages (30 volts or more) are often applied to these capacitors for integrated circuit devices. Conventionally, capacitors for silicon semiconductor integrated circuits, in particular those with a capacitance of several pF to several + pF, have an oxide film or a nitride film formed on a silicon substrate as a dielectric layer, and the bottom of each dielectric layer is It was formed by a disposed diffusion layer and a metal electrode on a dielectric layer.

このような構造では、半導体装置の小型化の為、誘電体
の膜厚は薄いほどコンデンサの容量の面積比は大になる
。したがって、半導体装置の小型化の為、誘電体の膜厚
は薄いほど高集積化には有利である。しかし、膜厚を薄
くすると、膜厚自体による耐圧が問題になるほか、窒化
膜は通常気相成長法によって形成される為ピンホールが
多くなる。In such a structure, in order to miniaturize the semiconductor device, the thinner the dielectric film is, the larger the area ratio of the capacitance of the capacitor becomes. Therefore, in order to miniaturize semiconductor devices, the thinner the dielectric film is, the more advantageous it is to achieving higher integration. However, if the film thickness is made thinner, the breakdown voltage due to the film thickness itself becomes a problem, and since the nitride film is usually formed by vapor phase growth, pinholes increase.

しかし、誘電体としては酸化膜より窒化膜を主体に使用
した方が誘電率が窒化膜は酸化膜の２倍近くある為に、
高集積化に有利である。上記理由で従来窒化膜を主なる
誘電体層としてコンデンサを集積回路基板上に形成する
と、電圧印加によりピンホール部に起因するコンデンサ
の絶縁破壊が発生した。However, it is better to use a nitride film as a dielectric material rather than an oxide film because the dielectric constant of the nitride film is nearly twice that of the oxide film.
It is advantageous for high integration. For the above reasons, when a capacitor is conventionally formed on an integrated circuit board using a nitride film as the main dielectric layer, dielectric breakdown of the capacitor due to the pinhole portion occurs due to voltage application.

本発明の目的は、上記の欠点を除去して、小面積で容量
の大きい、かつ耐圧も大きい内部コンデンサを有する半
導体装置の製造方法を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks and provide a method for manufacturing a semiconductor device having an internal capacitor having a small area, large capacity, and high breakdown voltage.

本発明の半導体装置の製造方法においては、特にシリコ
ン基板上に形成する窒化膜上から、水蒸気により１００
ＯＣ以下の温度で酸化膜を窒化膜のピンホール部に成長
させて、ピンホールによる欠点を除去している。また、
水蒸気による酸化の為、時間は短くてよく、温度が１０
０ＯＣ以下の為、前工程で形成されている拡散層に影響
を与えることが少く、かつ窒化膜はほとんど酸化されな
い。In the method for manufacturing a semiconductor device of the present invention, in particular, a nitride film formed on a silicon substrate is coated with water vapor to form a 100%
An oxide film is grown on the pinhole portion of the nitride film at a temperature below OC to eliminate defects caused by the pinhole. Also,
Because the oxidation is carried out by water vapor, the time may be short and the temperature is 10°C.
Since it is less than 0OC, it has little effect on the diffusion layer formed in the previous step, and the nitride film is hardly oxidized.

電１図は従来の製造方法で作成されたコンデンサの部分
断面図である。コンデンサの誘電体層としてシリコン基
板１の上に２００Ａの酸化膜２が形成されており、その
上に厚さ１００ＯＡの窒化膜３が形成されている。しか
し、気相成長法で形成される窒化膜３にはピンホール４
が発生し易Ｋ、ピンホールがなければ１１０〜１３０ｖ
位のコンデンサの耐圧がＩＯＶ前後になってしま５゜　
　　′つぎに本発明を実施例により説明する。Figure 1 is a partial cross-sectional view of a capacitor manufactured by a conventional manufacturing method. An oxide film 2 having a thickness of 200 Å is formed on a silicon substrate 1 as a dielectric layer of the capacitor, and a nitride film 3 having a thickness of 100 Å is formed thereon. However, there are pinholes 4 in the nitride film 3 formed by vapor phase growth.
Easy to occur, 110-130v if there is no pinhole
The withstand voltage of the capacitor is around IOV5゜
'Next, the present invention will be explained by way of examples.

第２図は本発明方法により作成した集積回路内部コンデ
ンサの部分断面図である。まず、第１図で示すアルミ電
極５の形成前の、酸化膜２、窒化膜３が被着されたシリ
コン基板１をもつ試料に対し、雰囲気温度ｘｏｏｏｃの
水蒸気により６分間の酸化処理を行い、ピンホール部４
に１００ＯＡ程度の酸化膜６を成長させる。その後、ア
ルミ電極５を窒化膜３の上に形成する。FIG. 2 is a partial cross-sectional view of an integrated circuit internal capacitor made by the method of the present invention. First, a sample having a silicon substrate 1 on which an oxide film 2 and a nitride film 3 are deposited before the formation of an aluminum electrode 5 shown in FIG. 1 is subjected to an oxidation treatment for 6 minutes using water vapor at an ambient temperature of Pinhole part 4
Then, an oxide film 6 of about 100 OA is grown. Thereafter, an aluminum electrode 5 is formed on the nitride film 3.

このようにして形成された窒化膜３を誘電体層とし、ア
ルミ電極５とシリコン基板ｌを両電極とするコンデンサ
は、ピンホール４が絶縁物の酸化膜６で充填されている
ので、ピンホールの欠かんはなくなり、小面積で比較的
大きな容量を有し、かつ１００ｖ程度の十分な耐圧を示
す。In a capacitor in which the nitride film 3 formed in this way is used as a dielectric layer, and the aluminum electrode 5 and the silicon substrate 1 are used as both electrodes, the pinhole 4 is filled with an oxide film 6 of an insulator. It has a relatively large capacity in a small area, and has a sufficient withstand voltage of about 100V.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来の製造方法で作成された集積回路内部コン
デンサの部分断面図、第２図は本発明方法により作成さ
れたコンデンサの部分断面図である。 １・・・・・・シリコン基板、２・−軸・酸化膜、３・
・・・・・窒化膜、４・・・・・・ピンホール、５・・
・・−アルミ電極、６・・・・・・ピンホール部の酸化
膜。 篤　ｆ　図 寮　Ｚ　図FIG. 1 is a partial sectional view of an integrated circuit internal capacitor manufactured by a conventional manufacturing method, and FIG. 2 is a partial sectional view of a capacitor manufactured by the method of the present invention. 1...Silicon substrate, 2.-axis/oxide film, 3.
...Nitride film, 4...Pinhole, 5...
...-Aluminum electrode, 6... Oxide film at the pinhole part. Atsushi f Zuryo Z diagram

Claims (1)

【特許請求の範囲】[Claims] シリコン基板上に窒化膜を形成した後、水蒸気により１
００ＯＣ以下の温度で酸化する工程を含むことを特徴と
する半導体装置の製造方法。After forming a nitride film on a silicon substrate, 1
A method for manufacturing a semiconductor device, comprising a step of oxidizing at a temperature of 00OC or less.
JP56111951A 1981-07-17 1981-07-17 Manufacture of semiconductor device Granted JPS5814537A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56111951A JPS5814537A (en) 1981-07-17 1981-07-17 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56111951A JPS5814537A (en) 1981-07-17 1981-07-17 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS5814537A true JPS5814537A (en) 1983-01-27
JPS6351375B2 JPS6351375B2 (en) 1988-10-13

Family

ID=14574234

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56111951A Granted JPS5814537A (en) 1981-07-17 1981-07-17 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5814537A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60170440U (en) * 1984-04-20 1985-11-12 株式会社河合楽器製作所 Soundproof room floor structure
JPS62135738U (en) * 1986-02-21 1987-08-26
US5079191A (en) * 1985-11-29 1992-01-07 Hitachi, Ltd. Process for producing a semiconductor device
EP0535553A2 (en) * 1991-09-30 1993-04-07 Motorola, Inc. Process for plugging defects in a dielectric layer of a semiconductor device

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS504434A (en) * 1973-05-17 1975-01-17
JPS5394780A (en) * 1977-01-14 1978-08-19 Hitachi Ltd Manufacture of semiconductor device
JPS5438780A (en) * 1977-08-31 1979-03-23 Cho Lsi Gijutsu Kenkyu Kumiai Semiconductor
JPS54109771A (en) * 1978-02-16 1979-08-28 Fujitsu Ltd Stabilizing method for surface protective film of semiconductor
JPS5522863A (en) * 1978-08-07 1980-02-18 Nec Corp Manufacturing method for semiconductor device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS504434A (en) * 1973-05-17 1975-01-17
JPS5394780A (en) * 1977-01-14 1978-08-19 Hitachi Ltd Manufacture of semiconductor device
JPS5438780A (en) * 1977-08-31 1979-03-23 Cho Lsi Gijutsu Kenkyu Kumiai Semiconductor
JPS54109771A (en) * 1978-02-16 1979-08-28 Fujitsu Ltd Stabilizing method for surface protective film of semiconductor
JPS5522863A (en) * 1978-08-07 1980-02-18 Nec Corp Manufacturing method for semiconductor device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60170440U (en) * 1984-04-20 1985-11-12 株式会社河合楽器製作所 Soundproof room floor structure
US5079191A (en) * 1985-11-29 1992-01-07 Hitachi, Ltd. Process for producing a semiconductor device
JPS62135738U (en) * 1986-02-21 1987-08-26
JPH0436355Y2 (en) * 1986-02-21 1992-08-27
EP0535553A2 (en) * 1991-09-30 1993-04-07 Motorola, Inc. Process for plugging defects in a dielectric layer of a semiconductor device

Also Published As

Publication number Publication date
JPS6351375B2 (en) 1988-10-13

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