JPH09246082A - Capacitance element and method of manufacturing - Google Patents
Capacitance element and method of manufacturingInfo
- Publication number
- JPH09246082A JPH09246082A JP8055733A JP5573396A JPH09246082A JP H09246082 A JPH09246082 A JP H09246082A JP 8055733 A JP8055733 A JP 8055733A JP 5573396 A JP5573396 A JP 5573396A JP H09246082 A JPH09246082 A JP H09246082A
- Authority
- JP
- Japan
- Prior art keywords
- platinum
- forming
- lower electrode
- film
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、強誘電性を有する
金属酸化物を容量絶縁膜とする容量素子およびその製造
方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capacitive element using a metal oxide having ferroelectricity as a capacitive insulating film and a method for manufacturing the same.
【0002】[0002]
【従来の技術】低動作電圧、高速書き込みおよび高速読
み出し可能な不揮発性RAMの実用化を目指し、自発分
極特性を有する強誘電体膜を容量絶縁膜とする容量素子
を半導体集積回路の上に形成するための技術開発が盛ん
に行われている。2. Description of the Related Art A capacitive element having a ferroelectric film having a spontaneous polarization characteristic as a capacitive insulating film is formed on a semiconductor integrated circuit in order to put a nonvolatile RAM capable of low operating voltage, high speed writing and high speed reading into practical use. The technology development for doing so is being actively done.
【0003】以下、従来の容量素子およびその製造方法
を図6の工程断面図を用いて説明する。A conventional capacitive element and a method of manufacturing the same will be described below with reference to process sectional views of FIGS.
【0004】図6(a)に示すように、シリコン基板よ
りなる支持基板1上に層間絶縁膜2となるシリコン酸化
膜を形成する。次に図6(b)に示すように、層間絶縁
膜2の上に密着層3となる膜厚が約20nmの金属チタ
ンおよび下部電極4となる膜厚が300nmの白金を、
室温で、アルゴンガスを用いたスパッタリング法により
連続して形成する。次に図6(c)に示すように下部電
極4の上に容量絶縁膜5となる組成がSrBi2Ta2O
9である強誘電体膜をスピンオン法で塗布し800℃で
焼成する。次に図6(d)に示すように容量絶縁膜5の
上に上部電極6となる白金をスパッタリング法により形
成する。さらに図6(e)に示すように写真食刻法とド
ライエッチング法により加工を行い、容量素子を形成す
る。As shown in FIG. 6A, a silicon oxide film to be an interlayer insulating film 2 is formed on a supporting substrate 1 made of a silicon substrate. Next, as shown in FIG. 6B, metal titanium having a film thickness of about 20 nm to be the adhesion layer 3 and platinum having a film thickness of 300 nm to be the lower electrode 4 are formed on the interlayer insulating film 2.
It is continuously formed at room temperature by a sputtering method using argon gas. Next, as shown in FIG. 6C, the composition forming the capacitive insulating film 5 on the lower electrode 4 is SrBi 2 Ta 2 O.
The ferroelectric film of No. 9 is applied by the spin-on method and baked at 800 ° C. Next, as shown in FIG. 6D, platinum serving as the upper electrode 6 is formed on the capacitive insulating film 5 by the sputtering method. Further, as shown in FIG. 6E, processing is performed by a photo-etching method and a dry etching method to form a capacitive element.
【0005】[0005]
【発明が解決しようとする課題】しかしながら従来の構
造およびその製造方法では、下部電極4を形成する白金
を室温で形成しているため、柱状結晶粒の並んだ荒い膜
質であるため結晶粒界を通じて密着層3の金属成分が、
下部電極4へ拡散し易く、密着層3が消滅して密着強度
が劣化しはがれが生じたり、さらに容量絶縁膜5にまで
拡散して容量素子の電気的特性が劣化するという課題を
有していた。However, in the conventional structure and the manufacturing method thereof, since platinum forming the lower electrode 4 is formed at room temperature, it has a rough film quality in which columnar crystal grains are lined up, and therefore, through the grain boundaries. The metal component of the adhesion layer 3 is
There is a problem that it is easy to diffuse to the lower electrode 4, the adhesion layer 3 disappears, the adhesion strength deteriorates and peeling occurs, and further, it diffuses to the capacitance insulating film 5 and the electrical characteristics of the capacitance element deteriorate. It was
【0006】本発明は上記の従来の課題を解決するもの
で、緻密な膜質の白金を形成することにより、はがれや
電気的特性劣化のない容量素子およびその製造方法を提
供することを目的とする。The present invention solves the above-mentioned conventional problems, and an object of the present invention is to provide a capacitive element which is free from peeling and deterioration of electric characteristics by forming a dense film of platinum, and a manufacturing method thereof. .
【0007】[0007]
【課題を解決するための手段】この目的を達成するため
に本発明の容量素子は、密着層の上に形成された下部電
極を形成する白金が、2×109dyn/cm2以上の引
っ張り応力の内部応力を有するものであり、その製造方
法は、下部電極を形成する白金を基板温度を200℃以
上600℃以下にしてアルゴンガスによるスパッタリン
グ法により形成するものである。In order to achieve this object, the capacitance element of the present invention is such that platinum forming the lower electrode formed on the adhesion layer has a tensile strength of 2 × 10 9 dyn / cm 2 or more. It has internal stress, and its manufacturing method is to form platinum forming the lower electrode by a sputtering method using argon gas at a substrate temperature of 200 ° C. or higher and 600 ° C. or lower.
【0008】本発明によれば、緻密な膜質の白金を形成
することができ、はがれや電気的特性劣化のない容量素
子が得られる。According to the present invention, it is possible to form a dense film of platinum, and to obtain a capacitive element free from peeling and deterioration of electrical characteristics.
【0009】[0009]
【発明の実施の形態】本発明の請求項1に記載の発明
は、支持基板上に形成された金属または金属酸化物より
なり密着層と、同密着層上に形成され、引っ張り応力が
2×109dyn/cm2以上である白金よりなる下部電
極と、同下部電極上に形成された金属酸化物よりなる容
量絶縁膜および同容量絶縁膜上に形成された上部電極と
を備えたものであり、これにより白金が緻密な膜質とな
るため、密着層を形成する金属成分が白金で形成された
下部電極へ拡散することを抑制する作用を有する。BEST MODE FOR CARRYING OUT THE INVENTION The invention according to claim 1 of the present invention is an adhesion layer made of a metal or a metal oxide formed on a supporting substrate, and formed on the adhesion layer with a tensile stress of 2 ×. A lower electrode made of platinum of 10 9 dyn / cm 2 or more, a capacitive insulating film made of a metal oxide formed on the lower electrode, and an upper electrode formed on the capacitive insulating film. Therefore, since platinum has a dense film quality, it has an effect of suppressing diffusion of a metal component forming the adhesion layer to the lower electrode formed of platinum.
【0010】請求項2に記載の発明は、支持基板上に金
属または金属酸化物よりなる密着層を形成する工程と、
前記密着層上に、アルゴンガスを用い、基板温度を20
0℃以上600℃以下に設定したスパッタリング法によ
り白金を形成して下部電極を形成する工程と、前記下部
電極上に金属酸化物よりなる容量絶縁膜を形成する工程
および前記容量絶縁膜上に上部電極を形成する工程とを
備えたものであり、これにより下部電極を形成する白金
の引っ張り応力を2×109dyn/cm2以上とするこ
とができ、白金を緻密な膜質とすることができる。この
結果密着層を形成する金属成分が白金で形成された下部
電極へ拡散することを抑制することができる。According to a second aspect of the present invention, a step of forming an adhesion layer made of a metal or a metal oxide on the supporting substrate,
Argon gas was used on the adhesion layer to increase the substrate temperature to 20.
A step of forming platinum by a sputtering method set to 0 ° C. or more and 600 ° C. or less to form a lower electrode; a step of forming a capacitive insulating film made of a metal oxide on the lower electrode; and an upper portion of the capacitive insulating film. And a step of forming an electrode, whereby the tensile stress of platinum forming the lower electrode can be set to 2 × 10 9 dyn / cm 2 or more, and platinum can be made into a dense film quality. . As a result, the metal component forming the adhesion layer can be suppressed from diffusing into the lower electrode formed of platinum.
【0011】請求項3に記載の発明は、請求項2記載の
スパッタリング法が平行平面型マグネトロン直流電界ス
パッタリング法であり、これにより白金をより緻密な膜
質とすることができる。According to a third aspect of the present invention, the sputtering method according to the second aspect is a parallel plane type magnetron DC electric field sputtering method, whereby platinum can be made into a more dense film quality.
【0012】以下、本発明の一実施の形態における容量
素子およびその製造方法を図1の工程断面図を用いて説
明する。A capacitive element and a method of manufacturing the same according to one embodiment of the present invention will be described below with reference to the process sectional views of FIGS.
【0013】(実施の形態1)図1(a)に示すよう
に、シリコン基板よりなる支持基板11上に層間絶縁膜
12となるシリコン酸化膜を形成する。次に、図1
(b)に示すように、層間絶縁膜12の上に密着層13
となる膜厚が約20nmの金属チタンを形成し、その上
に下部電極14となる膜厚が300nmの白金を、基板
温度を200℃〜600℃に設定し、アルゴンガスを用
いた平行平面型マグネトロン直流電界スパッタリング法
により形成する。次に図1(c)に示すように下部電極
14の上に容量絶縁膜15となる組成がSrBi2Ta2
O9である強誘電体膜をスピンオン法で塗布し800℃
で焼成する。次に図1(d)に示すようにこの上に上部
電極16となる白金をスパッタリング法により形成す
る。さらに図1(e)に示すように写真食刻法とドライ
エッチング法により加工を行い、容量素子を形成する。(First Embodiment) As shown in FIG. 1A, a silicon oxide film to be an interlayer insulating film 12 is formed on a supporting substrate 11 made of a silicon substrate. Next, FIG.
As shown in (b), the adhesion layer 13 is formed on the interlayer insulating film 12.
Forming a titanium metal film having a film thickness of about 20 nm, a platinum film having a film thickness of 300 nm to be the lower electrode 14, and setting the substrate temperature at 200 ° C. to 600 ° C. and using a parallel plane type using argon gas. It is formed by a magnetron DC electric field sputtering method. Next, as shown in FIG. 1C, the composition forming the capacitive insulating film 15 on the lower electrode 14 is SrBi 2 Ta 2
Apply a ferroelectric film of O 9 by spin-on method and 800 ℃
Baking. Next, as shown in FIG. 1 (d), platinum serving as the upper electrode 16 is formed thereon by a sputtering method. Further, as shown in FIG. 1E, processing is performed by a photo-etching method and a dry etching method to form a capacitive element.
【0014】ところで図1(b)の下部電極14を形成
する白金のスパッタリングでは、密着層13の金属チタ
ンの下部電極14への拡散を防ぐため緻密な膜質の白金
が要求される。図2〜図4に白金の成膜条件と白金の内
部応力との関係を示す。内部応力が引っ張り方向で大き
いほど緻密な膜となる。このことを以下に説明する。図
2は室温で、スパッタリング・パワー0.72kWの条
件での白金の内部応力のArガス圧依存性を示す図であ
る。図3は室温で、Arガス圧8mTorrの条件での
白金の内部応力のスパッタリング・パワー依存性を示す
図である。図4はスパッタリング・パワー0.72kW
でArガス圧が8mTorrの条件での白金の内部応力
の基板温度依存性を示す図である。図から分かるよう
に、白金の内部応力はArガス圧やスパッタリング・パ
ワーによってはあまり変化していない。これらに比べて
白金の内部応力は基板温度依存性が大きく、基板温度が
高いほど内部応力は引っ張り方向に強くなる。図5に、
容量素子形成後の下部電極14の白金と支持基板11上
に形成された層間絶縁膜12のシリコン酸化膜との密着
強度のArガス圧が8mTorr、スパッタリング・パ
ワー0.72kWの条件での基板温度依存性を示す。密
着強度は走査型スクラッチテスタにより膜がはがれた時
の臨界荷重として評価した。基板温度が高いほど臨界荷
重が大きくなる。このことから白金の引っ張り応力が大
きくなるほど、臨界荷重すなわち密着強度が大きくなる
ことがわかる。この結果、基板温度が高くなるほど、言
い換えれば白金の引っ張り応力が大きくなるほど、密着
層13を形成するチタンの拡散が抑制され、密着強度が
強くなることがわかる。以上の結果、白金の成膜条件は
基板温度を図5に示した臨界荷重がほぼ飽和する200
℃以上にして2×109dyn/cm2以上の引っ張り応
力を有する緻密な膜を形成することにより、チタン拡散
をほぼ抑制し、密着性の劣化をなくすことができる。By the way, in the sputtering of platinum for forming the lower electrode 14 of FIG. 1B, a dense film of platinum is required to prevent the diffusion of metallic titanium of the adhesion layer 13 into the lower electrode 14. 2 to 4 show the relationship between the platinum film forming conditions and the internal stress of platinum. The larger the internal stress in the tensile direction, the denser the film. This will be described below. FIG. 2 is a diagram showing the Ar gas pressure dependency of the internal stress of platinum under the conditions of room temperature and a sputtering power of 0.72 kW. FIG. 3 is a diagram showing the sputtering power dependence of the internal stress of platinum under the conditions of room temperature and Ar gas pressure of 8 mTorr. Fig. 4 shows sputtering power 0.72kW
FIG. 4 is a diagram showing the substrate temperature dependence of the internal stress of platinum under the condition of Ar gas pressure of 8 mTorr. As can be seen from the figure, the internal stress of platinum does not change much depending on the Ar gas pressure and the sputtering power. In comparison with these, the internal stress of platinum has a large dependence on the substrate temperature, and the higher the substrate temperature, the stronger the internal stress in the tensile direction. In FIG.
Substrate temperature under conditions of Ar gas pressure of 8 mTorr and sputtering power of 0.72 kW for adhesion strength between platinum of the lower electrode 14 after formation of the capacitive element and the silicon oxide film of the interlayer insulating film 12 formed on the supporting substrate 11. Show dependencies. The adhesion strength was evaluated as a critical load when the film was peeled off by a scanning scratch tester. The higher the substrate temperature, the larger the critical load. From this, it is understood that the greater the tensile stress of platinum, the greater the critical load, that is, the adhesion strength. As a result, it can be seen that as the substrate temperature increases, in other words, as the tensile stress of platinum increases, the diffusion of titanium forming the adhesion layer 13 is suppressed and the adhesion strength increases. As a result of the above, the platinum film forming conditions are such that the critical load shown in FIG.
By forming a dense film having a tensile stress of 2 × 10 9 dyn / cm 2 or more at a temperature of not less than 0 ° C., titanium diffusion can be substantially suppressed and deterioration of adhesion can be eliminated.
【0015】なお基板温度の上限を600℃としたの
は、600℃以上にすれば拡散が進みすぎることや金属
膜にヒルロックができやすくなるためである。The upper limit of the substrate temperature is set to 600 ° C. because if it is set to 600 ° C. or higher, the diffusion proceeds too much and the metal film is likely to have hillocks.
【0016】なお本実施の形態では支持基板として単な
るシリコン基板としたが、集積回路を作り込んだシリコ
ン基板でもよく、あるいは石英基板やGaAs基板など
でもよい。また本実施の形態では容量絶縁膜として、B
i系層状ペロブスカイト型構造を有する代表的な組成の
SrBi2Ta2O9を用いたがPb(Zr1-xTix)O3
や(Ba1-xSrx)TiO3などの他の強誘電体膜でも
よく、あるいはタンタル酸化物などの他の金属酸化物で
もよい。In this embodiment, a simple silicon substrate is used as the supporting substrate, but a silicon substrate having an integrated circuit built therein, a quartz substrate, a GaAs substrate or the like may be used. In addition, in this embodiment, as the capacitor insulating film, B
Although SrBi 2 Ta 2 O 9 having a typical composition having an i-based layered perovskite structure was used, Pb (Zr 1-x Ti x ) O 3 was used.
Other ferroelectric films such as or (Ba 1-x Sr x ) TiO 3 may be used, or other metal oxides such as tantalum oxide may be used.
【0017】また本実施の形態では容量絶縁膜をスピン
オン法で形成したが、スパッタリング法や化学気相成長
法で形成してもよい。Further, although the capacitor insulating film is formed by the spin-on method in the present embodiment, it may be formed by the sputtering method or the chemical vapor deposition method.
【0018】また本実施の形態では密着層に金属チタン
を用いたが、タンタルなどの他の金属やルテニウム酸化
物・イリジウム酸化物などの他の金属酸化物でもよい。In this embodiment, titanium metal is used for the adhesion layer, but other metals such as tantalum and other metal oxides such as ruthenium oxide and iridium oxide may be used.
【0019】[0019]
【発明の効果】本発明の容量素子は、下部電極を形成す
る白金が2×109dyn/cm2以上の引っ張り応力の
内部応力を有するものであり、その製造方法はこの白金
をスパッタリング法により200℃〜600℃の基板温
度で形成することを特徴とし、これにより緻密な膜質の
白金を形成することにより密着層の金属成分を下部電極
側への拡散を抑制し、密着層が薄くなることによるはが
れや密着層の金属成分が容量絶縁膜にまで拡散してきて
容量絶縁膜の電気的特性を劣化させることを防ぐことが
できる。In the capacitive element of the present invention, the platinum forming the lower electrode has an internal stress of tensile stress of 2 × 10 9 dyn / cm 2 or more. It is characterized in that it is formed at a substrate temperature of 200 ° C. to 600 ° C., thereby forming a dense film quality of platinum to suppress the diffusion of metal components of the adhesion layer to the lower electrode side, and the adhesion layer becomes thin. It is possible to prevent the peeling and the metal component of the adhesion layer from diffusing to the capacitive insulating film and deteriorating the electrical characteristics of the capacitive insulating film.
【図1】本発明の一実施の形態における容量素子および
その製造方法を示す工程断面図FIG. 1 is a process cross-sectional view showing a capacitive element and a manufacturing method thereof according to an embodiment of the present invention.
【図2】白金の内部応力のアルゴンガス圧依存性を示す
図FIG. 2 is a diagram showing the argon gas pressure dependence of internal stress of platinum.
【図3】白金の内部応力のスパッタリング・パワー依存
性を示す図FIG. 3 is a diagram showing the sputtering power dependence of the internal stress of platinum.
【図4】白金の内部応力の基板温度依存性を示す図FIG. 4 is a diagram showing substrate temperature dependence of internal stress of platinum.
【図5】白金下部電極と支持基板との密着性の基板温度
依存性を示す図FIG. 5 is a diagram showing the substrate temperature dependence of the adhesion between the platinum lower electrode and the supporting substrate.
【図6】従来例における容量素子の製造方法を示す工程
断面図FIG. 6 is a process cross-sectional view showing a method of manufacturing a capacitive element in a conventional example.
11 支持基板 12 層間絶縁膜 13 密着層 14 下部電極 15 容量絶縁膜 16 上部電極 11 Support Substrate 12 Interlayer Insulation Film 13 Adhesion Layer 14 Lower Electrode 15 Capacitance Insulation Film 16 Upper Electrode
Claims (3)
酸化物よりなり密着層と、同密着層上に形成され、引っ
張り応力が2×109dyn/cm2以上である白金より
なる下部電極と、同下部電極上に形成された金属酸化物
よりなる容量絶縁膜、および同容量絶縁膜上に形成され
た上部電極とを備えたことを特徴とする容量素子。1. An adhesion layer made of a metal or a metal oxide formed on a supporting substrate, and a lower electrode formed of platinum having a tensile stress of 2 × 10 9 dyn / cm 2 or more formed on the adhesion layer. And a capacitive insulating film made of a metal oxide formed on the lower electrode, and an upper electrode formed on the capacitive insulating film.
なる密着層を形成する工程と、前記密着層上に、アルゴ
ンガスを用い、基板温度を200℃以上600℃以下に
設定したスパッタリング法により白金を形成して下部電
極を形成する工程と、前記下部電極上に金属酸化物より
なる容量絶縁膜を形成する工程、および前記容量絶縁膜
上に上部電極を形成する工程とを備えたことを特徴とす
る容量素子の製造方法。2. A step of forming an adhesion layer made of a metal or a metal oxide on a supporting substrate, and a sputtering method in which argon gas is used on the adhesion layer and the substrate temperature is set to 200 ° C. or higher and 600 ° C. or lower. A step of forming platinum to form a lower electrode; a step of forming a capacitive insulating film made of a metal oxide on the lower electrode; and a step of forming an upper electrode on the capacitive insulating film. A method of manufacturing a characteristic capacitive element.
ロン直流電界スパッタリング法であることを特徴とする
請求項2記載の容量素子の製造方法。3. The method of manufacturing a capacitive element according to claim 2, wherein the sputtering method is a parallel plane magnetron DC electric field sputtering method.
Priority Applications (1)
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JP8055733A JPH09246082A (en) | 1996-03-13 | 1996-03-13 | Capacitance element and method of manufacturing |
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---|---|---|---|
JP8055733A JPH09246082A (en) | 1996-03-13 | 1996-03-13 | Capacitance element and method of manufacturing |
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JPH09246082A true JPH09246082A (en) | 1997-09-19 |
Family
ID=13007067
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2000013224A1 (en) * | 1998-08-31 | 2000-03-09 | Infineon Technologies Ag | Microelectronic structure, production method and utilization of the same |
US6960800B2 (en) | 1999-12-13 | 2005-11-01 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for fabricating the same |
US6974547B1 (en) | 1998-12-22 | 2005-12-13 | Matsushita Electric Industrial Co., Ltd. | Flexible thin film capacitor and method for producing the same |
-
1996
- 1996-03-13 JP JP8055733A patent/JPH09246082A/en active Pending
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2000013224A1 (en) * | 1998-08-31 | 2000-03-09 | Infineon Technologies Ag | Microelectronic structure, production method and utilization of the same |
JP2002524850A (en) * | 1998-08-31 | 2002-08-06 | インフィネオン テクノロジース アクチエンゲゼルシャフト | Microelectronic structure, method of manufacture thereof and its use in memory cells |
US6670668B2 (en) | 1998-08-31 | 2003-12-30 | Infineon Technologies Ag | Microelectronic structure, method for fabricating it and its use in a memory cell |
KR100499429B1 (en) * | 1998-08-31 | 2005-07-07 | 인피니언 테크놀로지스 아게 | Microelectronic structure, production method and utilization of the same |
US6974547B1 (en) | 1998-12-22 | 2005-12-13 | Matsushita Electric Industrial Co., Ltd. | Flexible thin film capacitor and method for producing the same |
US6960800B2 (en) | 1999-12-13 | 2005-11-01 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for fabricating the same |
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