JPH04349657A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH04349657A JPH04349657A JP3121521A JP12152191A JPH04349657A JP H04349657 A JPH04349657 A JP H04349657A JP 3121521 A JP3121521 A JP 3121521A JP 12152191 A JP12152191 A JP 12152191A JP H04349657 A JPH04349657 A JP H04349657A
- Authority
- JP
- Japan
- Prior art keywords
- capacitor
- palladium
- film
- electrode
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 11
- 239000003990 capacitor Substances 0.000 claims abstract description 60
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims abstract description 24
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims abstract description 24
- 229910052763 palladium Inorganic materials 0.000 claims abstract description 11
- 229910001252 Pd alloy Inorganic materials 0.000 claims abstract description 7
- 229910001260 Pt alloy Inorganic materials 0.000 claims abstract description 7
- 229910052697 platinum Inorganic materials 0.000 claims abstract description 5
- 229910045601 alloy Inorganic materials 0.000 claims abstract 2
- 239000000956 alloy Substances 0.000 claims abstract 2
- 229910052751 metal Inorganic materials 0.000 claims description 15
- 239000002184 metal Substances 0.000 claims description 15
- 239000007772 electrode material Substances 0.000 claims description 11
- 150000004767 nitrides Chemical class 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 14
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 14
- 230000015572 biosynthetic process Effects 0.000 abstract description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052710 silicon Inorganic materials 0.000 abstract description 6
- 239000010703 silicon Substances 0.000 abstract description 6
- 239000000758 substrate Substances 0.000 abstract description 6
- 238000000034 method Methods 0.000 abstract description 5
- 239000000463 material Substances 0.000 abstract description 4
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 abstract description 4
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 abstract description 4
- 238000009825 accumulation Methods 0.000 abstract 3
- 239000010410 layer Substances 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229910002113 barium titanate Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- 230000015654 memory Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は、ＤＲＡＭ又は不揮発性
メモリ等に用いるキャパシタ電極に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to capacitor electrodes used in DRAMs, nonvolatile memories, and the like.
【０００２】0002
【従来の技術】従来から、強誘電体膜又は高誘電体膜は
、その高い誘電率や残留分極値をもつため、高集積ＬＳ
Ｉメモリの誘電体として、検討されている。高誘電体膜
又は強誘電体膜をキャパシタ絶縁膜として用いるキャパ
シタの電極材料としては、従来Ｓｉ系（多結晶シリコン
又は金属シリサイド等）が用いられてきた。[Prior Art] Conventionally, ferroelectric films or high dielectric films have been used in highly integrated LS due to their high dielectric constants and residual polarization values.
It is being considered as a dielectric material for I-memory. Conventionally, Si-based materials (polycrystalline silicon, metal silicide, etc.) have been used as electrode materials for capacitors that use a high dielectric film or a ferroelectric film as a capacitor insulating film.
【０００３】0003
【発明が解決しようとする課題】図３に従来技術による
一実施例の断面図を示す。１はシリコン基板、２は下部
電極、３は強誘電体キャパシタ絶縁膜、４は上部電極。
９はシリコン酸化膜を示す。また図４（ａ）は、図３の
キャパシタ部の等価回路を示し、同（ｂ）は、電極と絶
縁膜との間にシリコン酸化膜が生じない場合のキャパシ
タ部の等価回路を示す。Ｃ１，Ｃ２はシリコン酸化膜９
における容量を示し、Ｃ，Ｃ０は強誘電体膜３における
容量を示す。強誘電体膜としてＰＺＴ膜を用いた場合、
高温，酸素雰囲気中でＰＺＴ膜を堆積するため、キャパ
シタ電極２，４に多結晶シリコンを用いた場合、キャパ
シタ電極２は、熱酸化され、またキャパシタ電極４は酸
化物であるキャパシタ絶縁膜と接しているため、界面が
酸化され、キャパシタ電極２，４とキャパシタ絶縁膜と
の界面にシリコン酸化膜９が形成される。また、キャパ
シタ電極にＰｔ等の金属を用いた場合、Ｐｔ等の金属は
シリサイド化され、キャパシタ絶縁膜３とキャパシタ電
極２，４との界面にシリコン酸化膜９が形成される。上
記の様に、シリコン酸化膜９が形成されると、図４（ｂ
）に示される等価回路から同（ａ）に示される等価回路
に変化し、キャパシタ全体としての誘電率は低下するこ
とになる。FIG. 3 shows a sectional view of an embodiment according to the prior art. 1 is a silicon substrate, 2 is a lower electrode, 3 is a ferroelectric capacitor insulating film, and 4 is an upper electrode. 9 indicates a silicon oxide film. 4(a) shows an equivalent circuit of the capacitor section in FIG. 3, and FIG. 4(b) shows an equivalent circuit of the capacitor section when no silicon oxide film is formed between the electrode and the insulating film. C1 and C2 are silicon oxide films 9
C and C0 indicate the capacitance in the ferroelectric film 3. When a PZT film is used as the ferroelectric film,
Since the PZT film is deposited at high temperature in an oxygen atmosphere, if polycrystalline silicon is used for the capacitor electrodes 2 and 4, the capacitor electrode 2 will be thermally oxidized, and the capacitor electrode 4 will be in contact with the capacitor insulating film, which is an oxide. Therefore, the interface is oxidized and a silicon oxide film 9 is formed at the interface between the capacitor electrodes 2 and 4 and the capacitor insulating film. Further, when a metal such as Pt is used for the capacitor electrode, the metal such as Pt is silicided, and a silicon oxide film 9 is formed at the interface between the capacitor insulating film 3 and the capacitor electrodes 2 and 4. When the silicon oxide film 9 is formed as described above, FIG.
) changes to the equivalent circuit shown in (a), and the dielectric constant of the capacitor as a whole decreases.
【０００４】本発明は、キャパシタ電極とキャパシタ絶
縁膜との界面におけるシリコン酸化膜の形成を抑制し、
高誘電率を有するキャパシタを提供することを目的とす
る。The present invention suppresses the formation of a silicon oxide film at the interface between a capacitor electrode and a capacitor insulating film,
An object of the present invention is to provide a capacitor having a high dielectric constant.
【０００５】[0005]
【課題を解決するための手段】請求項１記載の本発明は
、キャパシタ電極にパラジウム又はパラジウムと白金と
の合金を用いたキャパシタを設けたことを特徴とする。The present invention as set forth in claim 1 is characterized in that a capacitor is provided in which the capacitor electrode is made of palladium or an alloy of palladium and platinum.
【０００６】また、請求項２記載の本発明は、キャパシ
タ電極に導電性酸化物を用いたキャパシタを設けたこと
を特徴とする。[0006] Furthermore, the present invention as set forth in claim 2 is characterized in that a capacitor using a conductive oxide is provided for the capacitor electrode.
【０００７】さらに、請求項３記載の本発明は、キャパ
シタ電極が、キャパシタ絶縁膜に接する側から、白金又
はパラジウム又は白金とパラジウムとの合金、及びＶＩ
ａ族金属の窒化物、及びＶＩａ族金属の順に三層構造と
なるキャパシタを設けたことを特徴とする。Furthermore, the present invention according to claim 3 provides that the capacitor electrode is made of platinum, palladium, or an alloy of platinum and palladium, and VI
The present invention is characterized by providing a capacitor having a three-layer structure consisting of a nitride of a group a metal and a group VIa metal in this order.
【０００８】[0008]
【作用】上記請求項１記載の本発明を用いることによっ
て、電極材料に酸化されにくい金属を用いることで、電
極とキャパシタ絶縁膜との界面にシリコン酸化膜の発生
を抑制できる。By using the present invention as set forth in claim 1 above, by using a metal that is difficult to oxidize as the electrode material, it is possible to suppress the formation of a silicon oxide film at the interface between the electrode and the capacitor insulating film.
【０００９】また、上記請求項２記載の本発明を用いる
ことにより、電極材料に導電性酸化物を用いるので電極
とキャパシタ絶縁膜との界面におけるシリコン酸化膜の
発生を抑制できる。Further, by using the present invention as set forth in claim 2 above, since a conductive oxide is used as the electrode material, it is possible to suppress the formation of a silicon oxide film at the interface between the electrode and the capacitor insulating film.
【００１０】さらに、上記請求項３記載の本発明を用い
ることにより、電極材料のシリサイド化を防止し、電極
とキャパシタ絶縁膜との界面にシリコン酸化膜の発生を
抑制する。Furthermore, by using the present invention as set forth in claim 3 above, silicidation of the electrode material is prevented, and generation of a silicon oxide film at the interface between the electrode and the capacitor insulating film is suppressed.
【００１１】[0011]
【実施例】以下、実施例に基づいて本発明について詳細
に説明する。EXAMPLES The present invention will be explained in detail below based on examples.
【００１２】図１は、請求項１記載及び請求項２記載の
本発明の一実施例の製造工程を示し、図２は請求項３記
載の本発明の一実施例の製造工程を示す。FIG. 1 shows a manufacturing process of an embodiment of the present invention as set forth in claims 1 and 2, and FIG. 2 shows a manufacturing process of an embodiment of the invention as set forth in claim 3.
【００１３】１はシリコン基板、２は下部電極、３はキ
ャパシタ絶縁膜、４は上部電極、５，８はＶＩａ族金属
膜、６，７はＶＩａ族金属の窒化膜を示す。キャパシタ
絶縁膜３には、Ｔａ２Ｏ５膜，ＢａＴｉＯ３膜、ＳｒＴ
ｉＯ３膜又はＰＺＴ膜等を用いる。1 is a silicon substrate, 2 is a lower electrode, 3 is a capacitor insulating film, 4 is an upper electrode, 5 and 8 are VIa group metal films, and 6 and 7 are VIa group metal nitride films. The capacitor insulating film 3 includes Ta2O5 film, BaTiO3 film, SrT
An iO3 film, a PZT film, or the like is used.
【００１４】次に、請求項１記載及び請求項２記載の本
発明の一実施例の製造工程について説明する。Next, a manufacturing process of an embodiment of the present invention according to claims 1 and 2 will be explained.
【００１５】まずシリコン基板１上にスパッタ法を用い
て、下部電極２を１０００Å堆積する。該電極材料とし
て、パラジウム、又はパラジウムと白金との合金、又は
導電性酸化物を用いる。さらに、導電性酸化膜として、
ＩｎＯ３，ＳｎＯ２，ＲｕＯ２を用いる。上記材料をタ
ーゲットとして、酸素雰囲気中でスパッタリングを行う
（図１（ａ））。次に、スパッタ法を用いてキャパシタ
絶縁膜３として強誘電体膜（ＰＺＴ膜等）を１０００〜
３０００Å堆積する（図１（ｂ））。その後、上部電極
４を下部電極２形成工程と同一工程で１０００Å堆積す
る（図１（ｃ））。 次に、請求項３記載の本発明の
一実施例の製造工程について説明する。First, a lower electrode 2 having a thickness of 1000 Å is deposited on a silicon substrate 1 by sputtering. As the electrode material, palladium, an alloy of palladium and platinum, or a conductive oxide is used. Furthermore, as a conductive oxide film,
InO3, SnO2, and RuO2 are used. Sputtering is performed in an oxygen atmosphere using the above material as a target (FIG. 1(a)). Next, using a sputtering method, a ferroelectric film (such as a PZT film) with a thickness of 1,000 to
A thickness of 3000 Å is deposited (FIG. 1(b)). Thereafter, the upper electrode 4 is deposited to a thickness of 1000 Å in the same step as the step of forming the lower electrode 2 (FIG. 1(c)). Next, a manufacturing process of an embodiment of the present invention as defined in claim 3 will be explained.
【００１６】シリコン基板１上に拡散バリア層として、
Ｔｉ層５を５００Å，ＴｉＮ層６を５００Å形成する（
図２（ａ））。その後、下部電極２を１０００Å堆積す
る（図２（ｂ））。電極材料として、酸化されにくいパ
ラジウム、又は白金、又はパラジウムと白金の合金を用
いる。次にキャパシタ絶縁膜３として、ＰＺＴ膜等を１
０００〜３０００Å堆積する（図２（ｃ））。次に、上
部電極４を前記下部電極２形成工程と同一工程により１
０００Å形成した後（図２（ｄ）），ＴｉＮ層７及びＴ
ｉ層８をそれぞれ５００Å堆積する（図２（ｅ））。
上記堆積は、すべてスパッタ法により実施可能であり、
また、ＴｉのかわりにＶＩａ族金属のＺｒ，Ｈｆを用い
ても実施可能である。As a diffusion barrier layer on the silicon substrate 1,
A Ti layer 5 of 500 Å and a TiN layer 6 of 500 Å are formed (
Figure 2(a)). Thereafter, the lower electrode 2 is deposited to a thickness of 1000 Å (FIG. 2(b)). Palladium, platinum, or an alloy of palladium and platinum, which is not easily oxidized, is used as the electrode material. Next, as the capacitor insulating film 3, a PZT film etc.
000 to 3000 Å (FIG. 2(c)). Next, the upper electrode 4 is formed into a single layer by the same process as the lower electrode 2 formation process.
000 Å (Fig. 2(d)), the TiN layer 7 and the T
Each i-layer 8 is deposited to a thickness of 500 Å (FIG. 2(e)). All of the above depositions can be performed by sputtering,
It is also possible to use Zr or Hf, which are group VIa metals, instead of Ti.
【００１７】[0017]
【発明の効果】以上、詳細に説明した様に、請求項１及
び２記載の本発明を用いることにより、電極材料がキャ
パシタ絶縁膜形成時に酸化されにくく、そのため、電極
とキャパシタ電極との間にシリコン酸化膜が発生するこ
とを抑制でき、高誘電率を有するキャパシタを設けた半
導体装置が得られる。As described above in detail, by using the present invention according to claims 1 and 2, the electrode material is difficult to be oxidized during the formation of the capacitor insulating film, and therefore there is a gap between the electrode and the capacitor electrode. A semiconductor device can be obtained in which generation of a silicon oxide film can be suppressed and a capacitor having a high dielectric constant is provided.
【００１８】また、請求項３記載の本発明を用いること
により、電極材料に金属を用いた場合の金属のシリサイ
ド化を防止することができ、これにより、電極とキャパ
シタ電極との間にシリコン酸化膜が発生することを抑制
でき、高誘電率を有するキャパシタを設けた半導体装置
が得られる。Furthermore, by using the present invention as set forth in claim 3, it is possible to prevent metal from becoming silicided when metal is used as an electrode material, thereby preventing silicon oxide from forming between the electrode and the capacitor electrode. A semiconductor device can be obtained in which the formation of a film can be suppressed and a capacitor having a high dielectric constant is provided.
【図１】請求項１及び請求項２記載の本発明の一実施例
の製造工程図である。FIG. 1 is a manufacturing process diagram of an embodiment of the present invention according to claims 1 and 2.
【図２】請求項３記載の本発明の一実施例の製造工程図
である。FIG. 2 is a manufacturing process diagram of an embodiment of the present invention according to claim 3.
【図３】従来技術によるキャパシタ部の断面図である。FIG. 3 is a cross-sectional view of a capacitor section according to the prior art.
【図４】（ａ）は従来技術を用いた場合のキャパシタ部
の等価回路図であり、（ｂ）は本発明を用いた場合の同
等価回路図である。FIG. 4(a) is an equivalent circuit diagram of a capacitor section when a conventional technique is used, and FIG. 4(b) is an equivalent circuit diagram when the present invention is used.
１ シリコン基板 ２ 下部電極 ３ キャパシタ電極 ４ 上部電極 ５，８ ＶＩａ族金属膜 ６，７ ＶＩａ族金属の窒化膜 ９ シリコン酸化膜 1 Silicon substrate 2 Lower electrode 3 Capacitor electrode 4 Upper electrode 5, 8 Group VIa metal film 6,7 Group VIa metal nitride film 9 Silicon oxide film
Claims (3)
又は高誘電体膜を用いたキャパシタを設けた半導体装置
に於いて、キャパシタ電極材料にパラジウム又はパラジ
ウムと白金との合金を用いたキャパシタを設けたことを
特徴とする半導体装置。Claim 1: In a semiconductor device provided with a capacitor using a ferroelectric film or a high dielectric film as a capacitor insulating film, a capacitor using palladium or an alloy of palladium and platinum as a capacitor electrode material is provided. A semiconductor device characterized by:
又は高誘電体膜を用いたキャパシタを設けた半導体装置
に於いて、キャパシタ電極材料に導電性酸化物を用いた
キャパシタを設けたことを特徴とする半導体装置。2. A semiconductor device provided with a capacitor using a ferroelectric film or a high dielectric film as a capacitor insulating film, characterized in that a capacitor using a conductive oxide as a capacitor electrode material is provided. semiconductor device.
又は高誘電体膜を用いたキャパシタを設けた半導体装置
に於いて、キャパシタ電極材料が、キャパシタ絶縁膜に
接する側から、白金又はパラジウム又は白金とパラジウ
ムとの合金、及びＶＩａ族金属の窒化物、及びＶＩａ族
金属の順に三層構造とするキャパシタを設けたことを特
徴とする半導体装置。3. In a semiconductor device provided with a capacitor using a ferroelectric film or a high dielectric film as a capacitor insulating film, the capacitor electrode material is platinum, palladium, or platinum from the side in contact with the capacitor insulating film. 1. A semiconductor device comprising a capacitor having a three-layer structure in the order of an alloy of and palladium, a nitride of a group VIa metal, and a group VIa metal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3121521A JP2690821B2 (en) | 1991-05-28 | 1991-05-28 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3121521A JP2690821B2 (en) | 1991-05-28 | 1991-05-28 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04349657A true JPH04349657A (en) | 1992-12-04 |
| JP2690821B2 JP2690821B2 (en) | 1997-12-17 |
Family
ID=14813285
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3121521A Expired - Fee Related JP2690821B2 (en) | 1991-05-28 | 1991-05-28 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2690821B2 (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0766300A (en) * | 1993-08-09 | 1995-03-10 | Internatl Business Mach Corp <Ibm> | Capacitor and its manufacture |
| JPH0864786A (en) * | 1994-08-01 | 1996-03-08 | Texas Instr Inc <Ti> | Microelectronic structure and manufacture thereof |
| JPH08191137A (en) * | 1994-08-01 | 1996-07-23 | Texas Instr Inc <Ti> | Microelectronic structure body and its production |
| JPH09199687A (en) * | 1995-11-30 | 1997-07-31 | Hyundai Electron Ind Co Ltd | Capacitor for semiconductor element and manufacture of the same |
| EP0800187A3 (en) * | 1992-04-20 | 2005-09-14 | Texas Instruments Incorporated | Electrodes for high dielectric constant materials |
| JP2007184623A (en) * | 2007-01-22 | 2007-07-19 | Rohm Co Ltd | Dielectric capacitor |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0387056A (en) * | 1989-08-30 | 1991-04-11 | Nec Corp | Thin film capacitor and manufacture thereof |
| JPH03101260A (en) * | 1989-09-14 | 1991-04-26 | Nec Corp | Thin film capacitor |
-
1991
- 1991-05-28 JP JP3121521A patent/JP2690821B2/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0387056A (en) * | 1989-08-30 | 1991-04-11 | Nec Corp | Thin film capacitor and manufacture thereof |
| JPH03101260A (en) * | 1989-09-14 | 1991-04-26 | Nec Corp | Thin film capacitor |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0800187A3 (en) * | 1992-04-20 | 2005-09-14 | Texas Instruments Incorporated | Electrodes for high dielectric constant materials |
| JPH0766300A (en) * | 1993-08-09 | 1995-03-10 | Internatl Business Mach Corp <Ibm> | Capacitor and its manufacture |
| JPH0864786A (en) * | 1994-08-01 | 1996-03-08 | Texas Instr Inc <Ti> | Microelectronic structure and manufacture thereof |
| JPH08191137A (en) * | 1994-08-01 | 1996-07-23 | Texas Instr Inc <Ti> | Microelectronic structure body and its production |
| JPH09199687A (en) * | 1995-11-30 | 1997-07-31 | Hyundai Electron Ind Co Ltd | Capacitor for semiconductor element and manufacture of the same |
| JP2007184623A (en) * | 2007-01-22 | 2007-07-19 | Rohm Co Ltd | Dielectric capacitor |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2690821B2 (en) | 1997-12-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5489548A (en) | Method of forming high-dielectric-constant material electrodes comprising sidewall spacers | |
| EP0697718B1 (en) | Method of making electrical connections to materials with high dielectric constant | |
| US5581436A (en) | High-dielectric-constant material electrodes comprising thin platinum layers | |
| US5191510A (en) | Use of palladium as an adhesion layer and as an electrode in ferroelectric memory devices | |
| US5612574A (en) | Semiconductor structures using high-dielectric-constant materials and an adhesion layer | |
| US5929475A (en) | Capacitor for integrated circuit and its fabrication method | |
| KR0147655B1 (en) | Manufacturing method for capacitor of semiconductor device | |
| JP2002076293A (en) | Method for manufacturing capacitor and semiconductor device | |
| JPH04349657A (en) | Semiconductor device | |
| US6303952B1 (en) | Contact structure with an oxide silicidation barrier | |
| JP4392336B2 (en) | Method for manufacturing ferroelectric capacitor | |
| JPH0687491B2 (en) | Thin film capacitors | |
| JPH0992795A (en) | Capacitance element and manufacture thereof and semiconductor device | |
| JP2002203948A (en) | Semiconductor device | |
| EP0490288A2 (en) | Process for fabricating PZT capacitors as integrated circuit memory elements and a capacitor storage element | |
| JPH03253065A (en) | Thin-film capacitor and its manufacture | |
| JP3120568B2 (en) | Thin film capacitors | |
| US6238932B1 (en) | Method for fabricating reliable multilayer bottom electrode for ferroelectric capacitors | |
| JP3170254B2 (en) | Capacitor | |
| KR100207447B1 (en) | Capacitor and its fabrication method | |
| JPH09129849A (en) | Capacitor of semiconductor element and its preparation | |
| KR100277939B1 (en) | bottom electrode of capacitor with ferroelectric | |
| JP5030349B2 (en) | Dielectric film fabrication method | |
| JP3248475B2 (en) | Method of manufacturing ferroelectric nonvolatile memory cell structure | |
| JP2001267529A (en) | Semiconductor device and method of manufacturing the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20070829 Year of fee payment: 10 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080829 Year of fee payment: 11 |
|
| LAPS | Cancellation because of no payment of annual fees |