JPS6284541A - Lead frame for semiconductor device - Google Patents

Lead frame for semiconductor device

Info

Publication number
JPS6284541A
JPS6284541A JP22533485A JP22533485A JPS6284541A JP S6284541 A JPS6284541 A JP S6284541A JP 22533485 A JP22533485 A JP 22533485A JP 22533485 A JP22533485 A JP 22533485A JP S6284541 A JPS6284541 A JP S6284541A
Authority
JP
Japan
Prior art keywords
lead frame
lead
semiconductor element
semiconductor device
tab
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22533485A
Other languages
Japanese (ja)
Inventor
Seisaku Yamanaka
山中 正策
Tadashi Igarashi
五十嵐 廉
Hirohiko Ihara
井原 寛彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to JP22533485A priority Critical patent/JPS6284541A/en
Publication of JPS6284541A publication Critical patent/JPS6284541A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To obtain a lead frame for a semiconductor device having a heat- dissipating effect and little thermal stress to a semiconductor element by each using specific materials for a lead member and a tab. CONSTITUTION:In a semiconductor device manufactured by employing the lead frame, a large-sized semiconductor element 7 is fixed onto a tab 6 formed by a low thermal expansion material such as a 42 alloy (Fe-42% Ni) through a precious metal layer 8. Leads 9 are shaped by a copper group material having excellent heat-dissipating properties, and the noses of the leads 9 are bonded by wires 5 through precious metal layers 8. Heat generated on operation is transmitted over the lead members having superior heat-dissipating properties through the wires 5 and discharged to the outside in the semiconductor device constituted in this manner. Differential thermal expansion between the semiconductor element 7 and the tab is reduced, thus also preventing the generation of cracks in the semiconductor element.

Description

【発明の詳細な説明】 (イ)産業上の利用分野 この発明は半導体装置用リードフレーム、特に温度変化
に対応が可能なリードフレームに関するものである。
DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application This invention relates to a lead frame for a semiconductor device, and particularly to a lead frame that can cope with temperature changes.

(ロ)従来技術 従来、半導体装置においては、第2回に示すようなリー
ドフレームが使用されている。このリードフレームはフ
レーム1の中央部に半導体素子2を貴金属18を介して
載せるためのタブ3を設け、タブ3に向けて多数のリー
ド4を設けたものであり、リード4先端に設けられた貴
金属層8を介してリード4の先端と半導体素子間にワイ
ヤ5によりボンディングが施され、電気的な接続が行わ
れる。
(B) Prior Art Conventionally, lead frames as shown in Part 2 have been used in semiconductor devices. This lead frame has a tab 3 in the center of a frame 1 for mounting a semiconductor element 2 via a precious metal 18, and a large number of leads 4 facing the tab 3. Bonding is performed by the wire 5 between the tip of the lead 4 and the semiconductor element via the noble metal layer 8 to establish an electrical connection.

リード4は半導体素子ともに樹脂モールドされるインナ
ーリード部4aと、樹脂モールド外において背面側へ屈
曲されプリント基板等に装着されるアウターリード部4
bとから成る。
The lead 4 includes an inner lead part 4a in which the semiconductor element is molded with resin, and an outer lead part 4 which is bent toward the back side outside the resin mold and attached to a printed circuit board or the like.
It consists of b.

上記構造のリードフレームは、量産性に優れ、外部との
接続の信軌性が高いことから、近年ますます使用されて
いる。
The lead frame having the above structure has been increasingly used in recent years because it is excellent in mass production and has high reliability in connection with the outside.

リードフレーム材質としては、42合金 (Fe−42
χNi)に代表される鉄系材料および銅系材料が用いら
れている。半導体素子が大面積で、動作時の温度上昇に
よりクランク発生の可能性がある場合は、半導体素子と
熱膨張係数の近い鉄系材料が用いられているが、銅系材
料に比べ、熱伝導率が低いことから、パンケージとして
の放熱性に劣り、材料コストも高い。一方、銅系材料は
、低コスト性と良好な熱放散性から最近ますます多用化
されているがSiチップの如き半導体素子との熱膨張差
が大きく上記の大型半導体装置には通用されにくいのが
現状である。
The lead frame material is 42 alloy (Fe-42
Iron-based materials and copper-based materials, such as χNi), are used. If the semiconductor element has a large area and there is a possibility of cranking due to temperature rise during operation, iron-based materials are used that have a coefficient of thermal expansion similar to that of the semiconductor element, but they have lower thermal conductivity than copper-based materials. Because of its low heat dissipation properties as a pan cage, the material cost is also high. On the other hand, copper-based materials have recently been increasingly used due to their low cost and good heat dissipation properties, but the large difference in thermal expansion between them and semiconductor elements such as Si chips makes them difficult to use in large-scale semiconductor devices. is the current situation.

(ハ)発明が解決しようとする問題点 近年の高密度実装化動向の中で、半導体素子のパワー上
昇に対処する為のパンケージの放熱構造が問題となって
いる。気密封止形パッケージでは、放熱フィンや放熱ス
タンドを設けて放熱効果を高める工夫がなされている。
(c) Problems to be Solved by the Invention With the recent trend toward high-density packaging, the heat dissipation structure of the pancage to cope with the increase in the power of semiconductor devices has become a problem. Hermetically sealed packages are equipped with heat dissipation fins and heat dissipation stands to increase the heat dissipation effect.

−力木発明のリードフレームが対象としている樹脂封止
型パッケージでは、従来は銅系材料のリードフレームを
用いて対応している。しかしながら、銅系材料の上に半
導体素子を銀ペースト等で固着した場合、パワー発生時
半導体素子と銅系材料の熱膨張係数の大きな違いにより
、半導体素子に大きなストレスがかかり、クラックが生
じやすくなり、大型半導体装置には適用出来ないのが現
状である。
-Resin-sealed packages to which the lead frame of Rikiki's invention is intended have conventionally been handled using lead frames made of copper-based materials. However, when a semiconductor element is fixed on a copper-based material using silver paste, etc., the large difference in thermal expansion coefficient between the semiconductor element and the copper-based material during power generation places a large stress on the semiconductor element, making it more likely to crack. Currently, this method cannot be applied to large-sized semiconductor devices.

これらはいずれもリードフレームを同一材料で作ること
を前提としている。この発明は樹脂封止型パンケージに
用いられるリードフレームの上記欠点に鑑み、前記の前
提条件にとられれず放熱効果があり、しかも半導体素子
との熱ストレスが少ないリードフレームを提供すること
を目的とするものである。
All of these assume that the lead frame is made of the same material. In view of the above-mentioned drawbacks of lead frames used in resin-sealed pancages, it is an object of the present invention to provide a lead frame that does not meet the above-mentioned prerequisites, has a heat dissipation effect, and has less thermal stress with semiconductor elements. It is something to do.

(ニ)問題点を解決する為の手段 上記の目的を達成する為に、この発明はSiチップの如
き半導体素子と熱膨張係数が近い材料でタブを形成し、
リード部材は、熱放散性に秀れた材料で形成したリード
フレーム即ち、複数のリード部材とタブからなるリード
フレームにおいて、リード部材は、熱膨張係数の小さい
材料で形成され、タブは熱放散性のよい材料で形成され
ている半導体装置用リードフレームを提供するものであ
る。
(d) Means for solving the problem In order to achieve the above object, the present invention forms a tab with a material having a coefficient of thermal expansion close to that of a semiconductor element such as a Si chip,
The lead members are made of a material with excellent heat dissipation properties.In other words, in a lead frame consisting of a plurality of lead members and tabs, the lead members are made of a material with a small coefficient of thermal expansion, and the tabs are made of a material with excellent heat dissipation properties. The present invention provides a lead frame for a semiconductor device made of a material with good quality.

このリードフレームを用いることにより、従来樹脂封止
型パフケージでは不可能であった大型半導体装置への適
用が可能となる。
By using this lead frame, it becomes possible to apply it to large-sized semiconductor devices, which was impossible with conventional resin-sealed puff cages.

(ホ)実施例 第1図は、この発明のリードフレームを使用して製作し
た半導体装置の一例である。42合金(Fe−42χN
i )等の低熱膨張材料で形成されたダブ6上に大型半
導体素子7を貴金属層8を介して固着している。一方、
リード9は熱放散性に秀れた銅系材料で形成しており、
リード9の先端は、貴金属層8を介してワイヤー5によ
りボンディングを施している。このように構成される半
導体装置では動作時発生する熱は、ワイヤー5を介して
熱放散性の秀れたリード部材に伝熱し外部に放出される
(e) Example FIG. 1 shows an example of a semiconductor device manufactured using the lead frame of the present invention. 42 alloy (Fe-42χN
A large semiconductor element 7 is fixed on a dove 6 made of a low thermal expansion material such as i) via a noble metal layer 8. on the other hand,
The lead 9 is made of a copper-based material with excellent heat dissipation properties.
The tips of the leads 9 are bonded to the wires 5 through the noble metal layer 8. In the semiconductor device configured as described above, heat generated during operation is transferred to the lead member having excellent heat dissipation properties through the wire 5 and is emitted to the outside.

また半導体素子7とタブの熱膨張差が少ないことにより
半導体素子のクラック発生も防止される。
Moreover, since the difference in thermal expansion between the semiconductor element 7 and the tab is small, cracks in the semiconductor element are also prevented.

上記のようなリードフレームは、次のような手順で製作
することが出来る。すなわちタブを除いた形状のリード
フレームをフォトエツチングまたはスタンピングにより
製作し、別途製作したタブをスポット溶接またはハンダ
付により貼合せる。その後、タブ表面およびリード先端
部に貴金属めっきを部分的に施せばよい。
The lead frame as described above can be manufactured by the following procedure. That is, a lead frame without the tab is produced by photo-etching or stamping, and a separately produced tab is attached by spot welding or soldering. Thereafter, noble metal plating may be applied partially to the tab surface and the lead tip.

42合金(Fe−42χNi )、コバール(F e 
−2−9χN+−17XCo )等の鉄系材料を、又、
熱放散性のよい材料としては熱伝導度が0.1 g−c
al/am ・see ・”C以上の材料、たとえば錫
入り銅合金(Cu−0,1〜8χSn)、鉄入り鋼合金
(Cl−0,1〜3χFe )等の銅系材料を用いるこ
とが好ましい。
42 alloy (Fe-42χNi), Kovar (Fe
-2-9χN+-17XCo) and other iron-based materials,
A material with good heat dissipation properties has a thermal conductivity of 0.1 g-c.
al/am ・see ・It is preferable to use a material of C or higher, for example, a copper-based material such as a tin-containing copper alloy (Cu-0,1 to 8χSn), an iron-containing steel alloy (Cl-0,1 to 3χFe), etc. .

【図面の簡単な説明】 第1図は、この発明のリードフレームを用いて製作した
半導体装置の断面図。 第2図は、従来のリードフレームを用いた半導体装置の
断面図。 1・・・リードフレーム 2・・・半導体素子 3・・・タ ブ 4・・・リード 4a・・・インナーリード部 4b・・・アウターリード部 5・・・ワイヤ 6・・・タブ(低熱膨張素材) 7・・・大型半導体素子 8・・・貴金属層 9・・・リード(高放熱素材) 第1図 、:5   δ
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a sectional view of a semiconductor device manufactured using the lead frame of the present invention. FIG. 2 is a cross-sectional view of a semiconductor device using a conventional lead frame. 1...Lead frame 2...Semiconductor element 3...Tab 4...Lead 4a...Inner lead part 4b...Outer lead part 5...Wire 6...Tab (low thermal expansion Material) 7...Large semiconductor element 8...Precious metal layer 9...Lead (high heat dissipation material) Figure 1: 5 δ

Claims (3)

【特許請求の範囲】[Claims] (1)複数のリード部材とタブからなるリードフレーム
において、リード部材は熱膨張係数の小さい材料で形成
され、タブは熱放散性のよい材料で形成されていること
を特徴とする半導体装置用リードフレーム。
(1) A lead frame for a semiconductor device comprising a plurality of lead members and tabs, wherein the lead members are made of a material with a small coefficient of thermal expansion, and the tabs are made of a material with good heat dissipation. flame.
(2)リード部材が銅系材料で形成されていることを特
徴とする特許請求の範囲第1項記載の半導体装置用リー
ドフレーム。
(2) The lead frame for a semiconductor device according to claim 1, wherein the lead member is made of a copper-based material.
(3)タブが鉄系材料で形成されていることを特徴とす
る特許請求の範囲第1項又は第2項記載の半導体装置用
リードフレーム。
(3) A lead frame for a semiconductor device according to claim 1 or 2, wherein the tab is made of an iron-based material.
JP22533485A 1985-10-08 1985-10-08 Lead frame for semiconductor device Pending JPS6284541A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22533485A JPS6284541A (en) 1985-10-08 1985-10-08 Lead frame for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22533485A JPS6284541A (en) 1985-10-08 1985-10-08 Lead frame for semiconductor device

Publications (1)

Publication Number Publication Date
JPS6284541A true JPS6284541A (en) 1987-04-18

Family

ID=16827720

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22533485A Pending JPS6284541A (en) 1985-10-08 1985-10-08 Lead frame for semiconductor device

Country Status (1)

Country Link
JP (1) JPS6284541A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6441146U (en) * 1987-09-08 1989-03-13

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6441146U (en) * 1987-09-08 1989-03-13

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