JPS6284493A - Ic memory - Google Patents

Abstract

PURPOSE:To reduce power consumption without changing a maximum delay time and to speed up the operation without changing power consumption by equaling the timing of an address signal inputted to a decoder circuit irrespective of the length of wiring from an address gate to the decoder circuit. CONSTITUTION:Wiring lengths to a decoder driver 2 from plural address gates A, B, C, F and G satisfy a<b<c<f<g. Assuming that the average resistance value of the address gate A remains unchanged in order to flow a current amount in proportion to the wiring length, the average resistance value of the address gate G is made lower, and the others are set to the average resistance value in proportion to a parasitic capacity between them, every access time becomes the same as that of the gate A, and the actin is speed up. Assuming that the average resistance value of the address gate G remains unchanged, that of the gate A is made larger, and the others are set to the average resistance value in proportion to a parasitic capacity between them, all the current values can be constant, and the access times can be equal, thereby reducing power consumption.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The power supplied to a plurality of address gates is increased or decreased in proportion to the wiring length from the address gates to a required circuit. To this end, for example, the ratio of the resistances included in the address gates is changed at once between the Atotonose game 1 and each other.

[Industrial Application Field] The present invention is applicable to IC memory, for example, programmable ROM.
(Programmable Read Only M
(PROM).

As is well known, FROM is a read-only memory (storage device) in which programs are created according to the user's request, but the user wants the read operation to be as fast as possible, and also requires low power consumption. I also hope.

This project is a proposal to further meet that demand.

[Prior art and problems to be solved by the invention] Figure 1 shows an example of a FROM circuit block consisting of bipolar transistors, in which 1 is a memory cell, 2 is a decoder driver, and 3 is a multiplexer. A to ■ are address gates.

By the way, such FROMs are becoming highly integrated like other gate circuits, and the area of FROM substrates is gradually increasing, and memories are gradually becoming larger in capacity. Therefore, the wires connecting the circuit blocks have become longer, resulting in an increase in wire capacitance and a resulting delay in operation.

Among these, address gates in particular require connection with the outside, so they are often arranged scattered around the periphery of the board, as shown in Figure 1. Therefore, wiring to each address gate is difficult. The length varies, and the wiring capacitance of each address gate varies accordingly, causing a difference in operating speed of the address gate.

For example, in FIG. 1, the wiring length g from the address gate G to the decoder driver 2 is much longer than the wiring length a from the address gate A to the decoder driver 2.

Then, the wiring capacitance of address gate G is large,
The wiring capacitance of address gate A is small, and therefore the operating speed is different, with the access time of address gate G being slow and the access time of address gate A being fast.

On the other hand, when a user uses such a PROM, standards such as access time are written in the model book, and a desired electronic circuit is created based on this standard. The time standard is written according to the slow value (in the above example, the access time value of address game G). Furthermore, since power is supplied equally to addresses with fast access times and addresses with slow access times, power consumption is not effectively used to speed up access times.

As a result, the maximum delay time and power consumption listed in the model list may be evaluated to be lower than the performance of the device, even though the device can achieve even higher performance than the maximum delay time and power consumption listed in the model record. I am in a situation where I am In other words, conventional FROM can operate even faster, or
Although the power consumption is further reduced, it can be said that this structure is not fully utilized.

The present invention proposes a PRC) that can solve these problems and fully utilize the performance of the device.

[Means for solving the problem] The purpose is to reduce the power supplied to multiple address gates by
This is achieved by an IC memory that increases or decreases in proportion to the length of the wiring from the address gate to the required circuit.

To do this, for example, the ratio of resistances included in the address gates is changed all at once between address gates.

[Operation] That is, in the present invention, a plurality of address gates are configured so that the amount of current is changed in proportion to the wiring capacitance so that the access times are the same and the power consumption is equal.

In this way, it is possible to configure a FROM that can reduce power consumption without changing the maximum delay time, and it is also possible to configure a FROM that can operate even faster without changing the power consumption
It can be configured to M.

[Example] Hereinafter, an example will be described in detail with reference to the drawings.

The present invention will be explained with reference to the circuit block diagram of the FROM shown in FIG.
Respective wiring lengths a, b, c, and f from B, C, F, and G to the decoder driver 2.

The length of g is in a state where a<b<c<f<H. Therefore, conventionally, the parasitic capacitance to these wirings has increased proportionally, and therefore, the conventional access time becomes slow in proportion to its parasitic capacitance; the address gate G with the wiring length g is the slowest, and the address gate A with the wiring length a is the fastest.

However, in the conventional configuration, the largest current flows through address gate A and the smallest current flows through address gate G, and address gate A has the highest power consumption and address gate G has the lowest power consumption.

Therefore, the present invention configures the address gate so that an amount of current proportional to the length of the wiring to the address gate flows.

Then, the smallest current flows through address gate A, the largest current flows through address gate G, and current proportional to the wiring length flows through other address gates B, C, and F, and all addresses Access time from the gate can be kept constant.

In that case, if there is still room for the total power consumption of the device,
If you leave the current value flowing to address gate A unchanged and increase the current value to other address gates, the access time of all address gates will be the same as the access time of address gate A. hand,
Operation becomes faster.

In addition, if the current value flowing to the conventional address gate G is left as is and the current value to other address gates is decreased according to the parasitic capacitance of the wiring, the access time of all address gates can be reduced to that of the address gate G. The access time can be reduced as well, while power consumption is reduced.

Furthermore, it is also possible to take the power consumption of the device into consideration and distribute the power consumption in proportion to the wiring arrangement, thereby increasing the speed of operation without changing the power consumption of the device.

Now, a method of configuring all address gates to have the same access time as described above is to change the 1° C. resistance element (included in the address gate circuit) all at once in accordance with each address gate, for example. That is, FIG. 2 shows an address gate circuit, where In is an address terminal and Out is a connection to a decoder 1 driver (or multiplexer).

T is a transistor, D is a diode, +R1 to R7 are resistors, and the resistors R, , -R, are changed all at once.

At that time, the average resistance value of address terminal A is kept as IOKΩ as before, the average resistance value of address gate G is reduced to 8Ω, and the other address gates are set to an average resistance value proportional to the parasitic capacitance between them. Then, the access time of all address gates becomes the same as the access time of address gate A, and the operation becomes faster.

On the other hand, the average resistance value of the address gate G is set to I as before.
Leave it as OKΩ, and set the average resistance value of address gate A to 1.
If we set the other address gates to have a large resistance value proportional to the parasitic capacitance between them, the current value of all address gates can be made constant, and the access time becomes the same, making it easier than before. Power consumption is reduced.

Although the present invention has been described qualitatively above, it is actually created by performing precise calculations from the design standpoint.

It goes without saying that in FIG. 1, the address gates D, E, and If I connected to the multiplexer 3 are similarly implemented.

In this way, the present invention creates an efficient FROM by creating a FROM that matches the performance of the device.

[Effects of the Invention] As can be seen from the above description, according to the present invention, it is possible to reduce the power consumption of conventional devices without changing the maximum delay time, and it is possible to increase the speed of conventional devices without changing the power consumption. can be achieved.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram of a FROM to which the present invention is applied, and FIG. 2 is a circuit diagram of an address gate to which the present invention is similarly applied. In the figure, 1 is a cell, 2 is a decoder driver, 3 is a multiplexer, A-r is an address gate, R1-R7 is a resistor, and a+b+c+'+g is a wiring length. Uncivilized Embroidery '73 PROMnV Leisure Studies Figure 1 Figure 2

Claims (3)

[Claims] (1) Equipped with a plurality of address gates and a decoding circuit that decodes the address signal output from the address gate, and the timing of the address signal input to the decoding circuit is determined by the length of the wiring from the address gate to the decoding circuit. An IC memory characterized in that it is configured to be the same regardless of the location. (2) A patent claim characterized in that the timing of the address signal is adjusted by increasing or decreasing the power supplied to the address gate in proportion to the length of the wiring from the address gate to the decoding circuit. The IC memory according to item 1. (3) The IC memory according to claim 2, wherein the ratio of resistances included in the address gates is changed all at once between the address gates, so that the supplied power is increased or decreased.