JPH04279058A - Method of deciding layout of master slice type semiconductor circuit - Google Patents

Abstract

PURPOSE:To further improve the speed of a master slice type semiconductor circuit mounted with a BiCMOS gate. CONSTITUTION:In a master slice type semiconductor circuit in which a BiCMOS cell and CMOS cell are incorporated in a mixed state, cells G2 and G3 driven by means of a BiCMOS cell G1 are preferentially arranged near the BiCMOS cell G1. Therefore, the wiring length between the BiCMOS cell G1 and the cells G2 and G3 driven by the cell G1 can be reduced and the high speed property of the cell G1 can sufficiently be utilized.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to BiCMOS cells and CMOS cells.
The present invention relates to a layout method for a master slice type semiconductor circuit in which MOS cells are mixed. With the recent development of miniaturization technology, LSIs are becoming faster and larger. Among them, BiCM has both the small area and low power consumption of CMOS and the large drive capacity of bipolar transistors.
OS master slice type semiconductor circuits are attracting attention.

0002

[Prior Art] When using a BiCMOS master slice type semiconductor circuit, parts that require high-speed operation are driven by bipolar transistors, and parts that do not require such high-speed operation are driven by CMOS transistors. Design can be done.

[0003] As semiconductor circuits mounted on chips become larger in scale, the wiring connecting cells becomes longer. The output waveform of a cell transmitted through a long wiring becomes dull due to the distributed resistance and distributed capacitance of the wiring before reaching the gate of the next stage. The signal propagation delay time of the next stage gate is
Since it increases depending on how the input waveform becomes blunt, the wiring needs to be as short as possible.

0004

[Problems to be Solved by the Invention] BiCMOS gates operate at high speed and are considered to have large driving capabilities. According to this idea, BiCMOS gates may be driven far away by long wiring. However, the results of the analysis indicate otherwise. The present invention has been made with attention to this point, and an object of the present invention is to further increase the speed of a master slice type semiconductor circuit equipped with a BiCMOS gate.

[0005]

[Means for Solving the Problems] As shown in FIG. 1, in the present invention, when laying out a chip, attention is paid to cells G2 and G3 driven by BiCMOS cells, and these cells are Place it near BiCMOS cell G1. That is, the output terminal of G1 and the input terminal of G2, G
The gate arrays constituting G1 to G3 are selected so that the length of the signal line connecting the output end of G1 and the input end of G3 is as short as possible. In a gate array, only the common elements (mainly the diffusion layer) of various cells are created in advance, and finishing for each cell is done by wiring the common elements, so G2 and G3 are placed near G1. This can be easily done by selecting the above common elements. After that, the remaining cells G4, G5, etc. are appropriately arranged. In this example, gates G2 and G3 are CMOS cells, and G4
, G5 are arbitrary cells. Cells G4 and G5 are B
In the case of iCMOS, the next cells are cells G4 and G
Place it near 5.

[0006]

[Operation] Placing a cell driven by a BiCMOS cell in this way near the BiCMOS cell (placing it in a position where the waveform will not be too rounded even after wiring) will improve the high-speed performance of the BiCMOS cell. It can be fully demonstrated.

[0007]

Embodiment FIG. 2 shows the rise characteristics on the cell output side. As shown in FIG. 2(a), wires of various lengths L are connected to a cell G, and the cell is a BiCMOS cell or a CMOS cell.
The rising characteristics of the output end A and the wiring end B of the cell were determined using the cell. The horizontal axis of these figures (b) to (e) is time t (nS), and the vertical axis is voltage. Since the power supply voltage VCC is 5V, the final voltage after rising is this 5V, but this may not always be the case. In other words, in FIG. 2(b), cell G
is the rise characteristic of the output end A of CMOS, (c) is the rise characteristic of the wiring end B, and (d) is the rise characteristic of the output end A of the cell G.
The rising characteristic of the output end A of the MOS is the rising characteristic of the wiring end B, and (e) is the rising characteristic of the wiring end B. Each curve 1, 5, 10,...40
The wiring length L is 1mm, 5mm, 10mm,...40mm.
The rise characteristics are shown in the case of . As is clear from these curves, in the case of a CMOS gate, VCC rises to 5V, but in BiCMOS, as L becomes larger, VCC does not rise to 5V.

Furthermore, from these curves, it can be seen that in the BiCMOS gate, the rise is fast near the output end A, regardless of the magnitude of the wire length L, but the rise becomes slower at the wire end B as L becomes larger. Therefore, even if a BiCMOS gate is used with the expectation of high speed, this expectation will be disappointed if the next stage gate is driven through a long wiring. By arranging the next stage cell near the BiCMOS cell as in the present invention, the expected high speed can be obtained.

[0009] Also, as is clear from these curves, C
In a MOS cell, when the wiring length (load) becomes large, the rise is delayed at the output end, but in a BiCMOS cell, this does not occur, but the voltage value after the rise becomes low. When compared with the voltage rising to 4V, there is almost no effect of the wiring length at the output end of the BiCMOS cell, but at the wiring end, L=
1, 10, 20, 30, 40, approximately 0.6, 1.0, 2.
2, 4.0, 6.2 nS each. In a CMOS cell, the output end itself is affected by the wiring length, L=1, 10, 20,
30, 40 approximately 0.8, 1.5, 2.2, 3.1, 3.
8 nS each, L = 1, 10, 20, 30, 40 at the wiring end
This results in approximately 0.8, 1.6, 2.9, 4.4, and 6.4 nS each. At such long wiring ends, CMOS and BiCM
The OS will not change much either. This is related to the output terminal voltage, and in BiCMOS, the output terminal voltage decreases as L increases, so the rise of the wiring potential becomes slower.

FIG. 3 shows a flow chart of an embodiment of the layout method of the present invention. Temporarily place each cell on the entire chip as shown. At this time, BiCMOS cells having terminals having jitter properties are placed close to each other. Note that having a jitter property means that the BiCMOS cell terminal has an element that should be placed at a position where the waveform of the signal is not excessively rounded. Next, the cell you just placed is BiC
■ Check whether it is a MOS cell. If it is a BiCMOS cell, check whether there are any cells driven by this cell.■
, if any, rearrange the cells driven by that BiCMOS cell. Then, it checks whether this cell is placed within the specified range. If it is, it searches for a terminal (BiCMOS cell) with jitter property and checks whether the cell placement is complete.■ , If YES, give priority to wiring from the terminal with the jitter property■.

As is clear from FIG. 2, when a certain load capacitance is attached to the output of the BiCMOS gate, the speed changes depending on the operating frequency. In particular, communication
In transmission systems, this effect (jitter) is a concern. Figure 4
(a) is a diagram characteristically showing FIG. 2(e). As shown in this diagram, the output waveform of the BiCMOS rises steeply to a certain level, but then slowly rises with a large time constant. This tendency is more pronounced as the output load capacity becomes larger.

Now, consider the BiCMOS flip-flop shown in FIG. 4(b). In FIG. 4(b), D is a data terminal, CK is a clock terminal, and Q is an output terminal. Assuming that the clock CK and data D shown in FIG. 4(c) are input to the data terminal D and clock terminal CK, if the load is heavy, the output will be as shown in Q in FIG. 4(c). As can be seen from this output waveform, when data changes one after another, the output changes cannot keep up. This effect is BiCMO
Significant in S. Therefore, as shown in Fig. 4(b), the delay time is different between a change from H→L (or L→H) during a full swing and a change from H→L (or L→H) from an intermediate level. I end up.

For circuits in which such effects are of concern, the output load of the BiCMOS cell must be set so that the output of the BiCMOS takes full swing when the chip is operated at its maximum operating frequency. Here, controlling the length of the wiring is very important. The layout method is to add a jitter property to the output of the BiCMOS cell, and perform the layout so that the wiring length will be full swing when operating at the frequency given to the chip or BiCMOS cell. . The output rise time (fall time) Trf is Trf=K・CL,
CL = CG + CW where K is a constant, CG
When is the gate capacitance and CW is the wiring capacitance, the arrangement and wiring are made so that the relationship Trf/T<90% holds true, where T is the period and 1/T is the operating frequency. This formula means that the layout is such that the rising and falling operations are completed by 90% of the operation cycle. By performing such layout processing, L→H
, H→L delay time can be guaranteed as long as it is within the range of the maximum operating frequency. Although the explanation has been given using a flip-flop as an example, this method can be applied to all BiCMOS gates.

[0014]

[Effects of the Invention] As explained above, in the present invention, BiCM
Since the cell driven by the OS cell is placed near the BiCMOS cell, the high speed performance of the BiCMOS cell can be fully utilized.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of a layout method of the present invention.

FIG. 2 is a characteristic diagram showing the rise characteristics of a cell output.

FIG. 3 is a flow chart showing an embodiment of the layout method of the present invention.

FIG. 4 is a characteristic diagram of BiCMOS.

[Explanation of symbols]

Claims (1)

[Claims] 1. In a layout method for a master slice type semiconductor circuit in which BiCMOS cells and CMOS cells coexist, cells (G2, G3) driven by a BiCMOS cell (G1) are prioritized and placed near the BiCMOS cell. , A layout method for a master slice type semiconductor circuit characterized by shortening the wiring length between the cell and the BiCMOS cell.