JPS628225A - State detecting device for digital signal - Google Patents

Abstract

PURPOSE:To set a state to be detected optionally and to detect many states by using a memory stored previously with states to be detected corresponding to digital data supplied to an address input. CONSTITUTION:Two selectors 12 and 14 are switched to the sides of a memory setting address 13 and data corresponding to state detection is supplied as a set data 16 to an address corresponding to digital data 11, thereby writing the data in the memory 15. Then, the selector 12 is switched to the side of the digital data 11 and the selector 14 is switched to a feedback signal 21. Then a state detection output 17 is obtained from variation in the address of the memory corresponding to the digital data 11 and the feedback signal 21 corresponding to the contents of the last state detection output 17. A control output generating circuit 18 outputs a control output 20 corresponding to the state detection output 17.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a digital signal state detection device using a digital comparator using a digital memory.

[Technical background of the invention]

2. Description of the Related Art Conventionally, a device shown in FIG. 3, for example, is known as a device that performs control according to the state of a digital signal.

This device detects n states. That is, multiple bits of digital data 1 are input in parallel to each of the first to n-th state detectors x-1, 2-2, . . . , 2-n. And each state detector 2-1.2-2°...
. , 2-n have different states set in advance. Therefore, the state detection output 3 output from the state detector 2 whose contents match the digital data 1 is input to the control output generation circuit 4. The control output generation circuit 4 outputs a control output 5 corresponding to the contents of the input state detection output 3, and also feeds back to the control output generation circuit 4 itself.

Therefore, the control target (not shown) is a digital device.

- It can be controlled according to the contents of the data 1 and the control output 5.

[Problems with background technology]

However, such a device requires n state detectors in order to detect n different states of the digital data 1. Furthermore, the control output 5 is sent to the control output generation circuit 4.
In order to feed back the control output, the configuration of the control output generation circuit 4 becomes complicated, and the configuration for feeding back the control output is changed. This required changing the hardware, which was extremely troublesome.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and provides a digital signal state detection device that can arbitrarily set the state to be detected according to setting data and can detect a large number of states with a simple configuration. The purpose is to

[Summary of the invention]

That is, the present invention uses a memory in which digital data is applied to an address input, a state to be detected corresponding to the digital data is stored in advance as data at the address, and a data output of this memory is applied to a control output generation circuit. The device is characterized in that it obtains a control output and also feeds back the data output to the address input of the memory.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail with reference to the block diagram shown in FIG. Number 11 in the figure is digital data.
is applied to one input of the selector 12. 1 and 3 are the memory setting addresses and the first. Second selector 12.14
to each other input. And the first. The signal selected by the second selector 12.14 is applied to the address input of the memory 15. On the other hand, setting data 16 is input to the data input of the memory 15.

The data output from the memory J5 in response to the address input is temporarily stored in the register 16, and the state detection output 17 output from the register 16 is provided to the control output generation circuit 18 and the conversion circuit 19. Then, the control output generation circuit 18 outputs a control output 2 according to the content of the state detection output.
0 is output to control a control target (not shown).

On the other hand, the state detection output 17 output from the register 16 undergoes predetermined code conversion in a conversion circuit 19 and is applied to one input of the second selector 14 as a feedback signal 2.

With such a configuration, first. second selector 1
2. Switch 14 to the memory setting address 13 side and give the data corresponding to the status detection as the setting data 16 to the address corresponding to the content of the digital data 11.
Data is written to 5.

Then, the first selector 12 is switched to the digital data 11 side, and the second selector 14 is switched to the feedback signal 2 side.

Then, a state detection output 12 is obtained by changing the address of the memory according to the digital data 1 and the feedback signal 21 corresponding to the contents of the previous state detection output 17. Then, in response to this state detection output 17, the control output generation circuit 18 outputs the control output 2Q.The register 16 is connected to the memory 15 in synchronization with the clock signal.
Since the data output is captured and held, it is possible to remove glitches and the like (by reading during the valid period of the data output) and to capture accurate data.

Although the conversion circuit 19 is not necessarily provided, the conversion circuit 19 encodes, for example, the state detection output 17, and converts, for example, an 8-bit signal into three address signals by an 8-3 encoder. Take a note of this as the feedback signal 21 and give it to □S 15.
For example, the state detection output 17 is decoded by the 9, and 98 types of Tezzo select signals are obtained from the 3-bit signal by a 3-8 decoder, and the signals are applied as a feedback signal 21 to the memory 15, and the 8 signals provided in parallel are It is also possible to select one of the memories 15.

In the embodiment shown in FIG. 1, as the number of bits of the digital data 11 increases, the required capacity of the memory 15 increases significantly. In such a case, for example, as shown in Figure 2, it is possible to increase the required memory capacity by providing multiple memories in parallel and then providing cascaded memories whose outputs are given to the address input. It can be significantly reduced.

That is, in Fig. 2, 21-1, 21-2°...
, 21-n are first to nth memories.

Each memory 21-1, 21-2, -, 2 J-n
are the first selectors 22-1, 22-2°...
, 22-n, the first to nth digital data 2
J-1, 23-2) = , 23-n or first to nth memory setting addresses 24-1゜24-2, .
. . , 24-n is given to the address input. Furthermore, each memory 21-1.21-2. . . ., the second selector 25-1, 25-2 is connected to the address input of 21-n.
．． ..., each memory setting address 24 via 25-n.
-1.24-2. . . , a feedback signal 25, which will be described later, is input to a portion of 24-n. Furthermore, each memory 21-1
．． 21-2. ..., 21-n data input includes the first to nth setting data 26-1.26-2°..., 26
-n to set predetermined data.

Note that each digital data 23-1.23-2. ....

Numerals 23-n and 23-n are separate blocks in which the digital data whose state is to be detected are divided into a plurality of blocks. And each memory 21-1.21-2. ....

21-n each data output or memory setting address 27
is applied to the address input of the memory 29 via the selector 28. Setting data 30 is given in advance to the data input of this memory 29, and predetermined data is written to the address designated by -memory setting address 27. The data in the memory 29 read from the address specified by the data given via the selector 28 is temporarily stored in the register 3, and the control output generation circuit 3
2 and the conversion circuit 33 as a state detection output 34. The control output generation circuit 32 then outputs a control output 35 according to the content of the state detection output 34 to control a control target (not shown). Further, the output of the conversion circuit 33 is used as a feedback signal to each second selector 25-1.25-2°..., 25-
The contents of the previously output state detection output and the first to nth digital data 23-7 are fed back to the other input of n.
, 23-2)-.

A control output 35 corresponding to the contents of 23-n is obtained.

In this way, even if the number of bits of digital data increases, the increase in required memory capacity can be minimized, and increases in configuration and cost can be minimized.

〔Effect of the invention〕

As described above, according to the present invention, the content of the state to be detected can be arbitrarily set according to the setting data, and moreover, the digital signal allows detection of a state consisting of a combination of multiple bits with a simple configuration. A state detection device can be provided.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a block diagram showing another embodiment of the present invention, and FIG. 3 is a block diagram showing an example of a conventional state detection device. 15.21-1 to 21-n, 29...memory, 18.
32... Control output generation circuit, 19.33... Conversion circuit.

Claims (3)

[Claims] (1) A memory that stores data corresponding to the detection result at an address corresponding to the content of the digital signal to be detected, and receives the digital signal to be detected at the address input;
A digital signal state detection device comprising a control output generation circuit which is supplied with the data output of the memory and supplies a control output to a controlled object. (2) The digital signal state detection device according to claim 1, wherein a plurality of memories are connected in series. (3) The digital signal state detection device according to claim 1, which feeds back output data of the memory to the address input as a feedback signal at the next readout.