JPS6281839A - Sampling phase detection circuit - Google Patents

Abstract

PURPOSE:To attain high speed modulation by inverting the polarity of every other signal extracted in an odd/even number order from a signal sampled and outputted at a frequency being twice the modulation speed from a synchronizing demodulation analog signal and multiplying the inverted signals. CONSTITUTION:The synchronizing demodulation analog signal is sampled (14) by using a clock signal having a frequency 2fs being twice the modulation speed. The odd number order signal from the sampled signal is extracted by an extraction circuit 15, and every other sampled signal is subjected to polarity inversion 16. The signal of an even order number is extracted by an extraction circuit 17 and the polarity of the every other extracted signal is inverted (18). Outputs of both polarity inverting circuits 16, 18 are multiplied (19) to obtain an output signal S0. Thus, the frequency of the clock signal in use has a maximum speed being twice the modulation speed and the other sped is 1/2 or 1/4 of the modulation speed to attain high speed modulation.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention provides
The present invention relates to a means for reproducing black and white from a signal, and particularly to a phase detection circuit that is effective for reproducing black and white in a digital processing type abdominal adjuster.

(Prior Art) A second species detection circuit was constructed as shown in FIG. 1. The timing of the faulty analog [No. 3 51 is extracted by the timing extractor 502. Ii? The phase difference with the reference clock signal 53 that is being detected is detected by the reset circuit 503.
3 outputs a signal 54 corresponding to the phase difference between the extracted signal 52 and the reference black I7 signal 53.The second phase difference signal 54 has phase information in the pulse width, so to obtain the phase difference, the pulse width must be integrated. The important point is that if the demodulator uses analog processing, it can be processed by a product SY unit, but in the case of a digital processing type modulator, it is necessary to integrate digitally.

In this example, a method is shown in which integration is performed using a counter 504.The counter 504 performs counting only when the level of the signal 54 is logical "1°" due to the high-speed clock signal 55. Initial (hi (generally zero)
be done.

FIG. 5 is a time chart 1 showing the operation 1t of the conventional detection circuit shown in FIG.

(Problems to be Solved by the Invention) The phase resolution of the above conventional phase detection circuit is determined by the frequency of the high speed clock. In order to improve the phase resolution, it is necessary to increase the frequency of the high-speed clock and to increase the speed of the counter accordingly. In order to obtain the necessary phase resolution, a high-speed motion [t that is 30 times or more of the modulation speed is usually required. Therefore, there was a problem in that a high processing speed was required.

SUMMARY OF THE INVENTION In view of the above-mentioned problems of the prior art, an object of the present invention is to provide a phase detection circuit that does not require high-speed processing of modulation speeds of 30 (Means for solving problems). In order to achieve the above object, the present invention has the following configuration. That is, the sampling phase detection circuit of the present invention samples a synchronously demodulated analog signal at a frequency of 2 (f!i) of the modulation rate, and generates a sampled signal. A sampling circuit that outputs: a first signal extraction circuit that sequentially extracts odd-numbered sampling signals from the sampling signal; a first polarity inversion circuit that inverts the polarity of the extracted signal every other signal; a second signal extraction circuit that sequentially extracts even-ranked sampling signals from the sampling signals; a second polarity inversion circuit that inverts the polarity of the extracted signals every other signal; and the first polarity inversion circuit. and a multiplier that multiplies the output of the second polarity inversion circuit by the output of the second polarity inversion circuit.

(For 1 year use) Hereinafter, the use of the phase detection circuit of the present invention will be explained based on the drawings. FIG. 1 is a block diagram showing the configuration of the phase detection circuit of the present invention, FIG. 2 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 3 explains the operation in the configurations of FIGS. 1 and 2. This is the time chart 1 for doing this.

Now, the synchronous demodulated analog signal d input to the sampling circuit 1
(t) as d(t)=cosπt'st...
(1) However, +5 is the modulation speed.

The sampled output YEI<11) of the sampling circuit 1 with a clock of 21 & frequency 2fs of modulation speed f5 is Y, (n) = cos πfs<n-[:! -+to
)! 1π L ・cO5 (・+π 2) ... (2) T f days, T=1/fs 70 −・Phase shift time n becomes a natural number.

The first signal extraction circuit 15 extracts odd-numbered signals from among the signals expressed by equation (2), and the second signal extraction circuit 17 extracts even-numbered signals. Therefore, (2)
The equation is decomposed into terms for even number sampling of n = 0.2.4.6゜8... and terms for odd number sampling of n = 1.3゜5.7.9..., and each is expressed as Y,... ,Y. Then,
Yps (k > =cos (k π+-T-t
o) -・-111-(3)Y-10=CO8
(−L2−Hπ+tent.)=cos(kπ−]]薯+−
7-t) = sin (kyr +・7・t o)
...(4) However, k is a positive integer.

The signals of equations (3) and (4) are expressed by Ifi during period T=
The phase angle increases by π radians, indicating that the signal has the same oscillation angle and the polarity is reversed every cycle T.

By the way, the output of the first signal extraction circuit 15 (the first polarity inversion circuit 16/\+5 is added, and the positive inversion is performed on the extracted signal every other cycle. Similarly, the second signal extraction circuit The output of 17 is applied to a second polarity inversion circuit 18, which inverts the polarity of the extracted signal every other period. This means that the value of k in equations (3) and (4) advances by 1. Unit f thread count (-1)' or (-1
7, which means multiplying by 1'', the exponent part of the above count is k
The reason for +1 in or is due to the fact that in equations (3) and (4), whether the handwriting inversion is performed for the 1st direction when k is an even number, or the positive inversion is performed for the value when k is an odd number. This depends on the phase ambiguity as to when the polarity inversion circuit starts operating. Similarly, if we rewrite the above rank coefficient, it becomes (-1)'(-1)' (the proviso indicates the ambiguity of polarity and is O or 1). The output of the subject inversion circuit 16 )°;o
(k), and the output of the second polarity inverting circuit 18 is represented by the following equations, that is, Y;. (k) −(-1)'(-1>'.os
(kff+"-7)■ = (-1>'cos-'-π T-(5) Y, o(k) = (-1)'(-1)'s t n
(' to π+'-'-π>1(-1)・sin''LπT・(61) 1. Output J expressed by equations (5) and (6)) The signal is added to the multiplier 19/\ If the output signal for which the product is calculated is S, then S, -, ='l'□ (k) ・ Y Nira (1(
n = (-1)'C03-yr-(-1)'s i n-
'-πT T ='-s i n t, ,, T, ,,-,,,,
, -1(7)2 -T, and if we set 2π]t=θ, then S =・”・
5inθ... (8in From this θ=s in ”' 2 So
-1.-(9), and the output S of the multiplier 19. The phase difference between the modulation rate signal and the sampling clock signal can be detected from . By controlling the phase of the clock signal so that this phase difference becomes zero, transmission
It is possible to reproduce a clock whose phase matches that of the other clock.

As is clear from the above-described operation, the phase detection circuit of the present invention only uses a clock signal with a frequency of 2 (@) of the modulation speed and does not use a high-speed clock 1, so (T is not required.

(Example) Hereinafter, an example of the sampling phase detection circuit of the present invention will be described based on the drawings. FIG. 2 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 3 is a time chart for explaining operation 1. The synchronous demodulated analog signal 1 expressed by equation (1) is converted into a bit (k is a positive integer) quantum (hi ] For the sake of explanation, FIG. 3 is expressed in terms of analog amplitude.

This output is a bit quantized signal 5 expressed by equation (2).
is a D-type flip-flop (hereinafter D-F/
(denoted as F) 102, the sampling is delayed by the clock signal 3 having a speed of f3, and a signal 4 is obtained. Ikekata D-F/F
The clock signal 105 is sampled and delayed by the clock signal 14 obtained by passing the clock signal 3 through the polarity inverter 107 to obtain the signal 6. In this way, the sampling clock signal with a frequency of 2f3 is delayed.
The signal sampled by the clock is extracted using a clock signal obtained by dividing the sampling clock by 1/2 and a clock signal whose polarity is inverted, so each sampled signal is extracted alternately every other time. There will be. Therefore, if the signal 6 is the order of the number of copies, the signal 4 is the signal of the odd number order. Two and (Konaru.

D-F・'F102 output 1 word 4 is further D-FF10
4 to obtain signal 7, which is delayed by D-FF102 and D
-F F2O3 and signal D =/ Since the signals have inverted polarities (No. 3 4 and signal 6, the sampling delay waveform is exactly one cycle of 2'I'r (T,
, -'2), so in order to match the phases of both signal waveforms, signal 4 is delayed by T,.2 by D-F,'F104.

Ii6, after all, the output signal 6 of D-F y' F 105 is Ype (k+) of equation (3), and I)-F-'F1
The output 1 word 7 of 04 is Y, o(k) in equation (4) 4 Then, the signals 6 and 7 are polarity inverted Ht
109 and 108 respectively.A signal 8 obtained by dividing No. 3 14 by 17'2 by a 1/'2 frequency divider 106 is applied to the input terminals of these polarity inverters. The devices 108 and 109 receive the 1/2 clock signal 8.
For example, when the input value is logic “0”°, the input value is inverted and the logic “°1” is set.
When it is ゛, it moves 1 way so that it does not reverse. (The output signal 9 of the morphological inverter 109 is expressed by Equation (5), and the output signal 10 of the polarity inverter 108 is the output signal of the polarity inverter 109, expressed by Equation (6). 9 is input to the averaging circuit 110, and the output signal 10 of the polarity inverting circuit 108 is input to the averaging circuit 111.
1 is used to remove the influence of noise that is generated in the 51 transmission path and mixed in the signal.

Regarding the eleventh aspect of the present invention, the output signal 11 of the averaging circuit 110 can be expressed by equation (5) similarly to the input signal 9, and similarly, the output signal 1 of the averaging circuit 111 can be expressed as
Signal 11 and signal 12, expressed by equation (6), are applied to multiplier 112 and multiplied there. As a result, output 1 word 13 of equation (7) is obtained.The output signal is equation (7)
) or Equation (8), so the difference in order (0) between the modulation rate signal and the sampling clock signal can be detected using Equation (9).

In the above embodiment, the sampling circuit 14 of the A, /D2tA unit 101 and the D-F/F 102 and the D-F
/F104 is connected to the first signal extraction circuit 15, D-F/F1
05 corresponds to the second signal extraction circuit 17, the polarity inverter 108 corresponds to the first polarity inversion circuit 16, the polarity inverter 109 corresponds to the second polarity inversion circuit 18, and the multiplier 112 corresponds to the multiplier 19. .

(Effects of the Invention) As described above, the sampling phase detection circuit of the present invention has the highest frequency of the clock signal used, which is a sampling clock with a frequency of 2 (fj) of the modulation rate. is one-half or one-fourth of that frequency. Therefore, high-speed motion 1t that is more than 30 times the modulation speed
Compared to the phase detection circuit from Ue that requires Assuming this, the operating speed of the phase detection circuit can be much lower than the conventional one, which has the advantage of greatly simplifying circuit design and circuit manufacturing.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a phase detection circuit according to the present invention, FIG. 2 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. FIG. 4 is a block diagram showing the configuration of a conventional phase detection circuit, and FIG. 5 is a time chart explaining the operation of the conventional circuit. 14... Sample 11 circuit, 15... First Signal extraction circuit, 16..First polarity inversion circuit, 17..Second signal extraction circuit, 18..Second polarity inversion circuit, one.
・Multiplier, 101...A,/D converter, 102
・・D・F/F (D type flip-flop), 103・
・Half frequency divider, 104.105...D・F/F,
106...Half frequency divider, 107...Polarity inverter, 108.109...Polarity inverter, 110,11
1: Average circuit, 112: Multiplier, 502: Timing extractor, 503: Set/reset circuit (D/F/F), 504: Counter. Agent Patent Attorney Yoshi Hachiman Hiromoto f:
The circuit of the circuit cutting the skin Fig.1, (e) yqs!＞7Utsuk56 m2″″i″″11
'7r7frMJ7+ulylj+NiT! 17・m
'rhW.

Claims (1)

[Claims] a sampling circuit that samples a synchronously demodulated analog signal at a frequency twice the modulation rate and outputs a sampled signal; a first signal extraction circuit that sequentially extracts odd-numbered sampled signals from the sampled signal; a first polarity inversion circuit that inverts the polarity of the extracted signal every other signal; a second signal extraction circuit that sequentially extracts even-ranked sampling signals from the sampled signals; a second polarity inversion circuit that inverts the polarity; and a multiplier that multiplies the output of the first polarity inversion circuit and the output of the second polarity inversion circuit. detection circuit.