JPH0392772A - Digital watt meter - Google Patents

Abstract

PURPOSE:To achieve a reduction in errors by providing a circuit to generate a sampling pulse synchronizing an input voltage or a current waveform. CONSTITUTION:A timer 25 counts a clock signal CLK1 to output a pulse and an interrupt 1 of a microprocessor 32 is started by a timer output so that a value of an incremental counter 29 is turned to a half during a second conver sion period to be set on a reset decremental counter 27. The counter 27 applies an output to a monostable multivibrator 24 with a decremental counting of a set value according to a clock signal CLK3 and a sampling pulse of an output value of the counter 27 is generated to be applied to a sampling/holding circuits 15 and 16. After a flip flop 28 is set by an output of the timer 25, a zero- crossing detection circuit 26 detects a zero-crossing point of an input voltage waveform and the flip flop 28 is reset to start an interrupt 2 by a rising edge of an inversion output. This can minimize errors in the measurement of power.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is applied to a digital wattmeter using a digital sampling method. The present invention particularly relates to a digital power meter that performs sampling using a sampling link pulse synchronized with an input.

〔overview〕

The present invention reduces measurement errors in a digital wattmeter that measures power by sampling and integrating voltage and current inputs by sampling with a sampling pulse synchronized with the voltage or current input.

[Conventional technology]

Conventionally, analog multipliers have been used as digital wattmeters, which first convert alternating current to direct current and then convert it to digital. Further, a digital sampling type power meter is known in which AC input is directly sampled and converted into digital data, and the output is calculated to measure power.

[Problem to be solved by the invention]

Although this digital sampling method differs depending on the calculation method, there is a problem in that when averaging is performed after collecting multiple samples, the error becomes large unless synchronization is performed with the input.

Next, the principle of occurrence of this error will be explained.

The average AC power (hereinafter simply referred to as AC power) P is the average of the integrals of the instantaneous voltage value v (t) and the instantaneous current value i (t) over one cycle time T, and is expressed by the following equation (1). It is expressed as

The voltage waveform v (t) shown in FIGS. 3(a) and (b),
In power calculation using a digital signal obtained by sampling the current waveform 1(t), the AC power P is defined as the voltage/current digital signal V(k), ]
(g), and when the sampling interval t5 is decreased and the number of samples in one period is increased to n, then this is the bond sum average of each sample value, which is expressed by the following equation (2).

This digital sampling type power meter was actually used (2
), and is simplified as shown in Figure 4 (a) and Q:1), when the AC frequency is unknown, the true period t1o of the AC and the total sampling period n - tS may not match. could be. This is a cause of error in the digital sampling method.

The error ε will be explained based on FIG.

The voltage digital signal V (k) and the current digital signal i Ck) are expressed by the following equations (3) and (4).

v(k)-Vm s+n(k・φs).
．． −． (3)i(k)-I. sin(k-φS) (4)
However, ■. : Maximum voltage ■. &; Maximum value of current k: sampling number from k=o to n-1 φ5: Electrical angle of -v link interval tS Substitute (3) and (4) into equation (2) to find AC power P The following equation (5) is obtained.

The second term of this equation (5) becomes zero when the above-mentioned AC period jlr+ and the total zumbling period n-tS match, but
When they do not match, there is a difference φ6, so this difference φd is the error ε
becomes.

The error ε due to the difference φ6 is expressed by the following equation (6).

From this equation (6), it is known that the method of reducing the error of the power meter using the sampling method is to reduce the difference φ, or to vary the number of samples by a large amount.

The present invention reduces the error by providing a circuit that generates a sampling pulse in synchronization with the input voltage or current waveform so as to reduce this difference φ, and sampling with the sampling pulse synchronized with the input waveform. The purpose is to provide a digital wattmeter that can

[Means to solve the problem]

The present invention provides sampling means for sampling voltage input and current input based on a given sampling pulse, and means for digitally converting the voltage input and current input sampled by the sampling means and then integrating them to obtain a power detection output. A digital wattmeter is equipped with a reference oscillator that generates a clock signal, a zero cross detection means that detects a zero cross point of an input waveform, and a detection output of the zero cross detection means that starts counting, and continues. Counting circuit means for counting the clock signal or its frequency-divided output up to a zero-crossing point in a period, and a number of sampling pulses to be generated for each period is set based on the counting result of the counting circuit means, and the countdown output is set. The present invention is characterized in that it is provided with a counter means for counting the number of outputs of the counter means, and a sampling pulse output means for outputting the number of sampling pulses output from the counter means at each cycle in synchronization with the clock signal or its frequency-divided output.

[Effect]

The zero-crossing point of the input waveform is detected, and upon this detection, the clock signal output from the reference oscillator or its frequency-divided output is counted, and the number of sampling pulses to be output for each cycle is counted. The number of sampling pulses obtained as a result of this counting is set in a preset down counter, and a countdown is output from the start of the next converted conversion period (the next conversion period after the conversion period in which the zero crossing point was detected). , outputs sampling pulses synchronized with the clock signal output from the reference oscillator or its frequency-divided output for the number of countdown outputs output from the preset down counter.

This sampling pulse is a pulse that is synchronized with the input waveform, and since the input voltage and input current can be digitally converted by the sampling pulse that is synchronized with the input waveform, errors in the sampling method can be extremely reduced.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the structure of a digital wattmeter according to an embodiment of the present invention.

The digital wattmeter of this embodiment includes a circuit 1 that samples and digitally converts an input voltage waveform and an input current waveform based on a given sampling pulse, and integrates the digitally converted voltage and current values;
This circuit 1 is composed of a circuit that generates sampling pulses to be applied to the circuit 1. The circuit that generates this sampling pulse includes a zero-cross detection circuit 26 as a means for detecting a zero-cross point of an input voltage waveform or an input current waveform (the following will be explained with reference to the input voltage waveform), and Triggered by the detection output of the detection circuit 26, counting is started,
A counter 29 counts the frequency-divided output of the clock signal output by the reference oscillator 2l up to the zero-crossing point in the subsequent cycle, and the number of sampler pulses that should be generated in each cycle is calculated based on the count result of this counter 29. As a sampling pulse output means for outputting a number of sampling pulses equal to the number outputted by the preset down counter 27 and the preset down counter 27 in synchronization with the divided output of the clock signal outputted by the reference oscillator 21. It is equipped with 24 mono multi-by-breaks.

Further, the circuit for generating the sampling pulse includes a microprocessor 32 that controls the generation and setting of the sampling pulse in the above-mentioned circuit.

Next, the structure of this embodiment will be specifically explained.

The part of the circuit 1 surrounded by the dotted line shows the IT of a conventional digital sampling type power meter.

This digital sampling power training circuit 1 includes amplifiers 11 and 12 that amplify the input voltage waveform and current waveform, respectively, low-pass filters 13 and 14 that remove a certain amount of high frequency from the amplified waveform, and a sampling pulse generator. Sample-and-hold circuits 15 and 16 that sample the voltage and current waveforms output from the low-pass filters 13 and 14, respectively, using sampling pulses given from the generating means, and this sample-and-hold circuit 15
, l6, respectively, and the outputs of these analog-digital conversion circuits 17 and 18 are input, and the converted digital voltage value and digital current value are integrated to obtain a power value. A digital signal processor 19 is provided as a digital arithmetic circuit for calculating.

Next, the structure of the sampling pulse generation circuit, which is a feature of this embodiment, will be explained.

A reference oscillator 21 generates a clock signal CLKI, the output of which is directed to a multiplier 22 and a timer 25.

The multiplier 22 receives the clock signal CLKI of the reference oscillator 21.
Divide into 1/H. This frequency division number N is set to be twice the sampling frequency fS. Clock signal C L divided by 1/H by frequency divider 22
K2 is input to the up counter 29, and
The signal is input to a frequency divider 23 which divides the frequency by 1/2. Furthermore, the clock signal CLK3 whose frequency has been divided into 1/2 by the frequency divider 23 is inputted to the mono multi-by-break 24 and also inputted to the clock terminal of the preset down counter 27. The output of the mono multi-by-break 24 is led to sample hold circuits 15 and 16.

The output of timer 25 is routed to the cent input of flip-flop 28 and to the first interrupt terminal of microprocessor 32. The control output 1 of the microprocessor 32 is led to the reset input of the timer 25.

The output of the low-pass filter 13 of the digital wattmeter circuit 1 is also led to a zero-cross detection circuit 26, and the detection output of this zero-cross detection circuit 26 is led to the reset input of a flip-flop 28. Also Flimp Flossop 2
The inverted output 6 of 8 is led to the second interrupt terminal of the microprocessor 32.

The control output 2 of the microprocessor 32 is input to the enable terminal of the up counter 29, the control output 3 of the microprocessor 32 is input to the reset terminal, and the up counter 29 is connected to the data bus 33. There is. This data bus 33 is input to a microprocessor 32, a latch circuit 30 described below, and a digital signal processor 19.

The control output 4 of the microprocessor 32 is the latch circuit 30
The data bus 33 is connected to the data input terminal of the latch circuit 30, and the take output terminal is connected to the preset down counter 27. The output of the delay circuit 31 is the preset down counter 27
is input to the set terminal of brisset down counter 2.
7 output terminal Q. is connected to the reset terminal of the mono multi-bi break 24 and also to its own reset terminal.

Further, the control output 5 of the microprocessor sensor 32 is guided to the digital signal processor 19.

Next, the operation of this embodiment will be explained based on the time chart shown in FIG.

1 2 Preparation for synchronization to the voltage waveform according to this embodiment requires two conversion cycles, and since the first conversion cycle and the second conversion cycle are operations at startup and are not in a steady state, their explanation will be omitted. Now, the third conversion period and the fourth conversion period will be explained.

By counting the clock signal CLKI, the timer 25 outputs a pulse every cycle of the set time T as shown in FIG. 2(a) to determine the starting point of the conversion cycle. Including 1 works. Furthermore, the Frisov flop 28 is set by the output of the timer 25.

(2) The microprocessor 32 transfers to the precent down counter 27 a value n1 obtained by halving the value m1 read from the up counter 29 in the second conversion period by the operation of interrupt 1. The reason for shifting by 1/2 is to eliminate one count error due to the difference between the gate time T2 starting from the zero-crossing point and the clock signal CLK2.

The brisenote down counter 27 receives the cent value n,
13 is down-counted according to the clock signal CLK3, and the count output is given to the mono multi-by-break 24. When the down count value reaches "0", the preset down counter 27 remains "0" until the next preset.
Stay as you are. The mono multi-by-break 24 uses the count value n1 output from this preset down counter 27.
sampling pulses are generated and applied to sample and hold circuits 15 and 16.

When the count value of the preset down counter 27 becomes "0", the mono multi-by-break 24 does not operate the preset down counter 27 even if the clock signal CLK3 is applied.
Sampling pulses are not output due to the reset input given by .

After the flip-flop 28 is set, when the zero-cross detection circuit 26 detects the zero-cross point of the input voltage waveform, the flip-flop 28 is reset by this detection output.
The rising edge of the inverted output d of flip-flop 28 activates interrupt 2 of microprocessor 32. The microprocessor 32 converts the control output 2 into an up counter 2.
9, the count value of the up counter 29 is read out, and the value is set as m214. Immediately after reading, the control output 3 is output to reset the up counter 29 and restart counting.

■ When the next conversion time T set in timer 25 is reached,
The timer 25 outputs an output, sets the Frisopfron knob 28, and activates the microprocessor 32's interrupt (2). The microprocessor 32 presets the preset down counter 27 to the value n2, which is 1/2 of m2, and starts counting down. The mole multi-by-break 24 supplies the n2 sampling pulses output from the preset down counter 27 to the sample hold circuits 15 and I6 in the fourth conversion period.

At this time, the microprocessor 32 takes in the data calculated by the digital signal processor 19 during the third conversion cycle through the control output 5, converts it into a desired data format as a power meter, and outputs it to a display, etc. do.

Then, when the inverted output d of the flip-flop 28 rises due to the output of the zero-cross detection circuit 26, the microprocessor 32 reads the count value m3 of the up counter 29, and immediately performs a reset during the next gate period T2. clock signal CI. Restart K2 counting.

After that, the operation in the third conversion period and the fourth conversion period is repeated.

In this way, by detecting the zero-crossing point of the voltage waveform and giving the number of sampling pulses to be output in the next conversion period in synchronization with the input voltage waveform, even if the period of the input voltage waveform is unknown, the input A sampling pulse synchronized with the period of the voltage waveform can be provided. Note that the same implementation can be performed by detecting the zero cross point of the current waveform.

〔Effect of the invention〕

The present invention is configured as described above so that the input voltage waveform and the input current waveform can be sampled by the sampling pulse synchronized with the input waveform.
Errors in power measurement in the digital sampling method can be reduced.

16

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention. FIG. 2 is a time chart of the embodiment. FIGS. 3 and 4 are waveform diagrams illustrating errors. 11, 12...Amplifier, 13, 14...Low pass filter, 15, 16...Sample and hold circuit, 17,
18... Analog-to-digital conversion circuit, 19... Digital signal processor, 21... Reference oscillator,
22...multifrequency divider, 23...1/2 frequency divider, 24.
...Mono multi-by-break, 25...Timer, 26
. . . Zero cross detection circuit, 27 . . . Brisset down counter, 28 . . . Flip-flop, 29 . L32...Microprocessor, 33...Data path. 1 7 JP3 92772 (7) Yoyo

Claims (1)

[Claims] 1. Sampling means for sampling voltage input and current input based on a given sampling pulse; and power detection by digitally converting the voltage input and current input sampled by the sampling means and then integrating the data. A digital wattmeter is equipped with a reference oscillator that generates a clock signal, a zero-cross detection means that detects zero-cross points of an input waveform, and a digital wattmeter that performs counting using the detected output of the zero-cross detection means as a trigger. counting circuit means for counting the clock signal or its frequency-divided output from the start to the zero-crossing point in the subsequent cycle, and the number of sampling pulses to be generated for each cycle is set based on the counting result of the counting circuit means. It is characterized by comprising a counter means for generating the countdown output, and a sampling pulse output means for outputting the number of sampling pulses outputted by the counter means at each period in synchronization with the clock signal or its frequency-divided output. Digital wattmeter.