JPH0723899B2 - Electric quantity detection processing device - Google Patents

Description

Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to an electrical quantity detection processing device for detecting active power, reactive power, power factor, and the like, and particularly for, for example, one cycle of a commercial power frequency. Many sampling points are set in the first half by increasing the sampling rate, and the required data such as interphase voltage and phase current related to commercial power is acquired, and a digital data processor such as a microprocessor is set within the predetermined time in the second half. The present invention relates to an electrical quantity detection processing device in which the above-described electrical quantity detection processing is performed quickly and accurately by performing necessary calculations.

[Prior Art] Conventionally, in a device of this type, an analog calculator such as an analog multiplier is usually used as a part for performing necessary calculations on analog inputs such as input voltage and current. However, this type of analog calculator cannot be expected to be accurate and is susceptible to the influence of the surrounding environment such as temperature change.

In addition, a conventional device of this type has a sample rate of 1.
Many of them are extremely low at about 5 times / second, and this cannot be expected to improve accuracy, and there is also a problem that it takes a lot of time to warm up.

On the other hand, in recent years, a device for performing digital processing has also appeared. For example, the example disclosed in Japanese Patent Publication No. 56-158954 is
It measures electrical quantities in analog and converts the results into digital quantities for digital processing, which is beyond the scope of analog measurement.

Further, for example, the example shown in JP-B-57-137863,
Unlike the above example, digital processing is performed from the time of measurement. However, since the sampling operation is a random operation that is not synchronized with the input waveform, it requires a large memory capacity and a large amount of arithmetic processing time to obtain the required accuracy.

Further, for example, the example shown in Japanese Examined Patent Publication No. 54-1667,
The sampling operation is synchronized with the input waveform. But,
It takes a lot of time to obtain the result because the input signal and one cycle are sampled only once, and the electrical quantities are calculated according to the contents of the memory after all data for one cycle is stored in the memory. However, there is a problem that a memory for storing data is also required.

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above-mentioned various problems in the conventional apparatus of this type, in which the sampling rate of the sampling operation can be set high, and the data processing is performed digitally. , The sum of the squares of the three types of interphase voltages, the sum of the squares of the three types of phase currents, and the effective power By performing each calculation of the total sum and the total reactive power based on the d, q conversion theory,
It is an object of the present invention to provide an electrical quantity detection processing device that does not require a memory for storing sampling data and can quickly obtain highly accurate electrical quantities.

Embodiments of the Invention Embodiments of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG.
The figure is a waveform diagram. In FIG. 1, reference numeral 1 is an analog multiplexer, and on the input side, the interphase voltages VRS, VST and VTR of the three-phase AC on the generator 30 side, the phase currents IR, IS and IT, the field current FI and the system side 3 The interphase voltage SVRS of the phase alternating current is applied to each of them, and these input signals are output signals one by one in a predetermined order. 2 is an analog multiplexer 1
Is an A / D converter that takes in the output signal of and performs A / D conversion operation, starts A / D conversion by the A / D conversion command signal START, and outputs a completion signal Sf when A / D conversion is completed. Also, A / D
The converted value is output as serial data from the output terminal S0.

3 is a counter that counts the completion signal Sf, and returns to the reset state each time when the completion signal Sf indicating that the final electrical quantities (phase voltage SVRS) has been A / D converted from the first reset state is counted, The analog multiplexer 1 is made to output various electrical quantities in a predetermined order. Reference numeral 4 is a first 0-point detector, and 3
Electric quantities on the side of the generator 30 connected to the phase alternating current RST, for example, 0 point of the interphase voltage VRS is detected, and + 5V is detected every time the 0 point is detected.
And a rectangular wave frequency signal f ₁ that changes between 0 V and 0 V (see “Square wave on lead wire 110” in FIG. 2). Reference numeral 5 is a second zero point detection unit that detects the zero point of the interphase voltage SVRS on the system side, and operates in the same manner as the first zero point detection unit 4.

Reference numeral 6 denotes an analog input control circuit, which is started by a start signal P ₀ from a first microprocessor (described later), outputs the first A / D conversion command signal START, and then is completed by the A / D converter 2. The A / D conversion command signal START is output every time the signal Sf is received.

Reference numeral 7 denotes a PLL circuit, which multiplies the frequency of the frequency signal f ₁ output from the first zero-point detector 4 by a predetermined number (for example, 128 times) and outputs it as a frequency signal f ₂ composed of a pulse signal.
Reference numeral 8 denotes a frequency dividing circuit, which divides the frequency of the frequency signal f ₂ by a predetermined number (for example, 128) and outputs it as a frequency signal f ₁ ′.

If the frequency signals f ₁ to be input to the PLL circuit 7 is varied for some reason, the phase difference between the frequency signal f ₁ 'is fed back via the frequency signal f ₁ and the frequency dividing circuit 8 is generated, The PLL circuit 7 changes the output cycle in order to eliminate this phase difference. Accordingly, the frequency signal f ₂ output from the PLL circuit 7 (= 128f _1), the frequency signal f ₁ and
It is stable when the phases of f ₁ ′ match. For example, if the frequency of the frequency signal f ₁ is increased, the frequency signal f ₁ of the phase leads that the phase of the frequency signal f ₁ ', the phase difference between them occurs. Therefore, the period of the frequency signal f ₂ is shortened, the phase of f ₁ ′ is advanced, and the frequency signals f ₁ and f ₁ ′ are advanced.
The frequency signal f ₂ is stabilized when there is no phase difference during the period.

A is a gate connected to the output side of the PLL circuit 7 and takes the AND of the frequency signals f ₁ and f ₂ . Reference numeral 9 is a first microprocessor for calculating effective values of various electric quantities, and 10 is a second microprocessor for calculating active power P and reactive power Q, which are respectively an input terminal SI for serial data, a chip select CS, It has an interrupt INT for receiving an interrupt signal, an 8-bit parallel data input / output unit D, a clock input unit SCK for data fetch timing, and a clock input unit CLK for timing control of the microprocessor itself. The first microprocessor 9 outputs the activation signal P ₀ in response to the interrupt INT input from the gate A and outputs the interrupt IT to the host computer P ₁
have.

Reference numeral 11 is a clock generator, which is a clock input section for timing of data acquisition of each microprocessor 9 and 10.
A clock signal for SCK (for example, 2 MHz), a clock signal for a clock input section CLK for timing control of each microprocessor 9 and 10 itself (for example, 8 MHz),
A clock signal (for example, 1 KHz) supplied at the time of starting the generator 30 to the generator-side frequency detection unit (described later), the generator
After 30 reaches a steady state, a clock signal (for example, 100 KHz) supplied to various detection units (described later) is generated.

Reference numeral 12 is a parity generator that generates the parity of the input / output data, and is connected to the data bus 112. Reference numeral 13 is a data buffer for sending the data output from the respective microprocessors 9 and 10 to the host computer, and is connected to the data bus 112. 14 is a match selector,
According to the memory read command MRDC from the host computer, one of the microprocessors 9 and 10 and various detection units (described later) is selected and the chip select CS is activated. Also, chip select CS
By sending an XACK signal after a certain period of time after activating, the upper computer is notified that necessary data is being output on the data bus 112.

Reference numeral 15 is an address buffer for taking in the address information ADR and the address parity APAR from the host computer, and outputs the address information ADR to the match selector 14 and the like. Reference numeral 16 is a parity checker to which the address parity APAR is input via the address buffer 15, and sends out a bus parity error BPER to the host computer when an error is detected in the data on the data bus 112.

Reference numeral 17 denotes a generator-side frequency detection unit having a built-in counter and a register, which receives a pulse signal corresponding to the rotation speed of the generator 30, that is, a key phasor KP and a clock signal of 1 KHz and 100 KHz, and inputs one of the key phasor KP. Generator by counting clock signals from one input to the next
Detects 30 rpm. Further, after the count number is transferred to the register, the counter is reset and the clock signal counting is restarted.

Reference numeral 18 denotes a system side frequency detection unit, which receives a rectangular wave from the second zero point detection unit 5 and a clock signal of 100 KHz, and counts the clock signals between two rising edges of the rectangular wave, The frequency on the system side is detected.

Reference numeral 19 denotes an internal phase difference angle detection unit, which receives the rectangular wave and the 100 KHz clock signal from the key phasor KP and the first zero point detection unit 4 and counts the clock signal between the key phasor KP and the rising edge of the rectangular wave. Key phasor by
Monitor the time delay from KP to interphase voltage VRS.

Reference numeral 20 denotes a system-generator phase difference detector, which receives the rectangular wave from each of the 0-point detectors 4 and 5 and a clock signal of 100 KHz, and counts the clock signals between the rising edges of both rectangular waves. Thus, the phase difference between the interphase voltage SVRS on the system side and the interphase voltage VRS on the generator side is monitored.

Each of the detection units 17 to 20 is composed of a gate, a latch, a counter, etc., and has a data input / output unit D connected to the data bus 112 and a chip select CS connected to the coincidence selector 14.

Next, the operation of the embodiment of the present invention shown in FIG. 1 will be described with reference to the waveform chart of FIG. 2 and the flow chart of FIG.

First, the generator 30 is started and the rotation speed gradually increases.
In the initial stage of starting the generator 30, when the rotation speed is low (step S ₂ ), the low-frequency (for example, 1 KHz) clock signal from the clock generator 11 is selected (step S ₂ ).
S ₃ ). At this time, the generator-side frequency detection unit 17 monitors the initial rotation speed of the generator 30 by counting the clock signals input between the pulses of the key phasor KP (step S ₁ ).

After that, when the rotation speed of the generator 30 increases and becomes equal to or higher than a predetermined rotation speed (for example, 30 Khz), the clock signal input to the generator side frequency detection unit 17 is switched to a high frequency (for example, 100 Khz) (step S ₄ ). As a result, the rotation speed of the generator 30 is accurately detected, and the rotation speed of the generator 30 is controlled so that the frequency on the generator 30 side matches the frequency on the system side (step S ₅ ) (step S ₆ ). .

On the other hand, the PLL circuit 7 uses the frequency signal f ₁ based on the interphase voltage VRS on the generator 30 side detected by the first zero-point detector 4.
Is multiplied by a predetermined frequency (for example, 128 times) and output as a frequency signal f ₂ . The gate A takes the AND of the frequency signals f ₁ and f ₂ and outputs a pulse signal based on the frequency signal f ₂ only in the first half of one cycle of the interphase voltage VRS. This pulse signal has half of 128, that is, 64 pulses only in the first half of one cycle of the interphase voltage VRS, and becomes an interrupt INT to each of the microprocessors 9 and 10 ("interrupt INT to the microprocessor INT in FIG. 2". See).

Next, a method for inputting the above-mentioned various electrical quantities to the first and second microprocessors 9 and 10 will be described.

The first microprocessor 9 generates a start signal P ₀ in response to the interrupt INT and outputs it to the analog input control circuit 6. The analog input control circuit 6 outputs the A / D conversion command signal START eight times to the A / D converter 2 in response to one start signal P ₀ (“START to A / D converter” in FIG. 2). See). As a result, the A / D converter 2 A / D-converts electrical quantities such as the interphase voltage VRS input via the analog multiplexer 1, and the A / D-converted value as a serial signal for each microprocessor 9 and Output to 10 input terminals SI.

The A / D converter outputs a completion signal Sf every time the A / D conversion operation of one electrical quantity is completed. The analog input control circuit 6 outputs the next A / D conversion command signal START according to the completion signal Sf, and causes the A / D converter 2 to perform the A / D conversion of the following electrical quantities. On the other hand, the completion signal Sf is also input to the counter 3. The counter 3 returns to the reset state each time it counts the interphase voltage SVRS which is the final input, and causes the analog multiplexer 1 to sequentially output eight electrical quantities to the A / D converter 2. . In this way, every time one interrupt INT is output, the values after A / D conversion of eight electrical quantities are input to the first and second microprocessors 9 and 10.

The first microprocessor 9 determines the effective value (ΣVRS ² ) / 64, (ΣVST ² ) of each signal for 64 sets of data (that is, 64 × 8 = 512 data) corresponding to 64 interrupts INT. ) / 64,… (ΣSVRS ² ) / 64 is calculated. Here, Σ is the total sum of 64 data corresponding to 64 sets of data.

The second microprocessor 10 has active power P and active power QP = {Σ (IR · VRS + IT · VTS)} / 64 for 64 sets of data corresponding to 64 interrupt INTs. To calculate. Here, Σ is the total sum of 64 data corresponding to 64 sets of data. The interphase voltage VTS is a value that determines the polarity of the interphase voltage VST.

This arithmetic operation is performed in the first half of one cycle of the target commercial power, and is known per se.
It is performed based on the d, q conversion processing of the phase alternating voltage and current.
Further, since the operation for taking Σ is performed every time data is input, a memory for storing the data is not required.

In order to send the 8 effective values, the active power P and the reactive power Q to the host computer, the first microprocessor 9
Is an interrupt IT from the output terminal P ₁ to the host computer.
To occur. The high-order computer sets a predetermined address value in the address buffer 15 according to this, and checks it using the parity checker 16. This address value is also checked by the match selector 14 to select either the first or second microprocessor 9 or 10.

When the first microprocessor 9 is selected, the chip selector CS of the first microprocessor 9 is activated and the effective values of various electrical quantities are output from the parallel data input / output unit D of the first microprocessor 9. The indicated data is sent to the data buffer 13. And this data is
It is sent to the host computer together with the parity generated by the parity generator 12.

The active power P and the reactive power Q obtained by the second microprocessor 10 are similarly sent to the host computer. Further, the data obtained by the detection units 17 to 20 are also sent to the computer as needed.

Further, the calculation results of these electric quantities are converted into display and control data by the host computer. This conversion operation is performed within an appropriate time included in the latter half of one cycle of the target commercial power.

Based on the result of this calculation (steps S ₇ and S ₈ ), first, the field current FI is controlled so that the interphase voltage SVRS becomes equal to the interphase voltage VRS (step S ₉ ), and then between the grid and the generator 30. after the phase difference is 0 controlled to be close to (step S ₁₀₎ (step S _11), turning on the power generator 30 to the system side (step S _12). After that, while checking whether the internal phase difference angle is within the allowable range (steps S ₁₃ and S ₁₄ ), the electric power quantity is measured (step S ₁₅ ) and displayed (step S ₁₆ ).

Thus, the pulse frequency (frequency signal f ₂ ) is set to a predetermined multiple (128 times) of the input frequency (frequency signal f ₁ ), and the pulse signal f ₂ always divides the waveform of the input signal f ₁ into predetermined equal parts (128). Even if the input frequency (f ₁ ) changes, the same phase position of the waveform of the frequency signal f ₁ can be sampled at all times, and highly accurate data sampling can be performed. The pulse frequency (f ₂ ) is not constant but changes according to the input frequency (f ₁ ). This is because accurate measurement cannot be performed when the pulse frequency (f ₂ ) is constant and the sampling phase position differs due to a change in the input frequency (f ₁ ).

Also, by inputting the pulse frequency f ₂ to the interrupt (ITN) for each microprocessor 9 and 10, the A / D
By synchronizing the timing of data acquisition from the converter 2 (S0) and commonly inputting the basic clock and the serial clock to the respective input sections (CLK) and (SCK), the respective microprocessors 9 and 10 can perform the above-mentioned operation. Data can be acquired simultaneously, and high-speed data sampling can be supported.

Further, as in the above-described calculation formula, the instantaneous values of the active power P and the reactive power Q are simply calculated based on the interphase voltages VRS and VTS and the phase currents IR and IT, so that high-speed measurement is possible.

Due to the characteristics of the signal input (hardware) to the microprocessors 9 and 10 and the characteristics of the calculation formula (software) for the active power P and the reactive power Q, the input frequency of the pulse frequency (f ₂ = 128f ₁ ) The 64 instantaneous values for half a cycle are calculated at high speed and with high accuracy. Further, since each instantaneous value can be calculated at high speed, these instantaneous values can be added and stored in the memory, and a large amount of measurement data buffer is not required.

In addition, it is the generator 30 that measures the interphase voltage SVRS on the grid side.
Is to obtain the necessary information when the power is input to the system side, the calculation of the effective value of the interphase voltage is not limited to the system side,
Various effective values including the generator 30 side are calculated.

Further, although one A / D converter 2 is used in the above-mentioned embodiment, it is also possible to use two A / D converters 2. By doing so, the speed and accuracy of data processing can be further improved.

[Effects of the Invention] As described above, according to the present invention, the sample rate for capturing data for calculation is set high, and this calculation is digitally processed by using a microprocessor to obtain a highly accurate calculation result. Since it does not require a memory for quickly obtaining sampling data and storing sampling data, an electrical quantity detection processing device that is extremely effective not only for simple measurement but also for real-time detection of power generator 30 closing control, instantaneous blackout, etc. There is an effect to be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention. FIG. 2 is a waveform diagram of each signal in one embodiment of the present invention. FIG. 3 is a flow chart showing the operation of the embodiment of the present invention. 1 …… Analog multiplexer 2 …… A / D converter 6 …… Analog input control circuit 7 …… PLL circuit 9 …… First microprocessor 10 …… Second microprocessor 30 …… Generator f ₁ … Frequency Signal f ₂ ... Frequency signal (pulse signal) In the drawings, the same reference numerals indicate the same or corresponding parts.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Ryosuke Taniguchi 6-14 Maruo-cho, Nagasaki City, Nagasaki Prefecture Nagasaki Manufacturing Co., Ltd. (56) Reference JP-A-54-1667 (JP, A) 57-137863 (JP, A)

Claims (1)

[Claims] 1. An analog multiplexer for taking in various electrical quantities of three-phase alternating current and sequentially outputting them, and A for A / D converting an output signal of the analog multiplexer.
/ D converter, a PLL circuit that generates a pulse signal having a frequency that is a predetermined multiple of the generator-side frequency, and that receives the pulse signal as an interrupt signal, and a half-wave of one cycle of the generator-side frequency The A / D-converted electrical quantities are taken in to calculate the three types of interphase voltage on the generator side, the three types of phase current and the effective value of the field current, and the effective side voltage of one type on the system side. A first microprocessor for calculating a value; and receiving the pulse signal as an interrupt signal and taking in the A / D-converted electrical quantities in a half-wave of one cycle of the generator-side frequency. A second microprocessor that performs an operation for obtaining the active power and the reactive electrode on the generator side based on the d, q conversion theory, and is activated by either one of the first and second microprocessors, and Electrical quantities detection processing apparatus characterized by comprising an analog input control circuit that subjected to the A / D converter to the electric quantities to sequentially A / D conversion operation was taken in a predetermined order.