JPS6281054A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6281054A JPS6281054A JP60222115A JP22211585A JPS6281054A JP S6281054 A JPS6281054 A JP S6281054A JP 60222115 A JP60222115 A JP 60222115A JP 22211585 A JP22211585 A JP 22211585A JP S6281054 A JPS6281054 A JP S6281054A
- Authority
- JP
- Japan
- Prior art keywords
- drain
- gate
- source
- circular
- arranged around
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 9
- 230000005669 field effect Effects 0.000 claims description 5
- 238000009792 diffusion process Methods 0.000 abstract description 4
- 230000002542 deteriorative effect Effects 0.000 abstract 2
- 230000001133 acceleration Effects 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
- 238000007363 ring formation reaction Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 230000006866 deterioration Effects 0.000 description 2
- 241000255925 Diptera Species 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装ぎに関し、特にMOS型の半導体装置
に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a MOS type semiconductor device.
従来、二つのトランジスタの特性の整合(以下マツチン
グという)を要するトランジスタは、第5図に示すよう
に、多角形(主に四角形)の形状を成している。しかし
、拡散工程中、例えば目ずれなどによってイ踵徊鈷二つ
のトランジスタの相対位置関係の維持(以下相対性とい
う)を要するトランジスタの一方だけが拡散層、あるい
は配線にずれを生じ、他とマツチングが取れなくなる場
合がある。これを防ぐため、マツチングを要するトラン
ジスタはウェーハに対してチャネル幅を同方向にし、か
つ近距離に配置される工夫がなされている。Conventionally, transistors that require matching (hereinafter referred to as matching) of the characteristics of two transistors have a polygonal (mainly rectangular) shape, as shown in FIG. However, during the diffusion process, due to misalignment, for example, one of the transistors, which requires maintaining the relative positional relationship between the two transistors (hereinafter referred to as relativity), may be misaligned in the diffusion layer or wiring, causing mismatching with the other transistors. You may not be able to get it. To prevent this, the transistors that require matching have their channel widths in the same direction with respect to the wafer, and are arranged close to each other.
上述した従来の形状のトランジスタではマツチングを要
する場合、トランジスタのチップに対するX、y座標を
揃えるために、レイアウト設計期間の長網化及びチェッ
ク時の工数増大が伴うという欠点がある。When matching is required for the above-mentioned conventionally shaped transistors, there is a drawback that the layout design period becomes longer and the number of man-hours for checking increases in order to align the X and y coordinates of the transistors with respect to the chip.
又近年、動作速度の高速化の要求が高まる状況下で従来
の形状のトランジスタではドレインでの接合容量が下げ
にくく、高速化を妨げるという欠点がある。In addition, in recent years, under the increasing demand for higher operating speeds, conventionally shaped transistors have the disadvantage that it is difficult to reduce the junction capacitance at the drain, which hinders higher speeds.
本発明の目的はドレイン側の接合容量を下げ、高速化を
図り、かつトランジスタのソース、ゲートの目ずれによ
る特性の整合性の悪化を少くした半導体装置を提供する
ことにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device which reduces junction capacitance on the drain side, increases speed, and reduces deterioration in characteristic matching due to misalignment between the source and gate of a transistor.
本発明の半導体装置は、中央に円形のドレインを配置し
、該ドレインの周囲に同心円で環状にゲートを配置し、
該ゲートの周囲に環状にソースを配置した電界効果トラ
ンジスタを備えることにより構成される。The semiconductor device of the present invention has a circular drain arranged in the center, a gate arranged concentrically around the drain in an annular shape,
It is constructed by including a field effect transistor in which a source is arranged in an annular manner around the gate.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第1図(a)、(b)は本発明の第1の実施例の平面図
及びその等価回路図である。FIGS. 1(a) and 1(b) are a plan view and an equivalent circuit diagram of a first embodiment of the present invention.
この実施例は本発明をCMO8型O8回路に適用したも
のであり、中央にドレイン電極1を配置し、ドレインの
周囲に環状にゲート電極2を配置し、ゲート1極の周囲
に環状にソース電極3を配置して電界効果トランジスタ
を作ったものである。In this embodiment, the present invention is applied to a CMO8 type O8 circuit, in which a drain electrode 1 is arranged in the center, a gate electrode 2 is arranged in a ring shape around the drain, and a source electrode is arranged in a ring shape around the gate 1 pole. A field effect transistor was created by arranging 3.
尚% 4はPウェル、5はコンタクトである。Note that %4 is a P well and %5 is a contact.
この構造にすると、ソース領域に対して、ドレイン領域
は小さくなり、接合容量は小さくなる。With this structure, the drain region becomes smaller than the source region, and the junction capacitance becomes smaller.
次に数値を仮定して説明する。ドレイン領域だけに注目
した場合、第6図に示したドレイン寸法X、yをそれぞ
れ10μmとすると、ドレイン面積は10μmX10μ
m−100μm2 となる。ここでXはチャネル幅、y
はパターニングより寸法が制限されているドレイン幅で
ある。第1図に示す第1の実施例によるトランジスタ形
状では、yは同一とするとドレイン面積は(10/2)
”π中78.5μm2となり、接合容量はドレイン面積
と比例するため、約22%も接合容量を低減させる事が
可能である。Next, an explanation will be given assuming numerical values. When focusing only on the drain region, if the drain dimensions X and y shown in Figure 6 are each 10 μm, the drain area is 10 μm x 10 μm.
m-100 μm2. where X is the channel width, y
is the drain width whose dimension is limited by the patterning. In the transistor shape according to the first embodiment shown in FIG. 1, if y is the same, the drain area is (10/2)
Since the junction capacitance is proportional to the drain area, it is possible to reduce the junction capacitance by about 22%.
更に、チャネル幅は2πr−2π×5中31.4μm
より従来に比ベチャネル幅が長くでき、回路動作上有効
であると考えられる。Furthermore, the channel width is 31.4 μm in 2πr−2π×5
The channel width can be made longer compared to the conventional method, which is considered to be effective in terms of circuit operation.
第2図(a) 、 (b)は本発明の第2の実施例の平
面面
図及びその等価回畝ある。FIGS. 2(a) and 2(b) show a plan view of a second embodiment of the present invention and its equivalent ridge.
中央にドレイン電極lを配置し、ドレインの周囲に環状
にゲー[11極2を配置し、ゲート電極の周囲に環状に
ソース電極3を配置し、て霊界効果トランジスタを作る
。この第2の実施例はより小さいチャネル幅寸法に有効
である。A drain electrode 1 is arranged in the center, a gate electrode 11 is arranged in a ring shape around the drain, and a source electrode 3 is arranged in a ring shape around the gate electrode to form a spiritual effect transistor. This second embodiment is useful for smaller channel width dimensions.
第3図(a”)、(b)は本発明の第3の実施例の平面
図及びその等価回路図である。FIGS. 3(a) and 3(b) are a plan view and an equivalent circuit diagram of a third embodiment of the present invention.
この実施例は、本発明を差動増幅器に適用したものであ
り、中央にドレイン電極lを配置し、ドレインの周囲に
環状にゲート電極2を配置し、ゲート電極の周囲に環状
にソース電極3を配置して電界効果トランジスタを作っ
たものである。In this embodiment, the present invention is applied to a differential amplifier, in which a drain electrode l is arranged in the center, a gate electrode 2 is arranged in a ring shape around the drain, and a source electrode 3 is arranged in a ring shape around the gate electrode. A field effect transistor was created by arranging the .
この実施例は、目ずれによってトランジスタ同志の拡散
層や配線等のマツチングがとれなくなったり、付加容量
が増えるのを防ぐ効果がある0本発明によりレイアウト
設計時における設計工数の短縮が可能となるばかりか、
非相対性によるミスが減少し、それに伴りてチェック工
数を省く事も可能である。又、ここではマツチングを要
するトランジスタのソース領域を共通にし、トランジス
タ同志を接合させて縮小化を図っているが勿論、個々を
切離してレイアウトしてもこの形状の場合、方向を考慮
せずに相対性がとれる。This embodiment has the effect of preventing mismatching of the diffusion layers and wiring between transistors and an increase in additional capacitance due to alignment misalignment.The present invention not only makes it possible to reduce design man-hours during layout design. mosquito,
Mistakes due to non-relativity are reduced, and the number of checking steps can be reduced accordingly. In addition, here, the source regions of the transistors that require matching are made common, and the transistors are joined together to reduce the size, but of course, even if the individual transistors are separated and laid out, in this shape, it will be difficult to match them relative to each other without considering the direction. You can get your sense of nature.
この実施fIIFi2組の差動増幅器をたすき掛に配置
したものであり、中央にドレイン1極lを配置し、ドレ
インの周囲に環状にゲート電極2を配置し、ゲート電極
の周囲に環状にソース1極3を配置して電界効果トラン
ジスタを作ったものである。This implementation fIIFi has two sets of differential amplifiers arranged crosswise, with one drain pole l arranged in the center, a gate electrode 2 arranged annularly around the drain, and a source 1 arranged annularly around the gate electrode. A field effect transistor is made by arranging poles 3.
この実施例は、差動増幅器の精度をさらに高める場合に
有効である。This embodiment is effective in further increasing the accuracy of the differential amplifier.
この実施例はマツチングを要するチャネル幅が3=1の
2個のトランジスタのドレイン領域を共通にしたもので
ある。このドレイン電極の周囲にゲート電極2.ソース
電極3を設ける。In this embodiment, two transistors having a channel width of 3=1 which require matching have a common drain region. A gate electrode 2. is formed around this drain electrode. A source electrode 3 is provided.
通常、寸法の異なったトランジスタを配置する場合、ソ
ース又はドレイン領域を共通にし、トランジスタ寸法の
縮小化を図っていたが本発明により複数の異った寸法の
トランジスタを1個の円形の中に組み込む事により、ト
ランジスタ寸法をさらに縮小させる事が可能であり、し
かも接合容量を減少させる事ができる。この場合、各ト
ランジスタのチャネル幅を弧とした中心角の比がトラン
ジスタの面積比に相当する。Normally, when arranging transistors with different dimensions, the source or drain region is shared in order to reduce the transistor dimensions, but with the present invention, multiple transistors with different dimensions can be integrated into a single circle. As a result, the transistor dimensions can be further reduced and the junction capacitance can be reduced. In this case, the ratio of central angles with the channel width of each transistor as an arc corresponds to the area ratio of the transistors.
以上説明したように本発明は、ドレインを中央にしてゲ
ート電極、ソース電極を環状に設けるようにしたので、
ドレイン側の容量を減少させ、高速化を可能とし、かつ
目ずれによる特性の整合性の悪化を少くした半導体装置
が得られるという効果がある。As explained above, in the present invention, the gate electrode and the source electrode are provided in an annular shape with the drain in the center.
This has the effect of reducing the capacitance on the drain side, making it possible to increase the speed, and providing a semiconductor device with less deterioration in characteristic matching due to misalignment.
第1図(a)、(b)乃至第5図(a) 、 (b)は
それぞれ本発明の第1乃至第5の実施例の平面図及び等
価回路図、第6図(a) 、 (b)は従来のCMO8
反転回路の一例の平面図及び等価回路図である。
l・・・・・・ドレイン電極、2・・・・・・ゲート電
極、3・・・・・・ソース電極、4・・・・・・Pウェ
ル、5・・・・・・コンタクト。
□<l’L:、、−’□
第2v3
第3図
(b)1(a), (b) to 5(a), (b) are plan views and equivalent circuit diagrams of the first to fifth embodiments of the present invention, and FIG. 6(a), ( b) is the conventional CMO8
FIG. 2 is a plan view and an equivalent circuit diagram of an example of an inversion circuit. 1...Drain electrode, 2...Gate electrode, 3...Source electrode, 4...P well, 5...Contact. □<l'L:,,-'□ 2nd v3 Figure 3(b)
Claims (2)
囲に同心円で環状にゲートを配置し、該ゲートの周囲に
環状にソースを配置した電界効果トランジスタを有する
ことを特徴とする半導体装置。(1) A semiconductor device comprising a field effect transistor in which a circular drain is arranged in the center, a gate is arranged in a concentric ring around the drain, and a source is arranged in a ring around the gate.
る開環状である特許請求の範囲第(1)項記載の半導体
装置。(2) The semiconductor device according to claim (1), wherein the source has an open ring shape with a cutout portion aligned with the central angle of the concentric circles.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60222115A JPS6281054A (en) | 1985-10-04 | 1985-10-04 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60222115A JPS6281054A (en) | 1985-10-04 | 1985-10-04 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6281054A true JPS6281054A (en) | 1987-04-14 |
Family
ID=16777383
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP60222115A Pending JPS6281054A (en) | 1985-10-04 | 1985-10-04 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6281054A (en) |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1999021230A1 (en) * | 1997-10-22 | 1999-04-29 | Siemens Aktiengesellschaft | Field effect semiconductor component |
EP0982777A1 (en) * | 1998-08-25 | 2000-03-01 | International Business Machines Corporation | Wordline driver circuit using ring-shaped devices |
KR20030027653A (en) * | 2001-09-27 | 2003-04-07 | 미쓰비시덴키 가부시키가이샤 | Semiconductor device |
DE10203152C1 (en) * | 2002-01-28 | 2003-10-23 | Infineon Technologies Ag | Semiconductor memory device has driver transistor pair for each memory module and coupling transistor for coupling adjacent memory row selection lines |
KR100520624B1 (en) * | 1996-11-28 | 2005-12-21 | 마츠시타 덴끼 산교 가부시키가이샤 | Semiconductor device, method of designing the same and semiconductor integrated circuit device |
EP1863088A2 (en) * | 2006-06-02 | 2007-12-05 | NEC Electronics Corporation | FET semiconductor device with partial annular gate electrodes |
JP2008091547A (en) * | 2006-09-29 | 2008-04-17 | Fujitsu Ltd | Semiconductor device |
JP4836796B2 (en) * | 2003-10-14 | 2011-12-14 | セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー | Power supply system suppression method and apparatus and structure thereof |
JP2012069759A (en) * | 2010-09-24 | 2012-04-05 | Renesas Electronics Corp | Semiconductor device |
WO2024066745A1 (en) * | 2022-09-29 | 2024-04-04 | 华润微电子(重庆)有限公司 | Hemt device and manufacturing method therefor |
-
1985
- 1985-10-04 JP JP60222115A patent/JPS6281054A/en active Pending
Cited By (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100520624B1 (en) * | 1996-11-28 | 2005-12-21 | 마츠시타 덴끼 산교 가부시키가이샤 | Semiconductor device, method of designing the same and semiconductor integrated circuit device |
WO1999021230A1 (en) * | 1997-10-22 | 1999-04-29 | Siemens Aktiengesellschaft | Field effect semiconductor component |
KR100375885B1 (en) * | 1998-08-25 | 2003-03-15 | 인터내셔널 비지네스 머신즈 코포레이션 | Wordline driver circuit using ring-shaped devices |
US6236258B1 (en) | 1998-08-25 | 2001-05-22 | International Business Machines Corporation | Wordline driver circuit using ring-shaped devices |
EP0982777A1 (en) * | 1998-08-25 | 2000-03-01 | International Business Machines Corporation | Wordline driver circuit using ring-shaped devices |
KR20030027653A (en) * | 2001-09-27 | 2003-04-07 | 미쓰비시덴키 가부시키가이샤 | Semiconductor device |
DE10203152C1 (en) * | 2002-01-28 | 2003-10-23 | Infineon Technologies Ag | Semiconductor memory device has driver transistor pair for each memory module and coupling transistor for coupling adjacent memory row selection lines |
JP4836796B2 (en) * | 2003-10-14 | 2011-12-14 | セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー | Power supply system suppression method and apparatus and structure thereof |
EP1863088A2 (en) * | 2006-06-02 | 2007-12-05 | NEC Electronics Corporation | FET semiconductor device with partial annular gate electrodes |
US7675089B2 (en) | 2006-06-02 | 2010-03-09 | Nec Electronics Corporation | Semiconductor device |
EP1863088A3 (en) * | 2006-06-02 | 2010-11-24 | Renesas Electronics Corporation | FET semiconductor device with partial annular gate electrodes |
JP2008091547A (en) * | 2006-09-29 | 2008-04-17 | Fujitsu Ltd | Semiconductor device |
JP2012069759A (en) * | 2010-09-24 | 2012-04-05 | Renesas Electronics Corp | Semiconductor device |
WO2024066745A1 (en) * | 2022-09-29 | 2024-04-04 | 华润微电子(重庆)有限公司 | Hemt device and manufacturing method therefor |
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