JPS6281054A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the junction capacity on drain side for acceleration the circuit operation while preventing matching in characteristics from deteriorating due to deviation of source.drain of transistor by a method wherein, within an MOS type semiconductor device, a drain is arranged in the central part and then a circular gate is concentrically arranged around the drain while circular sources are arranged around the gate. CONSTITUTION:A drain electrode 1 is arranged at the central part and then a circular gate electrode 2 is arranged around the drain electrode 1 while circular source electrodes 3 are further arranged around the gate electrode 2 in a ring formation. In such a constitution, th drain region is made smaller than the source region so that the junction capacity propertional to the drain may be reduced. Besides, the matching of transistors with each other in diffusion layer of wirings etc. is prevented from deteriorating due to deviation also preventing the added capacity from increasing. Furthermore, the channel width can be extended making circuit operation more effective.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a MOS type semiconductor device.

[Conventional technology]

Conventionally, transistors that require matching (hereinafter referred to as matching) of the characteristics of two transistors have a polygonal (mainly rectangular) shape, as shown in FIG. However, during the diffusion process, due to misalignment, for example, one of the transistors, which requires maintaining the relative positional relationship between the two transistors (hereinafter referred to as relativity), may be misaligned in the diffusion layer or wiring, causing mismatching with the other transistors. You may not be able to get it. To prevent this, the transistors that require matching have their channel widths in the same direction with respect to the wafer, and are arranged close to each other.

[Problem that the invention seeks to solve]

When matching is required for the above-mentioned conventionally shaped transistors, there is a drawback that the layout design period becomes longer and the number of man-hours for checking increases in order to align the X and y coordinates of the transistors with respect to the chip.

In addition, in recent years, under the increasing demand for higher operating speeds, conventionally shaped transistors have the disadvantage that it is difficult to reduce the junction capacitance at the drain, which hinders higher speeds.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device which reduces junction capacitance on the drain side, increases speed, and reduces deterioration in characteristic matching due to misalignment between the source and gate of a transistor.

[Means for solving problems]

The semiconductor device of the present invention has a circular drain arranged in the center, a gate arranged concentrically around the drain in an annular shape,
It is constructed by including a field effect transistor in which a source is arranged in an annular manner around the gate.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIGS. 1(a) and 1(b) are a plan view and an equivalent circuit diagram of a first embodiment of the present invention.

In this embodiment, the present invention is applied to a CMO8 type O8 circuit, in which a drain electrode 1 is arranged in the center, a gate electrode 2 is arranged in a ring shape around the drain, and a source electrode is arranged in a ring shape around the gate 1 pole. A field effect transistor was created by arranging 3.

Note that %4 is a P well and %5 is a contact.

With this structure, the drain region becomes smaller than the source region, and the junction capacitance becomes smaller.

Next, an explanation will be given assuming numerical values. When focusing only on the drain region, if the drain dimensions X and y shown in Figure 6 are each 10 μm, the drain area is 10 μm x 10 μm.
m-100 μm2. where X is the channel width, y
is the drain width whose dimension is limited by the patterning. In the transistor shape according to the first embodiment shown in FIG. 1, if y is the same, the drain area is (10/2)
Since the junction capacitance is proportional to the drain area, it is possible to reduce the junction capacitance by about 22%.

Furthermore, the channel width is 31.4 μm in 2πr−2π×5
The channel width can be made longer compared to the conventional method, which is considered to be effective in terms of circuit operation.

FIGS. 2(a) and 2(b) show a plan view of a second embodiment of the present invention and its equivalent ridge.

A drain electrode 1 is arranged in the center, a gate electrode 11 is arranged in a ring shape around the drain, and a source electrode 3 is arranged in a ring shape around the gate electrode to form a spiritual effect transistor. This second embodiment is useful for smaller channel width dimensions.

FIGS. 3(a) and 3(b) are a plan view and an equivalent circuit diagram of a third embodiment of the present invention.

In this embodiment, the present invention is applied to a differential amplifier, in which a drain electrode l is arranged in the center, a gate electrode 2 is arranged in a ring shape around the drain, and a source electrode 3 is arranged in a ring shape around the gate electrode. A field effect transistor was created by arranging the .

This embodiment has the effect of preventing mismatching of the diffusion layers and wiring between transistors and an increase in additional capacitance due to alignment misalignment.The present invention not only makes it possible to reduce design man-hours during layout design. mosquito,
Mistakes due to non-relativity are reduced, and the number of checking steps can be reduced accordingly. In addition, here, the source regions of the transistors that require matching are made common, and the transistors are joined together to reduce the size, but of course, even if the individual transistors are separated and laid out, in this shape, it will be difficult to match them relative to each other without considering the direction. You can get your sense of nature.

This implementation fIIFi has two sets of differential amplifiers arranged crosswise, with one drain pole l arranged in the center, a gate electrode 2 arranged annularly around the drain, and a source 1 arranged annularly around the gate electrode. A field effect transistor is made by arranging poles 3.

This embodiment is effective in further increasing the accuracy of the differential amplifier.

In this embodiment, two transistors having a channel width of 3=1 which require matching have a common drain region. A gate electrode 2. is formed around this drain electrode. A source electrode 3 is provided.

Normally, when arranging transistors with different dimensions, the source or drain region is shared in order to reduce the transistor dimensions, but with the present invention, multiple transistors with different dimensions can be integrated into a single circle. As a result, the transistor dimensions can be further reduced and the junction capacitance can be reduced. In this case, the ratio of central angles with the channel width of each transistor as an arc corresponds to the area ratio of the transistors.

〔Effect of the invention〕

As explained above, in the present invention, the gate electrode and the source electrode are provided in an annular shape with the drain in the center.
This has the effect of reducing the capacitance on the drain side, making it possible to increase the speed, and providing a semiconductor device with less deterioration in characteristic matching due to misalignment.

[Brief explanation of drawings]

1(a), (b) to 5(a), (b) are plan views and equivalent circuit diagrams of the first to fifth embodiments of the present invention, and FIG. 6(a), ( b) is the conventional CMO8
FIG. 2 is a plan view and an equivalent circuit diagram of an example of an inversion circuit. 1...Drain electrode, 2...Gate electrode, 3...Source electrode, 4...P well, 5...Contact. □<l'L:,,-'□ 2nd v3 Figure 3(b)

Claims (2)

[Claims] (1) A semiconductor device comprising a field effect transistor in which a circular drain is arranged in the center, a gate is arranged in a concentric ring around the drain, and a source is arranged in a ring around the gate. (2) The semiconductor device according to claim (1), wherein the source has an open ring shape with a cutout portion aligned with the central angle of the concentric circles.