JPS628034B2 - - Google Patents

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Publication number
JPS628034B2
JPS628034B2 JP56023959A JP2395981A JPS628034B2 JP S628034 B2 JPS628034 B2 JP S628034B2 JP 56023959 A JP56023959 A JP 56023959A JP 2395981 A JP2395981 A JP 2395981A JP S628034 B2 JPS628034 B2 JP S628034B2
Authority
JP
Japan
Prior art keywords
film
bonding pad
present
silicon
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56023959A
Other languages
Japanese (ja)
Other versions
JPS57138165A (en
Inventor
Mototaka Kamoshita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP56023959A priority Critical patent/JPS57138165A/en
Publication of JPS57138165A publication Critical patent/JPS57138165A/en
Publication of JPS628034B2 publication Critical patent/JPS628034B2/ja
Granted legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3192—Multilayer coating
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】 本発明は半導体装置の製造方法に係わり、特に
高湿度に耐え得る該半導体装置及びその製造方法
に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a semiconductor device that can withstand high humidity and a method for manufacturing the same.

従来、半導体装置の耐湿性を向上させるために
は、例えば昭和53年11月27日に日経マグロヒル社
発行「日経エレクトロニクス」誌、第200号、173
頁からの特集記事「LSIの信頼性を向上させる半
導体プロセス技術−パシベーシヨン技術を中心に
見る−」にて、特に第176〜177頁の表１にまとめ
られている通り、チツプ上の表面保護膜を高耐湿
性材にする方法などがとられている。例えば同表
のように、スパツタ法で付着せしめた二酸化硅素
膜とか、プラズマ気相反応で付着させた窒化硅素
膜等が該高耐湿性材料として知られている。 Conventionally, in order to improve the moisture resistance of semiconductor devices, for example, "Nikkei Electronics" magazine published by Nikkei Maguro-Hill Co., Ltd. on November 27, 1973, No. 200, 173
As summarized in Table 1 on pages 176-177 in the special feature article "Semiconductor process technology to improve LSI reliability - Focusing on passivation technology", the surface protection film on the chip Methods such as making it into a highly moisture-resistant material are being taken. For example, as shown in the same table, a silicon dioxide film deposited by a sputtering method, a silicon nitride film deposited by a plasma vapor phase reaction, etc. are known as the highly moisture resistant material.

然るにこのような高耐湿材料をチツプの表面保
護膜に使用してもチツプから外部へリード線を接
続するボンデイングパツド部は金属配線層が露出
されているので、ボンデイングパツド部の耐湿性
向上にはつながらない。そのため一般には湿度に
対しては無防備なモールド材料を水分が透湿し、
水分とボンデイングパツド部を構成する金属とが
反応し、断線などの事故に至るという欠点があつ
た。 However, even if such a highly moisture-resistant material is used for the surface protection film of the chip, the metal wiring layer is exposed in the bonding pad area that connects the lead wires from the chip to the outside, so the moisture resistance of the bonding pad area cannot be improved. It doesn't lead to. Therefore, moisture permeates through the mold material, which is generally unprotected against humidity.
The drawback was that moisture reacted with the metal that made up the bonding pad, leading to accidents such as wire breakage.

本発明の目的はこのような欠点を解消し、耐湿
性の高い半導体装置の製造方法を提供することに
ある。 An object of the present invention is to eliminate such drawbacks and provide a method for manufacturing a semiconductor device with high moisture resistance.

本発明の構成は、ボンデイングパツド金属上に
も透湿性の低い樹脂を薄く付着せしめた構造を特
徴とする。更に又、本発明の特徴は、ボンデイン
グパツド金属上に薄く透湿性の低い膜を塗布し、
その膜を突き破つてリード線を接続する工程を含
むことにある。 The structure of the present invention is characterized by a structure in which a resin with low moisture permeability is thinly adhered also on the bonding pad metal. Furthermore, the present invention is characterized by coating a thin film with low moisture permeability on the bonding pad metal,
The method includes the step of piercing the membrane and connecting the lead wire.

更に又、本発明は該低透湿膜としてポリイミド
樹脂膜、あるいはそのポリイミドと半導体チツプ
との接着を強化するためのカプラー材として良く
用いられる遷移金属の有機化合物などを用いた半
導体装置である。 Furthermore, the present invention is a semiconductor device using, as the low moisture permeability film, a polyimide resin film, or an organic compound of a transition metal, which is often used as a coupler material to strengthen the adhesion between the polyimide and a semiconductor chip.

本発明の原理はボンデイングパツド金属上に数
100Åの低透湿性の膜を塗布すると耐湿性が著し
く改善されるという新規な発見に基づく。 The principle of the present invention is that several bonding pads are placed on the metal.
Based on the novel discovery that applying a 100 Å low moisture permeability membrane significantly improves moisture resistance.

本発明により、半導体装置の耐湿性に顕著な改
善が見られる。例えば、通常のモールド樹脂封止
したシリコンゲート、アルミニウム配線によるシ
リコンプレーナ集積回路にて、本発明の適用によ
り、温度85℃、湿度85％の環境試験で従来より約
200時間程度耐用時間が伸びるようになつた。 According to the present invention, significant improvement can be seen in the moisture resistance of semiconductor devices. For example, in a silicon planar integrated circuit with a silicon gate sealed with a regular molded resin and aluminum wiring, by applying the present invention, an environmental test at a temperature of 85 degrees Celsius and a humidity of 85% was performed to
The service life has increased by about 200 hours.

次に本発明の実施例を図面を参照して説明す
る。先ず比較のため、第１図に従来のシリコン集
積回路の一部の断面図を示した。即ち従来品では
例えばシリコン基板１０１に所望のpn接合１０
２を形成した後、絶縁膜１０３を介して電極配線
材料を付着し選択的に加工して配線１０４を形成
し、然る後に保護膜、例えばプラズマ中での化学
反応を利用した気相成長法による窒化シリコン膜
１０５を付着させる。その後、配線１０４と外部
端子との接続部であるボンデイングパツド部１０
６の上の窒化硅素膜１０５を選択的に除去し、そ
こにリード線１０７を接続する。この従来品では
ボンデイングパツド部１０６の上には保護膜が無
いので、外部からの水分と、配線材料との反応が
起こり易い。それに対し第２図は本発明の一実施
例の工程を示す断面図である。即ち、第２図Ａの
通り通常の如くｐ型シリコン基板２０１を用意
し、その上に絶縁膜、例えば二酸化シリコン膜２
０２を形成し、選択的に孔をあけてｎ型不純物を
添加し、pn接合２０３を形成した後、酸化を続
け、ｎ型不純物を添加した領域のシリコン基板２
０１の表面を再度二酸化シリコン膜２０４で被覆
する。然る後に所望のコンタクト用孔２０５を開
け、電極配線材料、例えばアルミニウムを蒸着法
などで付着せしめ、加工し、配線２０６を形成
し、その後プラズマ法により化学的なシランとア
ンモニアの気相成長により窒化シリコン膜２０７
を形成し、ボンデイングパツド部２０８の上の窒
化シリコン膜２０７を除去する。次いで第２図Ｂ
のようにカプラー剤としても使われる有機遷移金
属化合物、例えば有機クロムを約300Å程度塗布
した後ポリイミド２１０をつける。その後ポリイ
ミド２１０をヒドラジンを用いて所望の形に加工
し、ボンデイングパツド部２０８の上のポリイミ
ド２１０を除去し、カプラー剤の有機クロム膜２
０９を残した状態のチツプに、その有機クロム膜
２０９を突き破つてリード線２１１をボンデイン
グする。この状態の終了図が第２図Ｂである。こ
こでは第１図の場合と異なりボンデイングパツド
部２０８のアルミニウム上にカプラー剤の有機ク
ロム膜２０９が残つている。 Next, embodiments of the present invention will be described with reference to the drawings. First, for comparison, FIG. 1 shows a cross-sectional view of a part of a conventional silicon integrated circuit. That is, in conventional products, for example, a desired pn junction 10 is formed on a silicon substrate 101.
2, an electrode wiring material is deposited through an insulating film 103 and selectively processed to form a wiring 104, and then a protective film is formed, for example, by vapor phase growth using a chemical reaction in plasma. A silicon nitride film 105 is deposited. After that, a bonding pad part 10 which is a connection part between the wiring 104 and an external terminal
The silicon nitride film 105 above 6 is selectively removed, and a lead wire 107 is connected thereto. Since this conventional product does not have a protective film on the bonding pad portion 106, a reaction between moisture from the outside and the wiring material is likely to occur. On the other hand, FIG. 2 is a sectional view showing the steps of an embodiment of the present invention. That is, as shown in FIG. 2A, a p-type silicon substrate 201 is prepared in the usual manner, and an insulating film, for example, a silicon dioxide film 2 is formed on it.
After forming a pn junction 203 by selectively forming a hole and doping an n-type impurity, oxidation is continued to remove the silicon substrate 2 in the area to which the n-type impurity has been added.
The surface of 01 is again covered with a silicon dioxide film 204. Thereafter, a desired contact hole 205 is made, and an electrode wiring material, such as aluminum, is deposited by vapor deposition or the like and processed to form a wiring 206. Thereafter, the wiring 206 is formed by chemical vapor deposition of silane and ammonia using a plasma method. Silicon nitride film 207
is formed, and the silicon nitride film 207 on the bonding pad portion 208 is removed. Then Figure 2B
After applying an organic transition metal compound, such as organic chromium, which is also used as a coupler agent, to a thickness of about 300 Å, polyimide 210 is applied. Thereafter, the polyimide 210 is processed into a desired shape using hydrazine, the polyimide 210 on the bonding pad portion 208 is removed, and the organic chromium film 2 of the coupler agent is removed.
Lead wires 211 are bonded to the chip with 0.09 remaining by penetrating the organic chromium film 209. A final diagram of this state is shown in FIG. 2B. Here, unlike the case in FIG. 1, an organic chromium film 209 of a coupler remains on the aluminum of the bonding pad portion 208.

第３図は本発明の実施例による85℃での湿度85
％に於ける環境試験後でのpn接合の逆方向電流
を測定したものである。従来品Ａでは約100時間
後に逆方向電流が増加していたが、本発明品Ｂに
よると約300〜350時間後になつてやつと増加し始
めており、耐湿性の向上が著しい。 Figure 3 shows humidity 85 at 85°C according to an embodiment of the present invention.
This is a measurement of the reverse current of the pn junction after an environmental test at 50%. In the conventional product A, the reverse current increased after about 100 hours, but in the product B of the present invention, it gradually started to increase after about 300 to 350 hours, indicating a remarkable improvement in moisture resistance.

以上本発明の実施例としてシリコンの集積回路
について記述したが、本発明はシリコン素子のみ
でなく砒化ガリウムなど他の半導体素子でも有効
である。又、本実施例では配線材料としてアルミ
ニウムを主に説明して来たが、本発明は単にアル
ミニウム製ボンデイングパツドのみでなく、他の
水分と反応し易い金属製のボンデイングパツドを
持つ半導体装置にも適用できる。更に又、本発明
の低透湿性膜としてポリイミド系以外の膜でもよ
い。 Although a silicon integrated circuit has been described as an embodiment of the present invention, the present invention is effective not only for silicon devices but also for other semiconductor devices such as gallium arsenide. Furthermore, in this embodiment, aluminum has been mainly explained as the wiring material, but the present invention is not limited to simply bonding pads made of aluminum, but also applies to semiconductor devices having bonding pads made of other metals that easily react with moisture. It can also be applied to Furthermore, the low moisture permeability membrane of the present invention may be a membrane other than polyimide.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は比較のために掲けた従来品の断面図、
第２図Ａ，Ｂは本発明の一実施例を工程順に説明
するための断面図、第３図は本発明の一実施例の
効果を従来品と比較して説明するための図であ
る。 主な記号１０１，２０１……シリコン基板、１
０２，２０３……pn接合、１０３……絶縁膜、
１０４，２０６……配線、１０５，２０７……窒
化シリコン膜、１０６，２０８……ボンデイング
パツド部、１０７，２１１……リード線、２０
２，２０４……二酸化シリコン膜、２０５……コ
ンタクト用孔、２０９……有機クロム膜、２１０
……ポリイミド。 Figure 1 is a cross-sectional view of a conventional product for comparison.
2A and 2B are cross-sectional views for explaining an embodiment of the present invention in the order of steps, and FIG. 3 is a diagram for explaining the effects of the embodiment of the present invention in comparison with a conventional product. Main symbols 101, 201...Silicon substrate, 1
02,203...pn junction, 103...insulating film,
104,206...Wiring, 105,207...Silicon nitride film, 106,208...Bonding pad portion, 107,211...Lead wire, 20
2,204...Silicon dioxide film, 205...Contact hole, 209...Organic chromium film, 210
...Polyimide.

Claims (1)

【特許請求の範囲】[Claims] １ 半導体装置の半導体個片にて、外部ヘリード
線を接続するボンデイングパツド上の絶縁保護膜
を選択的に除去する工程と、該選択的に窓を開け
られたボンデイングパツドの金属面に薄く低透湿
性樹脂膜を塗布する工程と、該低透湿性樹脂膜を
つけた状態のボンデイングパツドにその膜を突き
破るようにリード線を圧着し接続する工程とを含
むことを特徴とする半導体装置の製造方法。1. A step of selectively removing an insulating protective film on a bonding pad that connects an external lead wire in a semiconductor piece of a semiconductor device, and a process of selectively removing a thin film on the metal surface of the bonding pad that has a window opened. A semiconductor device comprising the steps of: applying a low moisture permeability resin film; and crimping and connecting a lead wire to a bonding pad with the low moisture permeability resin film applied so as to break through the film. manufacturing method.
JP56023959A 1981-02-20 1981-02-20 Manufacture of semiconductor device Granted JPS57138165A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56023959A JPS57138165A (en) 1981-02-20 1981-02-20 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56023959A JPS57138165A (en) 1981-02-20 1981-02-20 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS57138165A JPS57138165A (en) 1982-08-26
JPS628034B2 true JPS628034B2 (en) 1987-02-20

Family

ID=12125078

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56023959A Granted JPS57138165A (en) 1981-02-20 1981-02-20 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS57138165A (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5770386A (en) * 1992-05-20 1998-06-23 The United States Of America As Represented By The Department Of Health And Human Services Methods and compositions for increasing the sensitivity of a cell to a DNA damaging agent
WO2014162387A1 (en) * 2013-04-01 2014-10-09 パイオニア株式会社 Wire connection structure and electrical device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53103375A (en) * 1977-02-22 1978-09-08 Toshiba Corp Semiconductor device
JPS55150259A (en) * 1979-05-11 1980-11-22 Hitachi Ltd Semiconductor device and method of fabricating the same
JPS55166942A (en) * 1979-06-15 1980-12-26 Hitachi Ltd Semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53103375A (en) * 1977-02-22 1978-09-08 Toshiba Corp Semiconductor device
JPS55150259A (en) * 1979-05-11 1980-11-22 Hitachi Ltd Semiconductor device and method of fabricating the same
JPS55166942A (en) * 1979-06-15 1980-12-26 Hitachi Ltd Semiconductor device

Also Published As

Publication number Publication date
JPS57138165A (en) 1982-08-26

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