JPS6276817A - Programmable logic array - Google Patents

Abstract

PURPOSE:To attain effective application of an electronic device system by supplying a signal to a AND plane in the state when a specified time lapse is measured from the leading of an output from a OR plane. CONSTITUTION:An A output signal is generated from an output line of the OR plane 13 of a main body element 11 of a programmable logic array and a high level state is reached, then a flip-flop circuit 22 is fixed to the reset state, the reset state of a counter 23 is released and the counter counts by using a clock pulse signal from an oscillator 26. When the count of the counter 23 reaches a specific value, the AND plane 24 selects a signal line B, which reaches a high level and a signal is inputted from a 1-bit decoder 25 to the AND plane 12. The timer function is set by the counter 23 and the 2nd feedback loop 21 having the timer function receives an output of the OR plane 13 and a signal is fed to the AND plane 12 after a specific time. Thus, the application of the programmable logic array is expanded effectively.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention particularly relates to an improved electronic device which is configured to have, for example, a timer function and is effectively applicable to various electronic equipment systems. Constructed as a single-chip semiconductor integrated circuit (related to the upcoming programmable logic array).

[Background Art] A programmable logic array is composed of an AND plane and an OR plane. A logic function is set on the AND plane, and the data input to the AND plane is subjected to logical operation processing to form an OR plane. It is set to be sent.

A sequential logic circuit is constructed by feeding back the output data from the OR plane to the AND plane. In this case, the logic to be implemented is one that can be easily programmed and is effectively used, for example, in input/output circuits of large computer systems.

That is, a feedback loop is formed between the OR plane and the AND plane described in -1-, for example, by an exclusive OR circuit, a flip-flop circuit, etc., and the output from the OR plane is supplied to the AND plane. Yes, but
In this case, since it is difficult to set functions such as a timer, the scope of use of the programmable logic array is limited, although it has advantages such as high-speed data processing capability.

[Problems to be Solved by the Invention] This invention was made in view of the above-mentioned points. , programmable logic that can be effectively applied not only to the electronic devices specified above but also to more electronic device systems, and in particular to a state that can be effectively realized with a single-chip semiconductor integrated circuit. It is intended to provide an array.

[Means for Solving the Problems] That is, the programmable logic array according to the present invention has -
1- Executes logical operation processing based on input data, and supplies the processed data to the OR plane so that it is output from this OR plane, and further outputs the output signal from this OR plane. A timer means is set to be activated in response to the rise of the timer. In this timer means, the output from the OR plane is
A signal is supplied to the AND plane shown in - while measuring the elapse of a specified time from the edge.

[Operation] In the programmable logic array as described above, a feedback loop having a timer function is formed between the AND plane and the OR plane. Therefore, logical operation processing with a timer function is executed in order, and after a specified time has elapsed since the output is generated from the OR plane, the next logical operation processing is executed on the AND plane. The present invention can be implemented and effectively applied in various electronic equipment systems.

[Embodiments of the invention] Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

The attached drawings show the configuration, and the main body element 11 portion of the programmable logic array is composed of an AND plane 12 and an OR plane 13. For example, 4-bit input signals input from input terminals 14a to +4d are supplied to the AND plane 12 via 1-bit decoders 15a to 15d, respectively. In this AND plane 12, a predetermined logical wave calculation process is executed in response to a program command set based on the input data, and the processed data (
output buffer Ifia-
It comes to be outputted from output terminals 17a to 17c via 16c. A first feedback loop 20 is formed between the L OR plane 13 and the UN i plane 12 by an exclusive OR circuit 18 and an SR flip-flop circuit 19.

Further, between the OR plane 13 and the AND plane 12, there is a second feedback loop 2 further equipped with a timer function.
1 is formed. This second feedback loop 21 includes an RS flip-flop circuit 22 in which an output signal line A from the OR plane 13 is connected to a reset terminal R.
, an N-bit, for example, 4-bit counter 23 that is reset-controlled by the output signal Q when the flip-flop circuit 22 is set, an AND plane 24 that decodes the output signal of this counter 23, and an output signal from this AND plane 24. It consists of a 1-bit decoder 25 that is input to the AND plane 12 of the programmable logic array 11.

= 6 = Here, the main body element 11 of the programmable logic array, the first and second feedback loops 20
and 21 are configured as a single-chip semiconductor integrated circuit, and the AND plane 1 of the main body element 11 portion
2 and the AND plane 24 portion of the counter 23 are programmed simultaneously by similar means. and,
The AND plane 24 generates an output signal on the signal line B corresponding to the count value specified by the counter 23, and this signal is supplied to the decoder 25, and the counter 23 further increases the counting step. When the next specified count value is reached, an output signal is generated on the signal line C, and the flip-flop circuit 22 is set and controlled.

The counter 23 is incremented by a clock pulse signal generated by an oscillator 26.
6 may be constructed integrally with the single-chip semiconductor integrated circuit described in -1-, but it may also be constructed independently and connected externally as a circuit element.

That is, in the programmable logic array configured as shown in -1-], the input terminals 14. a~+4
The input data input from d is sent to decoders 15a to 15.
d and are respectively decoded and input to the AND plane 12. In this AND plane 12, logical operation processing is executed according to a set program based on the input data, and the result is sent to an OR plane 13. A part of this processed data is sent to output buffers 1ea-16c.
It comes to be outputted from the output terminals 17a to 17c via. The delay time of output generation with respect to this input is, for example, about 50 nS, which allows arithmetic processing and output to be performed at a much higher speed than, for example, a microcomputer.

Furthermore, the remaining portion of the processed data is returned to the AND plane 12 via the first and second feedback loops 20 and 21. A sequential logic circuit is realized using this programmable logic array.

Here, assuming a conventional case in which the second feedback loop 21 does not exist, it is not possible to execute arithmetic operations including a timer function, such as turning on after one second and turning off after three seconds. However, if the timer function is set by the second feedback loop 21, the arithmetic processing as shown in "-" will also be executed.

That is, when the output line A output signal of the OR plane 13 of the main body element 11 of the programmable logic array is generated and becomes a high level state, the flip-flop circuit 2
2 is fixed in the reset state, the reset state of the counter 23 is released, and the counter 23 starts counting by the clock pulse signal from the oscillator 26. When the count value of the counter 23 reaches a specified value, the signal line B is selected by the AND plane 24 and becomes high level, and a signal is input from the 1-bit decoder 25 to the AND plane 12.

Then, when the counter 23 is further incremented and enters the next specific counting state, the signal line C is selected and the flip-flop circuit 22 is set, and the reset input of the counter 23 becomes high level, and -9= The counting operation of this counter 23 comes to be stopped. That is, a timer function is set by this counter 23, and the second feedback loop 21 having this timer function receives the output of the OR plane 13 and supplies a signal to the AND plane 12 after a specified time has elapsed. It is what it is.

[Effects of the Invention] As described above, in the programmable logic array according to the present invention, the timer function is set in the process of its logical operation processing operation. Not only can it be used for input/output circuits, etc., but it can also be effectively applied to commonly used small and medium-sized electronic control systems, and the range of application of this programmable logic array is This makes it possible to effectively expand the

[Brief explanation of drawings]

The attached drawings show a programmable computer according to an embodiment of the present invention.
FIG. 2 is a circuit configuration diagram for explaining a logic array. 11... Main body element of programmable logic array, 12... AND plane, 13... OR plane, 14a
-14d...Input terminal, 17a to +7c...Output terminal, 20...First feedback loop, 21...
-Second feedback loop (with timer function). Applicant's agent Patent attorney Takehiko Suzue = 11-

Claims (1)

[Claims] An AND plane that performs predetermined logical operation processing based on input data; an OR plane that outputs processed data calculated on the AND plane; and a rise of the output from the OR plane; and a timer means that is activated in response to the rise of the output and measures the elapse of the specified time, and the timer means detects the elapse of the specified time from the rise of the output from the OR plane. A programmable logic array characterized in that data processing having a timer function is executed by supplying a signal to the AND plane in the state.