JPS6276792A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6276792A
JPS6276792A JP21721685A JP21721685A JPS6276792A JP S6276792 A JPS6276792 A JP S6276792A JP 21721685 A JP21721685 A JP 21721685A JP 21721685 A JP21721685 A JP 21721685A JP S6276792 A JPS6276792 A JP S6276792A
Authority
JP
Japan
Prior art keywords
layer
gaas
algaas
type
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21721685A
Other languages
Japanese (ja)
Inventor
Seiichi Miyazawa
宮沢 誠一
Yoshinobu Sekiguchi
芳信 関口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP21721685A priority Critical patent/JPS6276792A/en
Publication of JPS6276792A publication Critical patent/JPS6276792A/en
Pending legal-status Critical Current

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  • Junction Field-Effect Transistors (AREA)
  • Semiconductor Lasers (AREA)

Abstract

PURPOSE:To prevent the characteristic of a semiconductor device from deteriorating by forming a GaAs layer adjacently on a AlGaAs layer of the thickness of 500Angstrom to 1mum, and forming the device including at least two sets of layers. CONSTITUTION:In a semiconductor device that FETs are, for example, integrated, a P-type AlGaAs clad layer 2, a GaAs active layer 3, an N-type AlGaAs clad layer 4 and an N-type GaAs cap layer 5 are laminated on a P-type GaAs substrate 1 to form a semiconductor laser A. A buffer layer 6, an a-type GaAs layer 7 are laminated thereon, and FET B is formed by the layer 7. The layer 6 is formed by alternately growing non-doped AlGaAs layer 21 of 500Angstrom -1mum thick and non-doped GaAs layer 22 formed adjacently thereon. If the AlGaAs layer is 500Angstrom or less, the surface is roughened, and if it exceeds 1mum, the surface roughness cannot be improved even by the GaAs layer.

Description

【発明の詳細な説明】 (技術分野) 本発明は、半導体装置、特に積層構造の薄膜形半導体装
置に関するものである。
DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a semiconductor device, and particularly to a thin film semiconductor device having a stacked structure.

(従来技術) 半導体薄膜化技術は近年分子線エピタキシー法(MBE
法)、有機金属化学気相成長法(MO−CVD法)、等
の新手法の研究により急速な技術革新をしており、これ
ら技術は、従来技術では不可能であった半導体の超薄膜
化、大面積にわたる均一成長などを可能にした。また、
これらの特徴を生かし、従来デバイスの高性能化、新デ
バイスの提案を行っており、将来的にも有望視されてい
る。
(Prior art) In recent years, semiconductor thinning technology has been developed using molecular beam epitaxy (MBE).
Rapid technological innovations are being made through research into new methods such as MO-CVD (method) and metal-organic chemical vapor deposition (MO-CVD), and these technologies are capable of making semiconductors ultra-thin, which was impossible with conventional techniques. This enabled uniform growth over a large area. Also,
Taking advantage of these features, we are improving the performance of conventional devices and proposing new devices, which are seen as promising for the future.

現在、これら半導体薄膜化技術を利用 している分野としては、化合物半導体の技術分野が大半
である0代表的な材料としては(GaAs、AuGaA
s)(InGaAsP。
Currently, most of the fields that utilize these semiconductor thinning technologies are compound semiconductor technology fields. Typical materials include (GaAs, AuGaA
s) (InGaAsP.

A文GaInP)等の材料があげられる。この様な材料
をMBE法、MO−CVD、法等で成長して行くと、成
長した膜がある成長条件内で表面状態が荒れる場合があ
る。第4図は、従来の薄膜の形成図である。42は基板
であるところのGaAs、43は成長膜であるところの
AlGaAsである。A1GaAs膜はMBE法を用い
て成長すると基板温度(Tsub)が680°C〜75
0℃程度においてAfLGaAs表面が荒れる。ただし
、この基板温度も装置個々により異なるため装置により
多少のズレを生ずるが、他の成長条件である■族元素分
子線強度Jvと■族元素分子線強度JIの(Jv/Jm
)比および成長速度(Growth  rate)に対
する依存度は小さい。
Examples include materials such as A-pattern GaInP). When such a material is grown by MBE, MO-CVD, etc., the surface of the grown film may become rough under certain growth conditions. FIG. 4 is a diagram showing the formation of a conventional thin film. 42 is a substrate of GaAs, and 43 is a grown film of AlGaAs. When A1GaAs film is grown using the MBE method, the substrate temperature (Tsub) is 680°C to 75°C.
The AfLGaAs surface becomes rough at about 0°C. However, this substrate temperature also differs depending on the individual equipment, so there will be some deviation depending on the equipment.
) ratio and growth rate is small.

成長した膜の表面荒れは、AlGaAs膜においては、
通常3000Å以下であると成長表面の凸凹は確認する
ことは出来ないが、5000人〜Igm以上になると肉
眼によってもAfLGaAs面がくもる等の現象により
確認が出来る。また厚くつむにつれてAfLGaAs面
i上の凸凹が増大することも確認された。
The surface roughness of the grown film is as follows for AlGaAs film:
Normally, if the thickness is less than 3000 Å, unevenness on the growth surface cannot be confirmed, but if it exceeds 5000 Igm, it can be confirmed with the naked eye due to phenomena such as clouding of the AfLGaAs surface. It was also confirmed that the unevenness on the AfLGaAs surface i increases as the thickness increases.

この表面の荒れは、下記の点で問題となる。This surface roughness poses problems in the following points.

■デバイス形成プロセスの障害となる ■作成した素子の特性を劣化させる 等である。■Obstructs the device formation process ■Degrading the characteristics of the created element etc.

この様に成長膜の表面状態がデバイスに与える影響は大
きく、デバイス形成に最適と考えられる範囲の成長膜が
得られないことは、大きな問題となる。
As described above, the surface condition of the grown film has a great influence on the device, and it becomes a big problem that the grown film cannot be obtained in a range that is considered optimal for device formation.

そこで、従来より半導体成長膜の表面改善のために成長
条件による改善や、半導体積層中に超格子構造をはさむ
等の工夫がなされてきたが、いまだ十分な結果が得られ
ていなかった。
Therefore, attempts have been made to improve the surface of semiconductor grown films by changing the growth conditions or by inserting a superlattice structure into the semiconductor stack, but satisfactory results have not yet been obtained.

(発明の概要) 本発明の目的は、半導体成長膜の表面荒れを防止し、特
性の優れた半導体装置を提供することにある。
(Summary of the Invention) An object of the present invention is to prevent surface roughening of a semiconductor grown film and provide a semiconductor device with excellent characteristics.

本発明の上記目的は、500Å以上1gm以下1 の厚
さのAMGaAs層と、該AlGaAs層上に相接して
形成されたGaAs層とを少なくとも2組以上含む半導
体装置によって達成される。
The above object of the present invention is achieved by a semiconductor device including at least two or more sets of an AMGaAs layer with a thickness of 500 Å or more and 1 gm or less 1 and a GaAs layer formed adjacent to the AlGaAs layer.

即ち、本発明ではAfLGaAs層を厚く形成する場合
に、500Å以上1gm以下の間隔でGaAs層をはさ
むことによって、AlGaAsによる表面の荒れを改善
するものである。
That is, in the present invention, when forming a thick AfLGaAs layer, the surface roughness caused by AlGaAs is improved by sandwiching the GaAs layers at intervals of 500 Å or more and 1 gm or less.

AfLGaAs層は500人から表面が荒れはじめる為
、上記間隔は500Å以下では意味がない。
Since the surface of the AfLGaAs layer begins to become rough after 500 people, the above-mentioned spacing is meaningless if it is less than 500 Å.

またAfLGaAS層の厚さがIgmを越えると、Ga
As層の積層によっても表面の荒れを改善しきれなくな
る。A見GaAs層の厚さは、望ましくは500−0Å
以下、さらに望ましくは3000Å以下である。GaA
s層の厚さは50Å以上あれば表面の荒れを十分改善で
きる。
Moreover, when the thickness of the AfLGaAS layer exceeds Igm, Ga
Even by laminating As layers, the surface roughness cannot be completely improved. The thickness of the GaAs layer is preferably 500-0 Å.
The thickness is preferably 3000 Å or less. GaA
If the thickness of the s layer is 50 Å or more, surface roughness can be sufficiently improved.

(実施例) 以下、本発明の実施例を図面を用いて詳細に説明する。(Example) Embodiments of the present invention will be described in detail below with reference to the drawings.

第1図は、本発明を半導体レーザと電界効果トランジス
タ(以下、FETと称す)を集積した半導体装置に適用
した第1実施例を示す略断面図である。第1図において
、1はp型のGaAs基板で、この上にp型A1GaA
sクラッド層2、GaAs活性層3、n型AlGaAs
クラッド層4、n型GaAsキャップ層5を積層し、半
導体レーザ部Aが形成される。更にこの上にバッファ層
6、n型GaAs層7を積層し、n型GaAs層7を用
いてFET部Bが形成される。9゜10.11はFET
の電極、12は半導体レーザの電極であり、8は絶縁層
である5i02である。半導体レーザ部Aは、FET部
Bの制御で駆動され発光部13よりレーザ光を発する。
FIG. 1 is a schematic cross-sectional view showing a first embodiment in which the present invention is applied to a semiconductor device in which a semiconductor laser and a field effect transistor (hereinafter referred to as FET) are integrated. In Fig. 1, 1 is a p-type GaAs substrate, on which p-type A1GaA
s cladding layer 2, GaAs active layer 3, n-type AlGaAs
A cladding layer 4 and an n-type GaAs cap layer 5 are laminated to form a semiconductor laser section A. Furthermore, a buffer layer 6 and an n-type GaAs layer 7 are laminated thereon, and the FET section B is formed using the n-type GaAs layer 7. 9゜10.11 is FET
12 is an electrode of a semiconductor laser, and 8 is an insulating layer 5i02. The semiconductor laser section A is driven under the control of the FET section B and emits laser light from the light emitting section 13.

バッファ層6は、半導体レーザ部AとFET部Bを電気
的に分離する為のもので、本実施例では、この部分をA
lGaAsとGaAsとの多層構成としたものである。
The buffer layer 6 is for electrically separating the semiconductor laser part A and the FET part B, and in this embodiment, this part is
It has a multilayer structure of lGaAs and GaAs.

第2図に、バッファ層6の実際の構成を示す。FIG. 2 shows the actual structure of the buffer layer 6.

バッファ層6は3000人の厚さのノンドープAM、G
aAS層21と、この上に相接して形成された500人
の厚さのノンドープGaAs層22とを交互に繰り返し
成長させることによって形成される。A4uGaAsは
不純物をドーピングしないと107Ωcm”程度の高抵
抗を示し、素子間分離に適している。しかしながら、前
述のようにAiG aA sを厚く成長させると、成長
表面が荒れる。本実施例ではAlGaAs中に3000
人間隔でGaAs層をはさむことによって、成長表面を
平担に保ちながら、絶縁性に優れたバッファ層6を得た
ものである。また第2図において、半導体層の繰り返し
周期を変え、5000人のノンドープAfLGaAs層
21と1000人のノンドープGaAs層22とを交互
に成長させてバッファ層6とした装置を形成したが、こ
れも前述の実施例と同様に、良好に作動した。
The buffer layer 6 is made of non-doped AM, G with a thickness of 3000 mm.
It is formed by alternately and repeatedly growing an aAS layer 21 and a non-doped GaAs layer 22 with a thickness of 500 nm formed adjacent thereto. A4uGaAs exhibits a high resistance of about 107 Ωcm'' without doping with impurities, making it suitable for isolation between elements. However, as mentioned above, when AiGaAs is grown thickly, the growth surface becomes rough. In this example, the growth surface becomes rough. 3000 to
By sandwiching the GaAs layers at intervals, a buffer layer 6 with excellent insulation properties was obtained while keeping the growth surface flat. Further, in FIG. 2, a device was formed as a buffer layer 6 by changing the repetition period of the semiconductor layer and growing a non-doped AfLGaAs layer 21 of 5000 layers and a non-doped GaAs layer 22 of 1000 layers alternately, which was also described above. It worked well, as did the previous example.

第3図は、本発明を半導体レーザに適用した第2実施例
を示す略断面図である0図中31はn型GaAs基板で
、この上に厚さ3000人のn型AfLGaAs層32
及び厚さ200人のn型GaAs33を交互に2組積層
し、更にn型AflGaAs層32を600OA成長さ
せて、し〜ザのクラッド層40とした。
FIG. 3 is a schematic cross-sectional view showing a second embodiment in which the present invention is applied to a semiconductor laser. In FIG.
Then, two sets of n-type GaAs 33 with a thickness of 200 layers were alternately laminated, and an n-type AflGaAs layer 32 with a thickness of 600 OA was grown to form the next cladding layer 40.

こ°のクラッド層40上にn型GaAs活性層34を形
成し、更にp型のクラッド層41.p型GaAsキャッ
プ層37を積層して半導体レーザを形成した。ここでク
ラッド層41もやはり活性層上に厚さ6000人のp型
AlGaAs層35を成長させ、更にこの上に厚さ20
0人のpWGaAs層36と厚さ3000人のP型Al
GaAs層35とを交互に2組積層することによって成
る。38は絶縁層、39は電極、30は発光部である。
An n-type GaAs active layer 34 is formed on this cladding layer 40, and a p-type cladding layer 41. A p-type GaAs cap layer 37 was laminated to form a semiconductor laser. Here, the cladding layer 41 is also formed by growing a p-type AlGaAs layer 35 with a thickness of 6000 on the active layer, and further growing a p-type AlGaAs layer 35 with a thickness of 2000 on top of this.
0.0 nm pWGaAs layer 36 and 3000 nm thick P-type Al
It is made by laminating two sets of GaAs layers 35 alternately. 38 is an insulating layer, 39 is an electrode, and 30 is a light emitting part.

本実施例において、活性層34に相接するA又GaAs
層が他の部分より厚くしであるのは、クラッド層中のG
aAs層があまり活性層に近いと、光を吸収する可能性
がある為である。
In this embodiment, A or GaAs adjacent to the active layer 34 is used.
The reason why the layer is thicker than other parts is because of the G in the cladding layer.
This is because if the aAs layer is too close to the active layer, it may absorb light.

本実施例では、上記構成によってクラッド層40の活性
層34との界面が改善され、界面準位の少い、長寿命の
半導体レーザが形成出来た。また、多層構成のクラッド
層41によってキャップN37の表面゛が平担化され、
作製プロセス中に表面凸凹によって生ずる問題が解消し
た。
In this example, the interface between the cladding layer 40 and the active layer 34 was improved by the above structure, and a long-life semiconductor laser with few interface states could be formed. Furthermore, the surface of the cap N37 is flattened by the cladding layer 41 having a multilayer structure,
Problems caused by surface irregularities during the fabrication process have been resolved.

本発明は、以上の実施例に限1ず。The present invention is not limited to the above embodiments.

A l (r a A sを用いる種々の半導体装置に
適用が可能である。
It can be applied to various semiconductor devices using A l (ra As).

(発明の効果) 以上説明したように、本発明は500Å以上1ルm以下
の厚さのA見GaAs層と、該AJljGaAS暦上に
相接して形成されたGaAs層とを少なくとも2組以上
含んで半導体装置を構成したので、装置の特性が劣化す
ることがなく、またデバイス形成プロセスにおける障寄
り奢生を防ぐ効果がある。
(Effects of the Invention) As explained above, the present invention comprises at least two or more sets of A-type GaAs layers having a thickness of 500 Å or more and 1 lumen or less, and GaAs layers formed adjacent to each other on the AJljGaAS layer. Since the semiconductor device is constructed by including the semiconductor device, the characteristics of the device do not deteriorate, and there is an effect of preventing failures in the device formation process.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の第1実施例を示す略断面図、第2図は
第1図におけるバッファ層の構成を説明する部分断面図
、第3図は本発明の第2実施例を示す略断面図、第4図
は従来の半導体層の成長の様子を示す略断面図である。 5−−−n型GaAsキャップ層、 6−−−バツフア層、7一−−n型GaAs層、21−
−− / yドープAMGaAs層、22−−−/7ド
ーブGaAs層。
FIG. 1 is a schematic cross-sectional view showing a first embodiment of the present invention, FIG. 2 is a partial cross-sectional view explaining the structure of the buffer layer in FIG. 1, and FIG. 3 is a schematic cross-sectional view showing a second embodiment of the present invention. 4 is a schematic cross-sectional view showing the growth of a conventional semiconductor layer. 5--n-type GaAs cap layer, 6--buffer layer, 71--n-type GaAs layer, 21-
--/y doped AMGaAs layer, 22---/7 doped GaAs layer.

Claims (2)

【特許請求の範囲】[Claims] (1)半導体の積層によって構成される半導体装置にお
いて、前記半導体が500Å以上 1μm以下の厚さのAlGaAs層と、 該AlGaAs層上に相接して形成された GaAs層とを少なくとも2組以上含むことを特徴とす
る半導体装置。
(1) A semiconductor device configured by stacking semiconductors, wherein the semiconductor includes at least two sets of an AlGaAs layer with a thickness of 500 Å or more and 1 μm or less, and a GaAs layer formed in contact with the AlGaAs layer. A semiconductor device characterized by:
(2)前記GaAs層が50Å以上の厚さを有する特許
請求の範囲第1項記載の半導体装置。
(2) The semiconductor device according to claim 1, wherein the GaAs layer has a thickness of 50 Å or more.
JP21721685A 1985-09-30 1985-09-30 Semiconductor device Pending JPS6276792A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21721685A JPS6276792A (en) 1985-09-30 1985-09-30 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21721685A JPS6276792A (en) 1985-09-30 1985-09-30 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6276792A true JPS6276792A (en) 1987-04-08

Family

ID=16700677

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21721685A Pending JPS6276792A (en) 1985-09-30 1985-09-30 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6276792A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7402447B2 (en) 2001-07-26 2008-07-22 Matsushita Electric Industrial Co., Ltd. Semiconductor laser device and method for fabricating the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7402447B2 (en) 2001-07-26 2008-07-22 Matsushita Electric Industrial Co., Ltd. Semiconductor laser device and method for fabricating the same

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