JP2874213B2 - Tunnel diode - Google Patents
Tunnel diodeInfo
- Publication number
- JP2874213B2 JP2874213B2 JP1259125A JP25912589A JP2874213B2 JP 2874213 B2 JP2874213 B2 JP 2874213B2 JP 1259125 A JP1259125 A JP 1259125A JP 25912589 A JP25912589 A JP 25912589A JP 2874213 B2 JP2874213 B2 JP 2874213B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- compound semiconductor
- iii
- type
- semiconductor layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、トンネルダイオードに用いられる半導体の
積層構造に関するものである。Description: TECHNICAL FIELD The present invention relates to a laminated structure of a semiconductor used for a tunnel diode.
従来、トンネルダイオードは、半導体中の伝導帯と価
電子帯の間の電子及び正孔のトンネル現象を利用したデ
バイスであり、このトンネル現象は、ｐ型層及びｎ型層
に高濃度の不純物をドープし、高い内部電界をpn接合部
に生ぜしめることにより可能となっていた。この為不純
物の高濃度ドーピングの可否がトンネルダイオードのト
ンネル特性の良否を左右していた（アイイーイーイ，ト
ランスアクション，オン エレクトロン デバイス ED
−23,644（1976）。Conventionally, a tunnel diode is a device using a tunnel phenomenon of electrons and holes between a conduction band and a valence band in a semiconductor, and this tunnel phenomenon causes a high concentration of impurities in a p-type layer and an n-type layer. This was made possible by doping and creating a high internal electric field at the pn junction. For this reason, the availability of high-concentration doping of impurities has influenced the quality of the tunnel characteristics of the tunnel diode (I / E / transaction / on-electron device ED)
-23,644 (1976).
しかし、不純物の高濃度ドーピングは、結晶成長条
件，不純物種によって特性が大きく変化し、良好なトン
ネル現象を得るのに必要な高濃度ドーピングは、一般に
困難である。However, high-concentration doping of impurities greatly varies in characteristics depending on crystal growth conditions and impurity species, and high-concentration doping necessary for obtaining a good tunnel phenomenon is generally difficult.
本発明の目的は、この問題点を解決し、高濃度ドーピ
ングを施こさなくても常に良好なトンネル特性が得られ
る半導体積層構造を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to solve this problem and to provide a semiconductor multilayer structure that can always obtain good tunnel characteristics without performing high-concentration doping.
本発明による半導体積層構造は、III−Ｖ族化合物半
導体上に３層のIII−Ｖ族化合物半導体層が積層された
構造よりなり、第１の層はｐ型の導電性を有し、第２の
層は引張性の歪を有し、第３の層はｎ型の導電性を有
し、第１から第３の層が順次（111）Ａ面方位のIII−Ｖ
族化合物半導体上に積層されるか、（111）Ｂ面方位のI
II−Ｖ族化合物半導体上に前記第３から第１の層が順次
積層されてあることに特徴がある構成になっている。The semiconductor laminated structure according to the present invention has a structure in which three III-V compound semiconductor layers are laminated on a III-V compound semiconductor, the first layer has p-type conductivity, and the second layer has a p-type conductivity. Has a tensile strain, the third layer has n-type conductivity, and the first to third layers are sequentially formed of (III) -III-V
Layered on group III compound semiconductors or (111) B-oriented I
The third to first layers are sequentially laminated on the II-V compound semiconductor.
また、別の発明では、III−Ｖ族化合物半導体上に３
層のIII−Ｖ族化合物半導体層が積層された構造であっ
て、第１の層はｐ型の導電性を有し、第２の層は圧縮性
の歪を有し、第３の層はｎ型の導電性を有し、第１から
第３の層が順次（111）Ｂ面方位のIII−Ｖ族化合物半導
体上に積層されるか、（111）Ａ面方位のIII−Ｖ族化合
物半導体上に前記第３から第１の層が順次積層されてあ
ることに特徴がある構成になっている。Further, in another invention, 3
A group III-V compound semiconductor layer, wherein the first layer has p-type conductivity, the second layer has compressive strain, and the third layer has The first to third layers having n-type conductivity are sequentially laminated on a (111) B group III-V compound semiconductor or a (111) A group III-V compound The configuration is characterized in that the third to first layers are sequentially stacked on a semiconductor.
以下、図面を用いて本発明の作用を説明する。 Hereinafter, the operation of the present invention will be described with reference to the drawings.
第１図（ａ）は第１の発明の半導体積層構造のバンド
図である。構造は、（111）Ａ面方位のIII−Ｖ族化合物
半導体上にｐ型層、引張性歪層、ｎ型層を順次積層して
pn接合の間に引張性の歪を有する層を挿入する構造とな
っている。この場合、積層方向が（111）Ａ方向であ
り、第２の層が引張性歪層で構成されており、この引張
性歪層には歪によるピエゾ内部電界が発生する。その電
界の方向は、この場合には積層方向とは逆の方向である
（111）Ｂ方向である。また、第１の層と第２の層の導
電型によっても、その間の層である引張性歪層に電界が
生じる。第１図（ａ）の場合、第１の層11はｐ型導電層
であり、第３の層13はｎ型導電層で構成されているの
で、この導電型により生じる内部電界の方向は積層方向
とは逆の方向である（111）Ｂ方向に生じる。則ち、歪
によるピエゾ内部電界の方向とｐ型層とｎ型層により生
じる内部電界の方向は同じである。このため、引張性歪
層12に印加される電界は、この２つの電界により大きく
増強され、大きなトンネル効果が得られる。図中、引張
性歪層12とｐ型導電性層11及びｎ型導電性層13との界面
でバンド不連続が生じるのは、そこで層の組成が変化し
ているためである。歪によるピエゾ電界は、約１％の格
子不整合に対しておよそ100〜300kV/cmと大きな電界が
発生する。pn接合による内部電界と歪による内部電界が
同方向に加わる為、pn接合部では大きなトンネル確率が
得られ、第２図の実線で示すような良好なトンネル特性
を示す。（111）Ａ面方位のIII−Ｖ族化合物半導体に替
えて（111）Ｂ面方位のIII−Ｖ族化合物半導体を用い、
積層方向を（111）Ｂ方向とした場合で、第２の層が引
張性歪層で構成されているときは、ピエゾ内部電界の生
じる方向は積層方向と同じ方向の（111）Ｂ方向に生じ
る。従って、このピエゾ内部電界を増長する方向に、導
電型による内部電界を生じせしめるようにｐ型層とｎ型
層を配置する。則ち、この場合、（111）Ｂ面方位のIII
−Ｖ族化合物半導体上にｎ型導電性層、引張性歪層、ｐ
型導電性層を順次積層すれば良好なトンネル特性が得ら
れる。FIG. 1A is a band diagram of the semiconductor multilayer structure of the first invention. The structure is such that a p-type layer, a tensile strain layer, and an n-type layer are sequentially laminated on a III-V compound semiconductor having a (111) A plane orientation.
In this structure, a layer having tensile strain is inserted between pn junctions. In this case, the laminating direction is the (111) A direction, and the second layer is formed of a tensile strained layer, and a piezoelectric internal electric field is generated in the tensile strained layer due to strain. In this case, the direction of the electric field is the (111) B direction, which is the direction opposite to the stacking direction. Also, an electric field is generated in the tensile strained layer that is a layer between the first layer and the second layer depending on the conductivity type of the second layer. In the case of FIG. 1 (a), the first layer 11 is a p-type conductive layer and the third layer 13 is an n-type conductive layer. It occurs in the (111) B direction, which is the opposite direction to the direction. That is, the direction of the piezoelectric internal electric field due to the strain is the same as the direction of the internal electric field generated by the p-type layer and the n-type layer. For this reason, the electric field applied to the tensile strained layer 12 is greatly enhanced by these two electric fields, and a large tunnel effect is obtained. In the figure, the band discontinuity occurs at the interface between the tensile strained layer 12, the p-type conductive layer 11, and the n-type conductive layer 13 because the composition of the layer changes there. The piezo electric field due to the strain generates a large electric field of about 100 to 300 kV / cm for about 1% lattice mismatch. Since the internal electric field due to the pn junction and the internal electric field due to the strain are applied in the same direction, a large tunnel probability is obtained at the pn junction, and good tunnel characteristics are exhibited as shown by the solid line in FIG. A III-V compound semiconductor having a (111) B orientation is used in place of a III-V compound semiconductor having a (111) A orientation,
When the laminating direction is the (111) B direction and the second layer is composed of a tensile strained layer, the direction in which the piezo internal electric field is generated occurs in the (111) B direction, which is the same direction as the laminating direction. . Therefore, the p-type layer and the n-type layer are arranged so as to generate an internal electric field of the conductivity type in a direction in which the piezo internal electric field is increased. That is, in this case, the III of the (111) B plane orientation
An n-type conductive layer, a tensile strain layer,
Good tunnel characteristics can be obtained by sequentially laminating the mold conductive layers.
第１図（ｂ）は、別の発明の半導体積層構造のバンド
図である。（111）Ｂ面方位のIII−Ｖ族化合物半導体上
にｐ型導電性層、圧縮性歪層、ｎ型導電性層を順次積層
した構造で、積層方向が（111）Ｂ方向であるため歪層1
5が圧縮性の歪を有する点が、第１の発明と異なる点で
ある。しかし作用の点では第１の発明と同じである。
（111）Ａ面方位のIII−Ｖ族化合物半導体を用いた場合
は、（111）Ａ面方位のIII−Ｖ族化合物半導体上にｎ型
導電性層、圧縮性歪層、ｐ型導電性層を順次積層すれば
上記と同様の効果が得られる。FIG. 1 (b) is a band diagram of a semiconductor multilayer structure according to another invention. A structure in which a p-type conductive layer, a compressive strained layer, and an n-type conductive layer are sequentially laminated on a (111) B-plane III-V compound semiconductor, and the lamination direction is the (111) B direction. Tier 1
5 is different from the first invention in that it has compressive distortion. However, the operation is the same as that of the first invention.
When a (111) A-plane III-V compound semiconductor is used, an n-type conductive layer, a compressive strained layer, and a p-type conductive layer are formed on the (111) A-plane III-V compound semiconductor. Are sequentially laminated, the same effect as above can be obtained.
第３図（ａ），（ｂ）は第１の発明による半導体積層
構造の２つの実施例である。これは、分子線エピタキシ
ー法により製作した。製作手順は、ｐ型InP（111）Ａ基
板上にBeドープIn0.53Ga0.47As層31を0.5μm,ドーピン
グ濃度は５×1018cm-3,その上にIn0.35Ga0.65As層32
（歪層）を60Å積み、更にSnドープIn0.53Ga0.47As層33
を0.5μm,ドーピング濃度は５×1018cm-3を順次積層し
た。この層構造のバンド図は第１図（ａ）のようであ
る。歪層32の格子不整合度は約１％であり、これによる
ピエゾ電界は、約150kV/cmである。このピエゾ電界が加
わることにより、空乏層に平均的にかかる内部電界は、
約500kV/cm程度となり、両ドーピング層31,33に〜１×1
019cm-3ドーピングしたのと同程度の電界が生じた。こ
れにより、そのトンネル特性は、第２図に示したような
良好な特性を示した。また第３図（ｂ）は、歪層の部分
もｐ型,n型にドーピングした例であり、歪層35,36にお
いても更に空乏層が広がるため、電子はよりトンネルし
やすくなっている。FIGS. 3A and 3B show two embodiments of the semiconductor multilayer structure according to the first invention. This was manufactured by a molecular beam epitaxy method. The fabrication procedure is as follows: a Be-doped In 0.53 Ga 0.47 As layer 31 on a p-type InP (111) A substrate is 0.5 μm, the doping concentration is 5 × 10 18 cm −3 , and an In 0.35 Ga 0.65 As layer 32
(Strained layer) 60Å, Sn-doped In 0.53 Ga 0.47 As layer 33
And a doping concentration of 5 × 10 18 cm −3 . The band diagram of this layer structure is as shown in FIG. The degree of lattice mismatch of the strained layer 32 is about 1%, and the piezo electric field is about 150 kV / cm. Due to the application of the piezo electric field, the internal electric field applied to the depletion layer on average is
Approximately 500 kV / cm, both doping layers 31 and 33
An electric field comparable to that of the 0 19 cm -3 doping was generated. As a result, the tunnel characteristics showed good characteristics as shown in FIG. FIG. 3B shows an example in which the strained layer is also doped with p-type and n-type. Since the depletion layers are further expanded in the strained layers 35 and 36, electrons are more easily tunneled.
第４図は、別の発明による半導体積層構造の実施例で
ある。FIG. 4 is an embodiment of a semiconductor laminated structure according to another invention.
これも分子線エピタキシー法により製作した。製作手
順は、InP（111）Ｂ基板上にBeドープIn0.53Ga0.41As層
41を0.5μm,ドーピングレベル５×1018cm-3、次にIn0.7
Ga0.3As層42を60Å積み、更にSnドープIn0.53Ga0.47As
層43をドーピングレベル５×1018cm-3で0.5μｍ積層し
たものである。This was also manufactured by the molecular beam epitaxy method. The fabrication procedure is as follows: Be doped In 0.53 Ga 0.41 As layer on InP (111) B substrate
41 at 0.5 μm, doping level 5 × 10 18 cm -3 , then In 0.7
Ga 0.3 As layer 42 is stacked 60 mm, and Sn-doped In 0.53 Ga 0.47 As
The layer 43 is a 0.5 μm layer with a doping level of 5 × 10 18 cm −3 .
この場合には、歪層のバンドキャップが両端のIn0.53
Ga0.47As層41,43より小さくなっており、このためトン
ネル特性は第１の発明に比べより良好のものとなった。In this case, the band cap of the strained layer has In 0.53
As compared with the Ga 0.47 As layers 41 and 43, the tunnel characteristics were better than those of the first invention.
本実施例では、InP上のInGaAs系を例にとって説明し
たが、材料はこれに限定されない。例えばInP上のInAlA
s系であってもよいし、GaAs上のInGaAs系,InGaAlP系で
あってもよい。また成長方法も気相成長法であっても液
相成長法であってもよい。In the present embodiment, an InGaAs system on InP has been described as an example, but the material is not limited to this. For example, InAlA on InP
It may be an s type, an InGaAs type on GaAs, or an InGaAlP type. The growth method may be a vapor phase growth method or a liquid phase growth method.
本発明によれば、高濃度ドーピングができない化合物
半導体でも良好なトンネルダイオードを製作できる。According to the present invention, a good tunnel diode can be manufactured even with a compound semiconductor that cannot be doped at a high concentration.
第１図（ａ）は第１の発明によるバンド図、第１図
（ｂ）は第２の発明によるバンド図。第２図は本発明に
よるトンネルダイオードのＩ−Ｖ特性を示す図、第３図
（ａ），（ｂ）は第１の発明の２つの実施例を示す図、
第４図は第２の発明の実施例の図である。 図において、 11……ｐ型導電性層、12……引張性歪層、13……ｎ型導
電性層、15……圧縮性歪層、31……BeドープIn0.53Ga
0.47As層、32……In0.35Ga0.65As歪層、33……Snドープ
In0.53Ga0.47As層、35……BeドープIn0.35Ga0.65As歪
層、36……SnドープIn0.35Ga0.65As歪層、41……Beドー
プIn0.53Ga0.47As層、42……In0.7Ga0.3As歪層、43……
SnドープIn0.53Ga0.47As層、 をそれぞれ示す。FIG. 1 (a) is a band diagram according to the first invention, and FIG. 1 (b) is a band diagram according to the second invention. FIG. 2 is a diagram showing the IV characteristics of the tunnel diode according to the present invention, FIGS. 3 (a) and (b) are diagrams showing two embodiments of the first invention,
FIG. 4 is a diagram of an embodiment of the second invention. In the figure, 11: p-type conductive layer, 12: tensile strain layer, 13: n-type conductive layer, 15: compressive strain layer, 31: Be-doped In 0.53 Ga
0.47 As layer, 32 ... In 0.35 Ga 0.65 As strained layer, 33 ... Sn doped
In 0.53 Ga 0.47 As layer, 35 ... Be doped In 0.35 Ga 0.65 As strained layer, 36 ... Sn doped In 0.35 Ga 0.65 As strained layer, 41 ... Be doped In 0.53 Ga 0.47 As layer, 42 ... In 0.7 Ga 0.3 As strained layer, 43 ……
And Sn-doped In 0.53 Ga 0.47 As layer, respectively.
Claims (4)
族化合物半導体層とｎ型III−Ｖ族化合物半導体層とか
ら成るpnトンネル接合を有するトンネルダイオードにお
いて、（111）Ａ面方位の前記III−Ｖ族化合物半導体上
に前記ｐ型III−Ｖ族化合物半導体層、引張性の歪を有
するIII−Ｖ族化合物半導体層、ｎ型III−Ｖ族化合物半
導体層を順次積層してトンネル接合を形成したことを特
徴とするトンネルダイオード。1. A p-type III-V compound semiconductor on a III-V compound semiconductor.
In a tunnel diode having a pn tunnel junction composed of a group III compound semiconductor layer and an n-type group III-V compound semiconductor layer, the p-type group III-V compound is formed on the group III-V compound semiconductor having a (111) A plane orientation. A tunnel diode formed by sequentially stacking a semiconductor layer, a III-V compound semiconductor layer having tensile strain, and an n-type III-V compound semiconductor layer to form a tunnel junction.
族化合物半導体層とｎ型III−Ｖ族化合物半導体層とか
ら成るpnトンネル接合を有するトンネルダイオードにお
いて、（111）Ｂ面方位の前記III−Ｖ族化合物半導体上
に前記ｎ型III−Ｖ族化合物半導体層、引張性の歪を有
するIIII−Ｖ族化合物半導体層、ｐ型III−Ｖ族化合物
半導体層を順次積層してトンネル接合を形成したことを
特徴とするトンネルダイオード。2. A p-type III-V compound semiconductor on a III-V compound semiconductor.
In a tunnel diode having a pn tunnel junction consisting of a group III compound semiconductor layer and an n-type group III-V compound semiconductor layer, the n-type group III-V compound is formed on the group III-V compound semiconductor having a (111) B plane orientation. A tunnel diode formed by sequentially stacking a semiconductor layer, a group III-V compound semiconductor layer having tensile strain, and a p-type group III-V compound semiconductor layer to form a tunnel junction.
族化合物半導体層とｎ型III−Ｖ族化合物半導体層とか
ら成るpnトンネル接合を有するトンネルダイオードにお
いて、（111）Ｂ面方位の前記III−Ｖ族化合物半導体上
に前記ｐ型III−Ｖ族化合物半導体層、圧縮性の歪を有
するIII−Ｖ族化合物半導体層、ｎ型III−Ｖ族化合物半
導体層を順次積層してトンネル接合を形成したことを特
徴とするトンネルダイオード。3. A p-type III-V compound semiconductor on a III-V compound semiconductor.
In a tunnel diode having a pn tunnel junction consisting of a group III compound semiconductor layer and an n-type group III-V compound semiconductor layer, the p-type group III-V compound is formed on the group III-V compound semiconductor having a (111) B plane orientation. A tunnel diode formed by sequentially stacking a semiconductor layer, a III-V compound semiconductor layer having compressive strain, and an n-type III-V compound semiconductor layer to form a tunnel junction.
族化合物半導体層とｎ型III−Ｖ族化合物半導体層とか
ら成るpnトンネル接合を有するトンネルダイオードにお
いて、（111）Ａ面方位の前記III−Ｖ族化合物半導体上
に前記ｎ型III−Ｖ族化合物半導体層、圧縮性の歪を有
するIII−Ｖ族化合物半導体層、ｐ型III−Ｖ族化合物半
導体層を順次積層してトンネル接合を形成したことを特
徴とするトンネルダイオード。4. A p-type III-V compound on a III-V compound semiconductor.
In a tunnel diode having a pn tunnel junction comprising a group III compound semiconductor layer and an n-type group III-V compound semiconductor layer, the n-type group III-V compound is formed on the group III-V compound semiconductor having a (111) A plane orientation. A tunnel diode, wherein a tunnel junction is formed by sequentially stacking a semiconductor layer, a III-V compound semiconductor layer having compressive strain, and a p-type III-V compound semiconductor layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1259125A JP2874213B2 (en) | 1989-10-03 | 1989-10-03 | Tunnel diode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1259125A JP2874213B2 (en) | 1989-10-03 | 1989-10-03 | Tunnel diode |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03120760A JPH03120760A (en) | 1991-05-22 |
| JP2874213B2 true JP2874213B2 (en) | 1999-03-24 |
Family
ID=17329668
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1259125A Expired - Fee Related JP2874213B2 (en) | 1989-10-03 | 1989-10-03 | Tunnel diode |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2874213B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7737451B2 (en) * | 2006-02-23 | 2010-06-15 | Cree, Inc. | High efficiency LED with tunnel junction layer |
-
1989
- 1989-10-03 JP JP1259125A patent/JP2874213B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH03120760A (en) | 1991-05-22 |
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