JP2702595B2 - Impurity diffusion layer - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an impurity diffusion layer formed on a silicon substrate.

(Prior art) In the literature (Journal of Applied Physics (J. Appl. Phys. 66 (2), 15, July 1989, p. 531)), a silicon nitride film is formed in a predetermined shape on a silicon wafer.
If a thick oxide film for element isolation is formed by oxidizing a portion of the silicon wafer where the silicon nitride film is not formed, a portion of the silicon wafer in contact with the silicon nitride film, particularly a portion in contact with an end portion of the silicon nitride film It has been reported that a dislocation defect is generated in the steel.

Further, the degree of occurrence of the dislocation defects depends on the stress of the silicon nitride film, the type and concentration of n-type or p-type impurities (hereinafter, impurities) on the silicon wafer surface, and the heat treatment temperature applied to the silicon / silicon nitride film structure. It is reported that the temperature depends on the type and concentration of impurities.

The reason why the occurrence of the dislocation defect depends on the type and concentration of the impurity is that when the impurity is arranged in a tetrahedral shape in the silicon crystal, the atomic radius of the impurity is different from that of silicon, so that the silicon crystal lattice is distorted. That is, the degree to which the silicon crystal lattice is distorted changes depending on the difference in the atomic radius due to the difference in the type of the impurity and the concentration of the impurity, and the amount of dislocation defects changes.

Further, in the above-mentioned document, as a specific example, the results of comparison of the occurrence of dislocation defects when the impurity is arsenic (As) and when the impurity is boron (B) are reported.

As dose of 1 × 10 ¹⁶ / cm ² on silicon wafer 45
When a 0 し た oxide film is formed, a 3,000 膜厚 silicon nitride film is further formed, and a structure obtained by simultaneously patterning the silicon nitride film and the oxide film is heat-treated at a temperature of 1000 ° C., very few dislocation defects occur. That.

On the other hand, when the impurity is B, if the thickness of the silicon nitride film and the oxide film and the heat treatment conditions are the same as those of the case of As, even if the dose amount of B is about 3 × 10 ¹³ , very many dislocation defects will occur. Is said to occur.

When As is used, the number of dislocation defects is small because the atomic radius of As is 1.25Å, which is almost the same as the atomic radius of silicon 1.17Å. It is said that it is not easy. On the other hand, when B is used, the atomic radius of B is 0.88 °, which is considerably smaller than that of silicon, so that the silicon crystal lattice is distorted in the direction of contraction. For this reason, dislocation defects are likely to occur.

(Problems to be Solved by the Invention) As described above, the distortion of the silicon crystal lattice induced by impurities in the n-type or p-type impurity diffusion layer (hereinafter, referred to as “strain”)
Abbreviated as impurity-induced strain. ) Due to dislocation defects
This does not occur only in a system composed of a silicon nitride film and an impurity diffusion layer. For example, a system composed of a high-concentration impurity diffusion layer frequently used in a silicon semiconductor and a wiring connected to the high-concentration impurity diffusion layer However, this is expected to occur when the wiring material is a material having high stress.

However, at present, no occurrence of a dislocation defect, which is considered to be caused by impurity-induced strain, at the junction between the impurity diffusion layer and the wiring and no defect due to the dislocation defect have been pointed out.

The reason for this is that because the wiring currently used is made of an aluminum alloy, the stress acting on the silicon substrate is small, and because of the melting point of aluminum, the heat treatment after the formation of the wiring (between the wiring and the impurity diffusion layer) The heat treatment for improving the connection) temperature was less than 500 ° C., and dislocation defects were hardly generated.

Even if a dislocation defect due to impurity-induced strain occurs near the surface of the impurity diffusion layer, the effect of the dislocation defect is limited to the pn junction due to the deep diffusion depth of the high-concentration impurity diffusion layer. This dislocation defect does not reach p-
That is, it did not cause deterioration of electrical characteristics such as an increase in leakage current at the time of reverse bias of the n-junction.

However, in the future, as the miniaturization of semiconductor elements further advances, the diffusion depth of the high-concentration impurity diffusion layer will be reduced due to the principle of proportional reduction, and aluminum will be required to prevent aluminum from entering the silicon substrate by sintering. Since it is expected that a barrier metal will be used between the wiring and the impurity diffusion layer, dislocation defects are likely to occur due to the stress of the barrier metal even in a heat treatment at less than 500 ° C. In addition, the dislocation defects affect the p ⁺ / n junctions (n ⁺ / p junctions) of the shallow high-concentration impurity diffusion layer and cause a leakage current when these junctions are reverse biased.

The present invention has been made in view of such a point,
SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide an impurity diffusion layer having a structure capable of preventing occurrence of dislocation defects due to impurity-induced strain at a junction between an impurity diffusion layer and a wiring which is expected in the future.

(Means for Solving the Problems) In order to achieve this object, according to the present invention, in an n-type or p-type impurity diffusion layer formed on a silicon substrate, And germanium (G
e) forming the second impurity diffusion layer formed using the method (e) at a depth shallower than the diffusion depth of the n-type or p-type impurity diffusion layer, and
It is characterized by being provided with a surface concentration represented by the following formula (1). Here, β _sol in the equation (1) is a lattice contraction coefficient of silicon (cm ³ / atom) due to an n-type or p-type impurity element.
m), which is given by the following equation (2). Also, (1)
Β _Ge in the equation is a lattice contraction coefficient (cm ³ / atom) of silicon by germanium, and is given by the following equation (3). Here, in the expressions (2) and (3), r _si is the atomic radius of silicon, and N is the density of the silicon crystal. Further, r _sol in the formula (2) is the atomic radius of the n-type or P-type impurity element.
R _Ge in the expression (3) is the atomic radius of germanium. .

Ge surface concentration = surface concentration of n-type or P-type impurity element × β _sol / β _Ge (1) β _sol = (1-r _sol / r _si ) / N (2) β _Ge = (1-r _Ge / r _si ) / N (3) The silicon substrate referred to in the present invention is a silicon substrate itself, or a substrate having an epitaxial silicon layer on a silicon substrate. This includes the case of a substrate that has already been fabricated.

(Function) According to the configuration of the present invention, the n-type or p-type impurity diffusion layer has a second impurity diffusion layer having a predetermined depth and a predetermined surface concentration formed by using Ge on a surface portion thereof. Become. Therefore, even if the n-type or p-type impurity in the n-type or p-type impurity diffusion layer has an atomic radius smaller than that of silicon and thus the silicon crystal lattice of the impurity diffusion layer is distorted, In the second impurity diffusion layer, the strain of the silicon crystal lattice is smaller than that of the n-type or p-type impurity diffusion layer due to the presence of Ge, which is an element having a large atomic radius. That is, impurity-induced distortion is less likely to occur in the second impurity diffusion layer.

Therefore, if a wiring is connected to the second impurity diffusion layer or a silicon nitride film is formed on the second impurity diffusion layer, the second impurity diffusion layer is formed even when the stress of the wiring or the silicon nitride film is high. Dislocation defects are less likely to occur in the impurity diffusion layer of FIG. Further, the second impurity diffusion layer is n-type or p-type.
The effect of the stress on the impurity diffusion layer is reduced. For this reason, dislocation defects due to the impurity-induced strain hardly occur in the entire impurity diffusion layer.

In the second impurity diffusion layer, silicon and Ge
(Si-Ge compound) is formed, the compound having a narrower band gap between the metal wiring and the silicon substrate when the metal wiring is provided on the second impurity diffusion layer than in the case where only silicon is provided. Become intervening. Since the ohmic contact can be better when the band gap is smaller, the contact between the second impurity diffusion layer and the metal wiring shows a lower resistance and better ohmic contact than the contact between the silicon and the metal wiring. Conceivable.

(Example) Hereinafter, an impurity diffusion layer according to an example will be described using an example in which germanium (Ge) is used as an element having an atomic radius larger than that of silicon, which is an element having a four-coordinate bond with silicon. The description will be made with reference to the drawings, but the drawings used for the description only schematically show the dimensions, shapes, and arrangement relations of the components so that the present invention can be understood.

FIG. 1 (A) is a cross-sectional view showing the impurity diffusion layer 11 of the embodiment along the thickness direction of the silicon substrate 13, and FIG. 1 (B) is a diagram showing the impurity diffusion layer 11 in FIG. It is the top view shown seen from P direction of (A).

The impurity diffusion layer 11 of this embodiment includes a p-type impurity diffusion layer 15 containing boron (B) as an impurity and formed on an n-type silicon substrate 13 containing phosphorus (P) as an impurity. A second impurity diffusion layer 17 formed using Ge as an impurity therein and having a depth smaller than the diffusion depth of the diffusion layer 15 is formed.

As shown in FIG. 1B, the area of the second impurity diffusion layer 17 of this embodiment is considerably smaller than the area of the p-type impurity diffusion layer 15, as viewed in plan. But,
The plane area of the second impurity diffusion layer 15 can be arbitrarily changed according to the design. For example, as shown in FIG.
It may be the same as the flat area of 15.

In the example shown in FIGS. 1A and 1B, the second
Although only one impurity diffusion layer 17 is formed in the p-type impurity layer 15, two or more may be provided as necessary (two examples are shown in FIG. 3 (C)). It may be formed.

Here, in the impurity diffusion layer 11, a p-type impurity diffusion layer
If the surface concentration of boron 15 is, for example, 2 × 10 ²⁰ / cm ³ , the surface concentration of Ge in the second impurity diffusion layer 17 is 1.
It is preferable to set to 18 × 10 ²¹ / cm ³ . This setting is made based on the following reasons.

Lattice contraction coefficient (latt) due to impurities in silicon crystal lattice
The ice contraction coefficient β is based on the literature (Solid-State Electron
nicS), 15 , 1972, pp. 259 to 264). Where r _sol
Is the atomic radius of the impurity atom, r _si is the atomic radius of the silicon atom, and N is the density of the silicon crystal.

β (cm ³ / atom) = (1−r _sol / r _si ) / N. Therefore, since the r _sol of boron is 0.88 °, the lattice contraction coefficient β _B of silicon due to boron is 5.0 × 10 ⁻²⁴ cm ³ / atom. Become. Also, since the r _sol of germanium is 1.22 °, the lattice contraction coefficient β _Ge of silicon by germanium is −0.85 × 10
^-24 cm ³ / atom. The minus sign in β _Ge indicates that the silicon crystal lattice is expanded.

From these facts, in order to eliminate the contraction and expansion of the silicon crystal lattice due to boron and germanium, the surface concentration of _Ge × β _Ge = the surface concentration of _B × β _B may be used. And the surface temperature of B is 2 × 10
The preferred surface concentration of Ge in the case of ²⁰ / cm ³ is as follows: Ge surface concentration = B surface concentration × β _B / β _Ge = 2 × 10 ²⁰ × 5 / 0.85 ≒ 1.18 × 10 ²¹ / cm ³ . Thus, the concentration of Ge is determined.

Next, in order to deepen the understanding of the present invention, an example in which the impurity diffusion layer 11 of the embodiment is used in an actual semiconductor device will be described.
In this example, an Al wiring is connected to an impurity diffusion layer via a barrier metal.

3 (A) to 3 (D) are process drawings for explanation thereof, and are cross-sectional views showing a state of a sample in a main process in a process of forming an impurity diffusion layer and a wiring.

First, an n-type silicon substrate 13 containing phosphorus as an impurity
Then, boron is introduced by a conventionally known method to form a p-type impurity diffusion layer 15 (FIG. 3A). In addition, a predetermined heat treatment is performed on this sample to activate the p-type impurity diffusion layer 15.

Next, on the n-type silicon substrate 13 on which the p-type impurity diffusion layer 15 has been formed, an interlayer insulating film 21 is formed by a known film forming method, and the interlayer insulating film 21 is further formed by a known photolithography technique and etching technique. Then, a contact hole 23 is formed in a portion opposing a predetermined portion of the p-type impurity diffusion layer 15 (FIG. 3B).

Next, Ge is implanted into a portion of the p-type impurity diffusion layer 15 exposed from the contact hole 23 by a known ion implantation technique. The conditions for the implantation of Ge are such that the Ge concentration as described above can be obtained.

Next, in order to arrange Ge at lattice points of silicon and to adjust the crystallinity of the Ge-implanted portion, the Ge-implanted sample is heat-treated at, for example, a nitrogen atmosphere at 900 ° C. for 30 minutes.
Thereby, the second impurity diffusion layer containing Ge as an impurity
17 are formed at two places in this embodiment (FIG. 3 (C)). Immediately after boron implantation, heat treatment for activating p-type impurity diffusion layer 15 is not performed, and activation of p-type impurity diffusion layer 15 is performed simultaneously by heat treatment for second impurity diffusion layer 17. good.

Next, a barrier metal layer is formed on the sample on which the second impurity diffusion layer 17 has been formed by a known film forming method and patterning technique.
25 and an Al wiring 27 are formed respectively (FIG. 3D).

Next, in order for the contact between the barrier metal layer 25 and the impurity diffusion layer 11 to have low resistance and exhibit ohmic contact,
This sample is heat-treated at a temperature of 400 to 500 ° C. in a nitrogen atmosphere, for example.

In the wiring structure thus obtained as shown in FIG. 3D, the p-type impurity diffusion layer 15 and the barrier metal layer 25
The connection is made via the second impurity diffusion layer 17. As described above, since the silicon lattice is not substantially distorted in the second impurity diffusion layer 17, the barrier metal layer
25 stress, barrier metal layer 25 and impurity diffusion layer 11
The heat generated during the heat treatment to improve the contact between
In this layer 17, dislocation defects due to impurity-induced strain hardly occur. In addition, the second impurity diffusion layer 17 reduces the stress of the barrier metal layer 25 from reaching the p-type impurity diffusion layer 15. Therefore, dislocation defects caused by impurity-induced strain in the entire impurity diffusion layer 11 can be reduced.

In the wiring structure as shown in FIG. 3D, the barrier metal layer 25 comes into contact with the second impurity diffusion layer 17. In the second impurity diffusion layer 17, a Si-Ge compound is formed, and its band gap is narrower than that of silicon since it has an intermediate value between the band gaps of Ge and Si.
Therefore, it can be expected that this wiring structure can provide a lower resistance and better ohmic contact than the case where the barrier metal 25 is brought into contact with silicon.

In the above, the embodiment of the impurity diffusion layer of the present invention has been described. However, the present invention is not limited to the above-described embodiment, and various modifications as described below can be added.

For example, in the above-described embodiment, an example has been described in which dislocation defects caused by impurity-induced strain in a p-type impurity diffusion layer containing boron as an impurity are reduced. However, the present invention relates to an n-type formed on a p-type silicon substrate. It is apparent that the present invention can be applied to a case where dislocation defects caused by impurity-induced strain of an impurity layer are reduced. Explaining in a specific example, when the n-type impurity diffusion layer contains, for example, phosphorus (P) as an impurity, since the atomic radius of phosphorus is 1.1 °, the lattice contraction coefficient β _P of silicon due to phosphorus is 1.2 × 10 ⁻ from the above equation. ²⁴ cm ³ / at
om. Therefore, in this case, since β _P / β _Ge ≒ 1.4, the same effect as in the embodiment can be obtained by implanting Ge into the silicon substrate so that the surface concentration of Ge is 1.4 times the surface concentration of phosphorus. .

When an impurity diffusion layer as shown in FIG. 2 where the plane area of the second impurity diffusion layer is substantially equal to the plane area of the n-type or p-type impurity diffusion layer is applied to the wiring structure of FIG. The diffusion layer may be formed as follows. That is, Ge may be implanted into a silicon substrate shallower than p or n-type impurities before and / or after ion implantation of P-type or n-type impurities before forming an interlayer insulating film. FIG. 4 is a diagram showing this state by a cross section corresponding to FIG. 3 (A).

(Effects of the Invention) As is apparent from the above description, according to the impurity diffusion layer of the present invention, a predetermined depth and a predetermined surface concentration formed by using Ge on the surface of the n-type or p-type impurity diffusion layer. Since the configuration includes the second impurity diffusion layer, the following effects can be expected.

Impurity-induced distortion is less likely to occur in the second impurity diffusion layer. Therefore, even when stress is applied to the second impurity diffusion layer, dislocation defects are unlikely to occur. Therefore, a wiring made of a material having a high stress such as a barrier metal can be connected to the second impurity diffusion layer. Further, when the barrier metal is connected to the second impurity diffusion layer, the second impurity diffusion layer reduces the stress of the barrier metal from being applied to the n-type or p-type impurity diffusion layer. For this reason, dislocation defects due to impurity-induced strain at the junction between the impurity diffusion layer and the wiring are less likely to occur.

Further, since a compound of silicon and Ge is formed in the second impurity diffusion layer and the band gap thereof is narrower than that of silicon, connecting the wiring to the second impurity diffusion layer is lower than connecting the wiring to silicon. Resistance and good ohmic contact are obtained.

[Brief description of the drawings]

1 (A) and 1 (B) are a cross-sectional view and a plan view showing an impurity diffusion layer according to an embodiment, FIG. 2 is a plan view showing an impurity diffusion layer according to another embodiment, and FIG. 3 (A). 4A to 4D are views for explaining an example of using the impurity diffusion layer of the embodiment, and FIG. 4 is a view showing a method of forming the impurity diffusion layer shown in FIG. 11 Impurity diffusion layer of Example 13 n-type silicon substrate 15 Boron-containing p-type impurity diffusion layer 17 Ge-containing second impurity diffusion layer 21 Interlayer insulating film 23 Contact hole 25 ... Barrier metal layer 27 ... Al wiring.

Claims (1)

(57) [Claims] In an n-type or p-type impurity diffusion layer formed on a silicon substrate, germanium (Ge) is contained in the n-type or p-type impurity diffusion layer.
The second impurity diffusion layer formed by using a shallower than the diffusion depth of the n-type or p-type impurity diffusion layer, and
An impurity diffusion layer having a surface concentration represented by the following formula (1) (where β _sol in the formula (1) is a lattice shrinkage coefficient (cm) of silicon due to an n-type or p-type impurity element. ³ / atom), which is given by the following formula (2), and β _Ge in the formula (1) is a lattice contraction coefficient of silicon by germanium (cm ³ / atom), which is given by the following formula (3). Here, in the formulas (2) and (3), r _Si is the atomic radius of silicon, N is the density of the silicon crystal, and r _sol in the formula (2) is an n-type or P-type impurity. It is the atomic radius of the element, and r _Ge in equation (3) is the atomic radius of germanium.) Ge surface concentration = surface concentration of n-type or P-type impurity element × β _sol / β _Ge (1) β _sol = (1-r _sol / r _si ) / N (2) β _Ge = (1-r _Ge / r _si ) / N… (3)