JPS6276326A - Coder and decoder - Google Patents

Abstract

PURPOSE:To use a decoder converting an ADPCM code into a nonlinear PCM code as a coder by providing the 1st - 3rd selectors to the decoder including transcoding processing so as to select the processing order. CONSTITUTION:The 1st selector 1 selecting an input signal and an output signal of a quantization circuit 9 and adding the result to an inverse quantization circuit 2, the 2nd selector 6 selecting the input signal and an output signal of a compression circuit 5 and adding the result to an expansion circuit 7, and the 3rd selector 11 selecting and outputting an output signal of a correction circuit 10 and an output signal of the circuit 9 are provided. In operating the titled device as a decoder, the selectors 1, 6, 11 are controlled into the connecting state shown in dotted lines so as to decode the ADPCM code input signal into the nonlinear PCM code signal. In operating the titled device as a coder, the selectors 1, 6, 11 are controlled reversely and the input signal of the nonlinear PCM code is coded into the ADPCM signal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] 1- A decoder that includes a lance coding process and converts from an ADPCM code to a non-linear PCM code
Utilizing the fact that the encoder includes a function of converting a CM code into an ADP CM code, a selector selects a processing flow and operates as an encoder or a decoder.

[Industrial application field]

The present invention relates to a code decoder that can realize an encoder function of converting a nonlinear PCM code into an ADPCM code and a decoder function of performing the reverse conversion process by controlling a selector.

The audio signal is converted into a non-linear P according to the companding law such as A law or μ law.
A digital switching system is known that converts the code into a CM code and sends it to the line. In order to further compress this non-linear PCM code and improve line efficiency, ADPCM
(Adaptive DifferentialPu
It is also known to convert to a lse Code Modulation (Code Modulation) code. For example, when an audio signal sampled at 8 KHz is converted to a 4-bit ADPCM code, the amount of data becomes 32 K b/s, which can be further compressed than compression using A-law or μ-law. In a communication system that includes such a code system, an encoder and a decoder are required to convert between the non-direct MPCM code and the ADPCM code.

[Conventional technology]

The decoder that converts the ADPCM code into a non-linear PCM code has the configuration shown in FIG.
The M-code input signal I is dequantized by the dequantization circuit 61 to become a reproduction error signal DQ, which is added to the prediction signal SE from the prediction circuit 63 by the adder 62 to yield the reproduction signal SR.

This reproduced signal SR is compressed by a compression circuit 64 to become a non-linear PCM code signal SP, which is applied to an expansion circuit 65 and a correction circuit 68.

The reproduction error signal DQ and reproduction signal SR are also applied to a prediction circuit 63 to form a prediction signal to be used in the next sample. Further, the difference between the signal SLX converted into a linear PCM code by the decompression circuit 65 and the prediction signal SE is obtained in an adder 66, and the signal DX representing the difference is added to a quantization circuit 67.

The nonlinear PCM code signal IX quantized by the quantization circuit 67 is applied to the correction circuit 68, and the ADPCM code input signal ■ and the nonlinear PCM code signal SP produce
A signal SD of the corrected non-linear PCM code is output. The processing performed by the circuits after the decompression circuit 65 is called transcoding processing, and in a system where an encoder and a decoder are connected in series, the transmission characteristics deteriorate due to the accumulation of errors caused by encoding and decoding. In order to prevent this, the correction circuit 68 corrects it.

Further, FIG. 9 shows the configuration of the encoder, in which an input signal S of a non-linear PCM code is converted into a signal SL of a linear PCM code by an expansion circuit 71 and added to an adder 72, and a predicted signal from a prediction circuit 76 is converted to a signal SL of a linear PCM code. The difference with SE is determined and becomes an error signal. This error signal is applied to a quantization circuit 73, quantized, and output as an ADPCM code signal I.

Further, this signal (2) is dequantized by a dequantization circuit 74 to become a reproduced error signal DQ, and this reproduced error signal DQ is added to the prediction signal SE by an adder 75 to become a reproduced signal SR. The reproduction signal SR and reproduction error signal DQ are applied to a prediction circuit 76 to form a prediction signal SE to be used for the next sample.

[Problem that the invention seeks to solve]

The common method is to convert the audio signal into an 8-bit non-linear PCM code using the A-law or μ-law companding law, but as mentioned above, in order to improve line efficiency, There is a method of converting the data into an ADPCM code such as bits and transmitting it.
Conversion with CM code is required. In that case, the decoder shown in FIG. 8 and the encoder shown in FIG. 9 are provided, each of which is configured as an independent circuit,
Moreover, the circuit scale is also relatively large. Therefore, even when integrated circuits are used, it is necessary to manufacture the decoder and encoder separately.

The present invention focuses on the fact that the decoder includes the necessary components as an encoder, and by controlling the processing flow 411, it can be used both as a decoder and as an encoder. The purpose is to

[Means for solving problems]

The code/decoder of the present invention operates as either an encoder or a decoder by controlling the processing flow using a selector. In the decoder including the processing, a first selector 1 selects the input signal and the output signal of the quantization circuit 9 and applies it to the inverse quantization circuit 2, and selects the input signal and the output signal of the compression circuit 5. and a third selector 1 that selects and outputs the output signal of the correction circuit 10 and the output signal of the quantization circuit 9.
1.

When operating as a decoder, the first to third selectors 1 and 6.11 are controlled by an external setting control signal to the connection state shown by the dotted line, and the input signal of the ADP CM code is changed to the input signal of the non-linear PCM code. Decode to signal. When operating as an encoder, the first to third selectors 1, 6.11 are controlled by the setting control signal so that they are in the connection state opposite to the dotted line, and the input signal of the non-linear PCM code is connected to the ADPCM signal. It is encoded into .

[Effect]

In order to operate as a decoder, the first to third selectors 1
．． When 6.11 is controlled to the connection state shown by the dotted line, the input ADPC code signal ■ is applied to the dequantization circuit 2 via the first selector 1, and becomes the reproduction error signal DQ by dequantization. .

This reproduction error signal DQ and the prediction signal SE from the prediction circuit 3
are added by an adder 4 to obtain a reproduced signal SR of the linear PCM code. The reproduced signal SR and the reproduced error signal DQ are added to the prediction circuit 3, and the predicted signal SE of the next sample is
is formed. The reproduced signal SR is compressed by the compression circuit 5 to become a non-linear PCM code signal SP, which is applied to the expansion circuit 7 via the second selector 6.

Expansion circuit 7. Adder 8. Quantization circuit 9 and correction circuit 10
Transcoding processing is performed by the correction circuit 10, and the non-linear PCM code signal SD is outputted as a decoded output signal via the third selector 11.

Also, in order to operate as an encoder, if the first to third selectors 1, 6.11 are controlled to be in the connection state opposite to the dotted line, the input non-linear PCM code signal will be The straight line P is applied to the expansion circuit 7 via the selector 6.
The signal is converted into a CM code signal, the difference from the prediction signal SE from the prediction circuit 3 is obtained by an adder 8, the difference signal is added to a quantization circuit 9, and it is quantized to become an ADPCM code signal. It is output as an encoded output signal via the third selector 11. Further, the ADPCM code signal is applied to the dequantization circuit 2 via the first selector 1, and is dequantized to become a reproduction error signal DQ, which is added to the prediction signal SE from the prediction circuit 3 by the adder 4 and reproduced. The reproduced signal SR and the reproduced error signal DQ are added to the prediction circuit 3 to form a predicted signal for the next sample.

Therefore, by controlling the selector, it can be operated as either a decoder or an encoder.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, and 1.6.
11 is the first. Of the second and third selectors, the first selector 1 selects the input signal and the output signal of the quantization circuit 9 and adds it to the inverse quantization circuit 2, and the second selector 6 , the output signal and input signal of the compression circuit 5 are selected and applied to the expansion circuit 7. Further, the third selector 11 selects the output signal of the quantization circuit 9 and the output signal of the correction circuit 10 and outputs the selected signal.

When operating as a decoder, the first to third selectors 1, 6.11 are controlled to the connection state shown by the dotted line by external setting control signals,
The signal I of the ADPCM code of via 1- is applied to the inverse quantization circuit 2 via the first selector 1. This inverse quantization circuit 2 dequantizes the reproduction error signal DQ, which is added to the prediction signal SE from the prediction circuit 3 in an adder 4 to become a reproduction signal SR of, for example, a 16-bit linear PCM code. . The reproduction error signal DQ and the reproduction signal SR are also applied to a prediction circuit 3 to form a prediction signal for the next sample.

The reproduced signal SR is applied to the compression circuit 5, compressed according to the companding side, and converted into a signal SP of, for example, an 8-bit non-linear PCM code. This signal SP is applied to the decompression circuit 7 via the second selector 6, and is again converted into a linear PCM code signal S L X. This signal SLX is applied to an adder 8, and the difference between it and the prediction signal SE from the prediction circuit 3 is calculated, and the difference signal D Ru.

This non-direct vAP CM code signal IX and the input
In addition, the DPCM code signal I and the nonlinear PCM code signal SP from the compression circuit 5 are applied to a correction circuit IO, and a nonlinear PCM code signal SD corrected to reduce the error is output. , and becomes a decoded output signal via the third selector 11.

When operating as an encoder, the first to third selectors 1, 6.11 are controlled to the connection state opposite to the dotted line, and the configuration of FIG. 1 is changed to the encoder shown in FIG. 9. If the connection configuration is shown to correspond to the above, the configuration shown in FIG. 2 will be obtained.

That is, the first to third selectors 1, 6.11 are restricted to the connection state shown by the chain line. The non-linear PCM code signal S inputted from the outside after ff1l is applied to the decompression circuit 7 via the second selector 6, and is converted into the linear PCM code signal SL. The difference between this signal SL and the prediction signal SE from the prediction circuit 3 is obtained in an adder 8, and the difference signal is added to a quantization circuit 9 and converted into an ADPCM coated signal I. The signal I of this ADPCM code is the third
It becomes an encoded output signal via the selector 11.

Further, the ADPCM code signal (2) is applied to the inverse quantization circuit 2 via the first selector 1, and is applied to the prediction circuit 3 and adder 4 as a reproduced error signal DQ through inverse quantization. The adder 4 adds the reproduced error signal DQ and the prediction signal SE, and outputs the reproduced signal SR, which is sent to the prediction circuit 3.
added to. Therefore, the prediction circuit 3 forms a prediction signal for the next sample using the reproduction signal SR and the reproduction error signal DQ. In this encoder, the compression circuit 5 and the correction circuit 10 are idle.

As mentioned above, by controlling selectors 1 and 6.11,
It can be operated as a decoder or an encoder.

FIG. 3 is a block diagram of another embodiment of the present invention, showing a code decoder capable of time division multiplexing.

In the same figure, 21.30 is an expansion circuit, 22.27.3
1 is an adder, 23.32 is a quantization circuit, 25 is an inverse quantization circuit, 26 is an update circuit, 28 is a prediction circuit, 29 is a compression circuit, 33 is a correction circuit, 24.34 is a selector, 35 is a random access Memory (RAM), 36 is a memory control circuit, 37 is an input/output data path of RAM 35, 38-
47 is a delay circuit.

If an 8 kHz frame is divided into equal parts according to the number of channels for multiplexing, and the divided periods are designated as periods, 32 periods are required to perform multiplexing on 32 channels. Therefore, if the functional blocks of the encoder and decoder are arranged in chronological order so that they have common parts, they are divided into six periods P1 to P6. For example, period P
If the n-th channel is being processed in period P6, then the n-5th channel is being processed in period P6. Each of the delay circuits 38 to 47 has a delay time of one period.

When operating as an encoder, the first selector 24 selects the ADPCM code signal (2) output from the quantization circuit 23 and adds it to the inverse quantization circuit 25 and the update circuit 26, and the third selector 34 Control is performed to select and output the ADPCM code signal I output from the quantization circuit 23 via the delay circuits 43 to 46.

In addition, when operating as a decoder, the first selector 24
is the ADPCM applied through delay circuits 38 and 39.
In addition to the inverse quantization circuit 25 and the update circuit 26 that select the input signal of the code, the third selector 34 is connected to a correction circuit 33.
It is controlled to select and output the signal SD of the non-direct NI'A P CM code output from . The second selector 6 shown in FIGS. 1 and 2 is omitted in FIG. 3 because the expansion circuit, adder, and quantization circuit are provided in duplicate.

Furthermore, in processing the ADP CM code, it is necessary to provide a sample cycle delay in order to use coefficients generated from several samples before to the current sample in processing the next sample. Therefore, the RAM 35 is used as a delay element. As shown in FIG. 4, the address of this RAM 35 consists of a bit configuration of channel designation and symbol designation.
The contents of M35 include, for example, as shown in FIG. 6, symbols SE (prediction signal), Y (step signal), etc. are stored in correspondence with channel designation and symbol designation. The read/write timing of the RAM 35, which is repeated every period wI, is as shown in FIG.

The time slot TS is a time divided into 32 equal periods, and R in R/W (read/write) indicates read and W indicates write. Such control of the RAM 35 is performed by a memory control circuit 36.

In addition, when processing a single channel signal, as in the embodiment shown in FIG. 1, by changing the processing order of the functional blocks using selectors 1 and 6.11, it can be operated as an encoder or a decoder. However, in multi-channel processing using time division multiplexing, the encoder and decoder do not read out the RAM for non-common blocks in the time series, and the symbols are different, so the RAM address is different between the encoder and decoder. You need to choose. Therefore, as shown in Figure 5,
A selector 48 is provided to select channel designation bits in the address of the RAM 35 in correspondence with the encoder and decoder.

When operating as an encoder, selector 2
4 selects the output of the quantization circuit 23, and the selector 34 selects the output of the delay circuit 46 iM. Then, in period P1, non-direct 'faP
The CM code signal is added to the expansion circuit 21, and the linear PC
The predicted signal SE is converted into an M-code signal SL and applied to an adder 22, and the prediction signal SE read out from the RAM 35 is applied to the adder 22 via a data bus 37 to obtain a difference signal. In this case, the time slot TS in FIG.
As shown in FIG. 1, the prediction signal SE of channel n is read out at the read (R) timing, and this prediction signal SE is added to the adder 22 as described above.

In period P2, signal processing of channel n-1 is performed, and the quantization circuit 23 quantizes the difference signal according to the step signal Y and converts it into an ADPCM code signal (2). In this case, time slot T in FIG.
As shown in S2, the step signal Y of channel n-1 is read out at the read (R) timing and applied to the quantization circuit 23. Further, the selector 24 selects the ADPCM code signal I output from the quantization circuit 23.

Also, in period P3, signal processing of channel n-2 is performed, and ADPC of the selected output of the selector 24 is processed.
The M code signal (2) is inversely applied to the slave circuit 25, and is inversely quantized to output a reproduction error signal DQ. Adder 2
7, this reproduction error signal DQ and the prediction signal SE read out from the RAM 35 are added and added to produce the reproduction signal SR.
becomes. In this case, as shown by time slot TS 3 in FIG. 7, channel n-
Two step signals Y are successively outputted and applied to the inverse quantization circuit 25. Although not shown in the figure, the prediction signal SE of channel n-2 is read out at the next timing and sent to the adder 2.
Added to 7.

The update circuit 26 uses the ADPCM code signal ■ to
It is determined whether or not to update the step signal Y, and if the step signal Y is to be updated, the step signal Y of channel n-2 is written at the timing of write <W), as shown by 16 of time slot TS in FIG. It will be crowded. Further, the prediction circuit 28 uses the reproduced error signal DQ and the reproduced signal SR to predict the channel n-
A predicted signal for the next sample after sample 2 is formed, and a predicted signal SE for channel n-2 is written at write (W) timing (not shown).

Also period P4. In period P5, there is no structure used as an encoder, and in period P6, channel n-
A signal with an ADPCM code of 5 is outputted via the selector 34. That is, the signal I of the ADP CM code 4 periods before, quantized by the quantization circuit 23, is sent to the delay circuit 4.
3 to 46, the output is delayed by 4 periods.

When operating as a decoder, the selector 24 selectively outputs the ADPCM code signal output from the delay circuit 39. Therefore, if the signal of channel n is processed in period P1, and the signal of channel n-1 is processed in period P2, then in period P3, as in the case of operating as an encoder, channel n-2
Processing of the ADPCM code signal will be performed, including inverse quantization using the step signal Y, formation of the reproduced signal SR using the reproduced error signal DQ and the prediction signal SE, etc.
The step signal Y is updated and the prediction signal is formed.

Therefore, the read/write timing of the RAM 35 in period P3 is the same as that of the encoder.

In period P4, the reproduced signal S of channel n-3
R is subjected to compression processing, and the compression circuit 29 generates a non-linear PCM code signal SP. Further, the prediction signal SE of channel n-3 by the prediction circuit 28 is written into the RAM 35.

In period P5, the nonlinear PC of channel n-4
The M code signal SP is expanded by an expansion circuit 30 and converted into a linear PCM code signal SLX, which is applied to an adder 31. Also, the prediction signal SE of channel n-4 is stored in the RAM.
35 and added to the adder 31;
A difference signal DX is output from. Prediction signal SE in this case
is read out as the prediction signal SE of channel (n-4), as shown at time slot TS 1 in FIG. That is, when operating as an encoder, the time slot TS
1 is channel n, but when operating as a decoder, it becomes channel n-4, and the channel designation is selected by the selector 48 shown in FIG.

In period P6, the difference signal DX of channel n-5
is applied to the quantization circuit 32, and the step signal Y of channel n-5 is read out from the RAM 35 and applied to the quantization circuit 32, where it is converted into the ADPCM code signal IX. This signal IX and the non-linear PC of channel n-5 in period P4 delayed by one period in the delay circuit 47
The correction circuit 3 receives the M code signal SP and the input ADPCM code signal of channel n-5 delayed by 5 periods.
3 and corrected ADPCM code signal SD
is selectively outputted by the selector 34.

The step signal Y in this case is read out as a step signal of channel (n-5), as shown at time slot TS 2 in FIG. In this case, as before,
2 of time slot TS when operating as an encoder.
was channel n-1, but when operating as a decoder, it becomes channel n-5, and selector 48 in FIG.
The channel designation is selected by .

In addition, we have described the case where the selector 48 is provided to select the address of the RAM 35, but the RAM 35 is accessed separately for blocks that are not common in the time series, and the RAM 35 is accessed separately.
Time division processing can also be performed by selecting the results read from No. 5.

〔Effect of the invention〕

As explained above, the present invention includes first to third selectors 1, 6.1 in a decoder including transcoding processing.
1 and select the processing order, ADPC
It operates as a decoder that converts an M code into a non-linear PCM code or an encoder that converts a non-linear PCM code into an ADPCM code, and since it can be mass-produced as the same type of integrated circuit, it can be used as an encoder. This has the advantage that costs can be reduced compared to the case where the decoder and the decoder are manufactured separately. Furthermore, as shown in FIG. 3, it is also possible to adopt a configuration that performs time-division processing, thereby making it possible to configure an economical code decoder.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a block diagram of the embodiment of the present invention when it operates as an encoder, FIG. 3 is a block diagram of another embodiment of the present invention, and FIG. The figure is RA
Figure 5 is a diagram explaining RAM address selection, Figure 6 is a diagram explaining RAM contents, Figure 7 is a diagram explaining read/write timing, Figure 8 is a block diagram of the decoder, Figure 9 is a diagram explaining the M address.
The figure is a block diagram of an encoder. 1.24 is the first selector, 6 is the second selector, 11
．． 34 is the third selector, 2.25 is the inverse quantization circuit, 3
, 28 is a prediction circuit, 4, 8, 22.27.31 is an adder, 5.29 is a compression circuit, 7.21.30 is an expansion circuit, 9
, 23.32 is a quantization circuit, 10.33 is a correction circuit, 3
5 is a random access memory (RAM), 36 is a memory control circuit, 37 is a data bus, 43 to 47 are delay circuits, and 26 is an update circuit.

Claims (1)

[Claims] In a code decoder having an encoder function for converting a non-linear PCM code into an ADPCM code and a decoder function for converting an ADPCM code into a non-linear PCM code, a transcoding process is performed. The inverse quantization circuit (9) selects the ADPCM code output from the quantization circuit (9) of the decoder including the
A first selector (1) added to the first selector (1) added to the inverse quantization circuit (2), and a linear PCM code formed from the reproduction error signal output from the dequantization circuit (2) and the prediction signal from the prediction circuit (3), ), a second selector (6) which selects the non-linear PCM code output from the compression circuit (5) and the non-linear PCM code inputted from the outside and adds it to the expansion circuit (7); A difference signal between the linear PCM code output from the decompression circuit (7) and the prediction signal from the prediction circuit (3) is added to the quantization circuit (9), and the A output from the quantization circuit (9) is
A code decoder comprising a third selector (11) that selects a DPCM code and an ADPCM code output from a correction circuit (10) that performs transcoding processing.